WO2013147895A2

WO2013147895A2 - Dynamic physical register use threshold adjustment and cross thread stall in multi-threaded processors

Info

Publication number: WO2013147895A2
Application number: PCT/US2012/031710
Authority: WO
Inventors: James D. Hadley; Srikanth T. Srinivasan; Matthew C. Merten; Ravi Rajwar RAJWAR; David G. LIM; Yury N. ILYIN
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2012-03-30
Filing date: 2012-03-30
Publication date: 2013-10-03
Anticipated expiration: 2014-09-30

Description

DYNAMIC PHYSICAL REGISTER USE THRESHOLD ADJUSTMENT AND CROSS THREAD STALL IN

MULTI-THREADED PROCESSORS

BACKGROUND

Technical Field

Embodiments relate to processors. In particular, embodiments relate to multi-threaded processors that allocate physical registers to logical registers for multiple threads.

Background Art

Various multi-threaded processors are known in the arts. The multi-threaded processors commonly include multiple sets of hardware and/or logic that are each operable to serve as a logical processor, processing element, or thread to support a software thread (e.g., operating system code, application code, etc.). Different software threads may be performed concurrently by the multiple logical processors, processing elements, or threads.

Commonly, the threads may share resources, such as, for example, physical registers. By way of example, the physical registers may be used in conjunction with register renaming to avoid unnecessary serialization of software in order to facilitate concurrent parallel execution of the software by the threads and thereby increase performance.

Since the threads share access to the physical registers, a problem may occur if one of the threads ties up too many physical registers. In such a case, there is a chance that another thread may stall at physical register allocation due to not enough physical registers being available for the thread to continue to make forward progress. One known solution to such a problem is to employ a physical register use counter per thread and impose a physical register use threshold below which the physical register use of the thread is enforced.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings:

Figure 1 is a block diagram of an embodiment of a multi-threaded processor suitable for implementing embodiments of the invention.

Figure 2 is a block diagram of an embodiment of logic of a processor to perform out-of- order physical register allocation.

Figure 3 is a block flow diagram of a first embodiment of a method of handling physical register use. Figure 4 is a block flow diagram of a second embodiment of a method of handling physical register use .

Figure 5 is a block diagram of an embodiment of an apparatus to handle physical register use.

Figure 6 is a block diagram of an embodiment of a thread having separate integer and vector physical register use counters, separate integer and vector higher physical register use thresholds, and separate integer and vector lower physical register use thresholds.

Figure 7A is a block diagram illustrating an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the invention.

Figure 7B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the invention.

Figure 8A is a block diagram of a single processor core, along with its connection to the on- die interconnect network and with its local subset of the Level 2 (L2) cache, according to embodiments of the invention.

Figure 8B is an expanded view of part of the processor core in Figure 8A according to embodiments of the invention.

Figure 9 is a block diagram of a processor that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention.

Figure 10 shown is a block diagram of a system in accordance with one embodiment of the present invention.

Figure 11 shown is a block diagram of a first more specific exemplary system in accordance with an embodiment of the present invention.

Figure 12, shown is a block diagram of a second more specific exemplary system in accordance with an embodiment of the present invention.

Figure 13, shown is a block diagram of a system on chip in accordance with an embodiment of the present invention.

Figure 14 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention. Description of the Embodiments

A technical problem with known solutions to avoiding a thread stalling due to not enough physical registers being available is that single, static physical register use thresholds are used. These single, static physical register use thresholds do not account for entrance of a thread into a transitory higher physical register use mode. Some embodiments disclosed herein include different physical register use thresholds, namely a higher physical register use threshold for use when threads are not in transitory higher physical register use mode and a lower physical register use threshold when a thread is in a transitory higher physical register use mode.

In the following description, numerous specific details, such as logic implementations, particular types of processor logic, types and interrelationships of system components, particular orders of operations, and logic partitioning/integration details, are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

Figure 1 is a block diagram of an embodiment of a multi-threaded processor 100 suitable for implementing embodiments of the invention. In one or more embodiments, the processor may be a general-purpose processor. For example, the processor may be a general-purpose processor of the type manufactured by Intel Corporation, of Santa Clara, California, although this is not required. Alternatively, the processor may be a special-purpose processor. Representative examples of suitable special-purpose processors include, but are not limited to, network processors, communications processors, cryptographic processors, graphics processors, co-processors, embedded processors, and digital signal processors (DSPs), to name just a few examples. The processor may be any of various complex instruction set computing (CISC) processors, various reduced instruction set computing (RISC) processors, various very long instruction word (VLIW) processors, various hybrids thereof, or other types of processors. In still other embodiments, the processor may represent a controller (e.g., a microcontroller), or other type of logic circuit capable of processing microcode or microinstructions.

The processor includes at least a first core 101. In some embodiments, the processor may optionally include at least two cores, namely the first core 101 and a second core 102. In some embodiments, the at least two cores may be symmetric cores (e.g., having same configurations, functional units, logic, etc.). In other embodiments, the at least two cores may be asymmetric cores (e.g., having different configurations, functional units, and/or logic). By way of the example, one of the cores may be an out-of-order core while the other is an in-order core, one of the cores may be a general-purpose core and the other core may be a DSP, the cores may execute different instruction sets, etc.

Each core may include one or more logical processors, processing elements, or threads. The logical processors, processing elements, or threads may represent hardware and/or logic to support a software thread (e.g., operating system code, application code, etc.). The logical processors, processing elements, or threads may represent hardware and/or logic that is capable of being independently associated with a software thread. Examples of suitable logical processors, processing elements, or threads include, but are not limited to, a thread unit, a thread slot, a process unit, a context, a context unit, a hardware thread, a core, and/or other hardware and/or logic capable of holding a state, such as an execution state and/or an architectural state.

In the illustrated embodiment, the first core 101 includes a first set of architecture registers 103 A mapped to a first portion of physical registers 109 A and a second set of architecture registers 103B mapped to a second portion of physical registers 109 A. The different sets of architectural registers may allow separate architectural states and/or contexts to be stored. Accordingly, each of the different sets of architecture registers may represent at least a portion of a separate logical processor, processing element, or thread, as described above. Software entities, such as an operating system, potentially view the first core as two separate logical processors, processing elements, or threads that are capable of executing two software threads concurrently. In other embodiments, the first core may include fewer or more threads. The second core may include one or more additional sets of architectural registers each representing an additional separate thread.

A core often refers to logic located on an integrated circuit or die that is capable of maintaining an independent architectural state, in which each independently maintained architectural state is associated with at least some dedicated execution resources. A hardware thread often refers to logic located on an integrated circuit or die that is capable of maintaining an independent architectural state, in which the independently maintained architectural states share access to execution resources. When certain resources are shared and others are dedicated to an architectural state, the distinction between the nomenclature of a core and a hardware thread blurs. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors or threads, where the operating system is able to individually schedule operations on each logical processor.

The illustrated processor includes a few representative types of components commonly found in out-of-order processors. In alternate embodiments, the processor may include additional components (e.g., other types of components found in processors), omit certain of the illustrated components, or a combination thereof. Moreover, while the illustrated processor represents an out- of-order processor, and includes types of components found in out-of-order processors, in another embodiment the processor may be an in-order processor and may omit such components. There are literally numerous different possible combinations and configurations of processor components known in the arts. The scope of the invention is not limited to any known such combination or configuration.

The various components of multi-threaded processors may be fully shared, shared through partitioning, partly shared, or dedicated to particular threads, depending upon the particular type of component and the particular implementation. The illustrated processor shows one example of a way in which the illustrated components may be shared by, partitioned among, and/or dedicated to the different threads. However, other embodiments may share, partition, and/or dedicate the various different components or logic differently. In general, the many different ways of sharing, dedicating, and/or partitioning the logic/components as known in the art are typically suitable.

Referring again to Figure 1, the first core includes a first fetch/decode logic 104A dedicated to the first thread or logical processor, and a second fetch/decode logic 104B dedicated to the second thread or logical processor. These may include instruction pointers, decoders, and the like, which are replicated per thread. The first core also includes a first physical register allocation logic 105 A dedicated to the first thread or logical processor, and a second physical register allocation logic 105B dedicated to the second thread or logical processor. In an alternate embodiment, a physical register allocation logic may be shared by the first and second threads or logical processors and may switch or alternate between allocating for the threads. By way of example, the physical register allocation logic may include a register alias table or other logic operable to perform register renaming. Instruction scheduling logic 106 is shared by the first and second threads or logical processors. By way of example, the instruction scheduling logic may include one or more reservation stations. Execution logic 107 is shared by the first and second threads or logical processors. By way of example, the execution logic may include one or more arithmetic units, arithmetic logic units, logic units, floating point execution units, integer execution units, jump execution units, load execution units, store execution units, or other types of execution units or functional units known in the arts. Reordering/retirement/rollback logic 108 may be shared by the first and second threads or logical processors, partitioned among the first and second threads or logical processors, or a combination thereof. By way of example, the reordering/retirement/rollback logic may include a reorder buffer, a retirement unit, a history table, or other known logic to perform instruction reordering and instruction retirement (e.g., in the case of an out-of-order processor). For example, the reorder buffer may hold execution results for instructions executed out of order by the execution logic and the retirement unit may retire the instructions in-order with the results being accessed from the reorder buffer. The rollback logic is included in the event of speculative execution or processing by the processor. Examples of possible speculative execution include, but are not limited to, speculative branch prediction and speculative transactional execution.

The processor also includes a set of physical registers 109. A first portion of the physical registers 109A are mapped to the first set of architectural registers 103 A, a second portion of the physical registers 109B are mapped to the second set of architectural registers 103B, and a third portion of the physical registers 109C is unallocated/available and available for speculation. The physical register allocation logic of the processor (e.g., the first and second physical register allocation logic 105 A, 105B) may allocate or reserve physical registers from the set of physical registers 109 (e.g., the third portion 109C) when performing register renaming. In this aspect, the physical register allocation logic may include register renaming logic and/or register alias table logic. The allocated physical registers may be used to store execution results associated with the different threads. The physical registers may be mapped to logical registers. The physical register allocation logic may also allocate or reserve resources in the reordering/retirement/rollback logic to hold the results while they are being reordered and/or so that they are available in case a rollback of execution is appropriate (e.g., following a miss-predicated branch, a nuke event, or an aborted transactional execution).

The processor also includes an embodiment of dynamic physical register use threshold adjustment logic 110 that is operable to dynamically adjust a physical register use threshold. In some embodiments, the dynamic physical register use threshold adjustment logic may dynamically reduce a physical register use threshold (e.g., from a higher threshold to a lower threshold) when one or more threads, logical processors, or processing elements attempt to enter a transitory higher physical register use mode (e.g., attempt to perform hardware based transactional execution, attempt to switch between optimized dynamic binary translation and static compilation, etc.). Dynamic physical register use threshold adjustment logic will be discussed further below.

The processor also includes an embodiment of cross thread stall logic 111 that is operable to allow a first thread to stall a second thread. In some embodiments, the cross thread stall logic may be operable to allow a first thread, logical processor, or processing element that is attempting to enter a transitory higher physical register use mode to temporarily stall a second thread, logical processor, or processing element when the second threads physical register use value is not within a threshold (e.g., a lower physical register use threshold more appropriate for the transitory higher physical register use mode). In some embodiments, the first thread may be prevented from entering the transitory higher physical register use mode while the second threads use value is not within the threshold. In some embodiments, often relatively quickly after the first thread stalls the second thread, due in part to instructions of the second thread committing and the associated physical registers being reclaimed, the second threads use value will drop to within the threshold, and the first thread will be permitted to enter the transitory higher physical register use mode.

In some embodiments, the transitory higher physical register use mode may represent hardware based transactional execution. While hardware transactional execution is often used herein as an example of a transitory higher physical register use mode, the scope of the invention is not so limited. Other examples of transitory higher physical register use modes include, but are not limited to, those based on switches between dynamic binary translation and static compilation, swapping in and out sets of architectural registers, switching off threads and/or cores, or the like. Still other transitory higher physical register use modes will be apparent to those skilled in the art and having the benefit of the present disclosure.

Figure 2 is a block diagram of an embodiment of processor logic 200 operable to perform out- of-order physical register allocation. Instructions may be provided to fetch/decode logic 204. The instructions may be from one or more threads. By way of example, the fetch/decode logic may include one or more instruction fetch units and one or more instruction decoders. The fetch/decode logic 204 is coupled with physical register allocation logic 205. By way of example, the physical register allocation logic may include one or more register renaming units, one or more register alias tables, or similar logic. The physical register allocation logic is coupled with available physical registers tracking logic 214. The available physical registers tracking logic is operable to track physical registers of a set of physical registers (e.g., physical registers 109 in Figure 1), which are available for allocation. By way of example, the available physical registers tracking logic may include a physical register free list (also referred to simply as a free list) that maintains a list of physical register file (PRF) entry identifiers.

The physical register allocation logic is operable to allocate available physical registers to logical registers used to store pre-commit results for architectural registers specified by instructions of programs. The physical registers generally are not specified by instructions or visible to programmers. Physical register allocation to logical registers (e.g., in conjunction with register renaming) is often used to avoid unnecessary serialization of program operations imposed by the reuse of architectural registers by those program operations. Computer programs often make extensive use of architectural registers in performing desired operations. The physical register allocation logic may store a mapping of logical registers to corresponding physical registers.

An instruction scheduling logic 206 is coupled with the physical register allocation logic. Decoded instructions (e.g., microinstructions, micro-operations, etc.) from the decoder, together with their allocated physical registers may be provided to and stored in the instruction scheduling. By way of example, the instruction scheduling logic may include one or more reservation stations. The instruction scheduling logic is coupled with execution logic 207. The decoded instructions from the instruction scheduling logic , together with their allocated physical registers, may be provided to the execution logic. In some embodiments, the execution logic includes out-of-order execution logic to execute decoded instructions out-of-order (i.e., not in original program order), although the scope of the invention is not so limited. The execution logic is coupled with the reordering/retirement/rollback logic 208.

Results of execution of the decoded instructions by the execution logic may be provided to and stored or preserved in the reordering/retirement/rollback logic. The physical register allocation logic 205 is also coupled with reordering/retirement/rollback logic 208 and may indicate the allocated physical registers to the reordering/retirement/rollback logic so that the reordering/retirement/rollback logic can keep track of the results of the execution associated with the allocated physical registers. With register renaming, multiple copies of a single register may be active at different states of commitment and/or speculation at a single point in time. Reordering logic and retirement logic of the logic 208 may reorder and retire instructions which were executed out-of-order back into original program order (i.e., in-order). As instructions retire, the committed state of the registers may be updated in a register map that keeps track of the renamed registers. In alternate embodiments, when in-order execution is performed, the reordering logic and retirement logic may optionally be omitted. The reordering/retirement/rollback logic may store or preserve the results so that they are available in case a rollback in execution is appropriate. By way of example, a rollback in execution may be appropriate when a branch miss-prediction has occurred, when a nuke event has occurred, when a speculative transactional execution has been aborted, when it is decided that other speculative execution is to be discarded, etc. That is, the data stored in the reordering/retirement/rollback logic may represent checkpointed information useful to rollback execution to a previous known state.

[0001] As shown, in some embodiments, the reordering/retirement/rollback logic may include transactional execution checkpoint logic 213. In some embodiments, the transactional execution checkpoint logic may be operable to assist with checkpointing of results of execution associated with speculative transactional execution. In some embodiments, this transactional execution checkpoint logic 213 may be used when transactional execution is being performed but may not be used when transactional execution is not being performed.

When results of execution are ready to be committed to architectural state (e.g., the results of the execution are to be stored in architectural registers), physical registers may be reclaimed. The previous physical register overwritten by the instructions begin retired/committed, which are mapped to the same logical register as the instruction being retired/committed, may be de-allocated or reclaimed. A free list may be maintained. When a new physical register is needed, it may be allocated from the free list, and a pointer to the register may be tracked appropriately by the processor. The available physical registers tracking logic 214 is coupled with the reordering/retirement/rollback logic to receive indications of the reclaimed physical registers and is operable to use the information to keep track of the set of available physical registers.

As discussed above, in a multi-threaded processor, the multiple threads or logical processors generally utilize a common set of physical registers. The number of physical registers is fixed/limited. A limited number of physical registers are apportioned among the multiple threads. Commonly each thread needs to have at least a minimum number of physical registers available in order to continue to make forward progress. The particular minimum number of physical registers needed typically depends upon various implementation details (e.g., the particular processor, architecture, pipeline, etc.). By way of example, this minimum number of physical registers needed may include a number of physical registers sufficient to hold the architectural state and/or execution state of the thread (e.g., the architecturally visible registers, flags, other architectural state of the thread, etc.), a number of physical registers sufficient to get one or more new instructions (e.g., microinstructions) through the pipeline, etc. If the minimum number of physical registers needed is not available for a thread, for example if too many of the physical registers have already been allocated for other hogging threads, then the needy thread may not be able to make forward progress and may stall. This is generally undesirable. As one example, suppose there are 200 physical registers total, a first thread needs a minimum of 50 physical registers to make forward progress, and a second thread is using more than 160 physical registers, there are not enough physical registers remaining for the first thread to have its minimum number of 50 physical registers (i.e., only 40 = (200-160) physical registers are unallocated) and accordingly the first thread may stall.

In some embodiments of the invention, physical register allocation to threads may take into account whether or not one or more threads are attempting to enter a transitory higher physical register use mode (e.g., are attempting transactional execution). In some embodiments of the invention, different (e.g., lower or more restrictive) physical register use thresholds are enforced when at least one thread is attempting to enter such a transitory higher physical register use mode, as compared to when no threads are attempting to enter such a transitory higher physical register use mode. These lower or more restrictive thresholds may reflect that the minimum numbers of physical registers needed for a thread to continue to make forward progress may increase during these transitory higher physical register use modes. For example, instead of the first thread needing a minimum of 50 physical registers, as in the example above, it may need an additional 20 physical registers due to the transitory higher physical register use mode resulting in a need for a total of 70 physical registers to continue to make forward progress. As a result, more physical registers should be left available for allocation among the threads instead of being overly allocated to any given thread, in order to prevent or at least reduce the chances of a thread being stalled and/or not being able to continue to make forward progress due to lack of available physical registers.

To further illustrate certain concepts, consider further the example of hardware based transactional execution. In some embodiments, the transactional execution may involve extended speculative execution than that typically found in out-of-order processors, branch predicting processors (e.g., beyond the depth of a reorder buffer). A greater number of results of execution may need to be preserved in the event a rollback of execution is appropriate (e.g., a rollback to a state at the start of the extended speculative execution). The number of results of execution that may need to be preserved may be based on the number of checkpoints of architectural state. Additional execution result storage/preservation logic (e.g., transactional execution checkpoint logic 213 in Figure 2) may be included to supplant the logic commonly used without transactional execution (e.g., reorder buffers, etc.) in order to preserve the execution results associated with the extended speculative execution. In some embodiments, this additional execution result storage/preservation logic may be used when transactional execution is performed, but not used when transactional execution is not being performed. Use of this additional logic, in some embodiments, may increase the minimum numbers of physical registers needed for one or more threads to continue to make forward progress. Operating within transactional execution may represent an embodiment of a transitory higher physical register use mode. Not operating in transactional execution may represent a contrasting lower physical register use mode.

As another example, in some embodiments, lower and higher physical register use modes may be encountered when switching between dynamic binary translation and static compilation. In one mode, a dynamic binary translator may be used to optimize or improve program code being executed by a processor based on dynamic information. In some embodiments, more checkpointing type information may need to be preserved due to a more speculative aspect of the dynamic optimizations. Accordingly, a mode in which the dynamic binary translator is being used may represent an embodiment of a higher physical register use mode. However, sometimes it may be desirable to switch from performing dynamic binary translation to performing static compilation. For example, this may be the case when the dynamic binary translation and/or the optimizations are not safe, not reliable, or have some other perceived drawback. A switch may be made to a mode in which a static compiled code is used. The performance or other improvements may not be achieved. Lower physical register use may be achieved. Accordingly, a mode in which the static compiler is being used may represent an embodiment of a lower physical register use mode.

Figure 3 is a block flow diagram of an embodiment of a method 320 of dynamically reducing a physical register use threshold of a second thread based on a determination that a first thread is attempting to enter a transitory higher physical register use mode, and preventing the first thread from entering the transitory higher physical register use mode based on a determination that a physical register use value of the second thread is not within the reduced physical register use threshold.

A determination is made that the first thread is attempting to enter the transitory higher physical register use mode, at block 321. In some embodiments, the transitory higher physical register use mode represents hardware based transactional execution. By way of example, determining that the first thread is attempting to enter transactional execution may include examining a bit, counter or flag set when transactional execution entrance is attempted, receiving an indication (e.g., from a decoder) that an instruction of the first thread indicates (e.g., has an opcode that indicates) a start of transactional execution. In other embodiments, the transitory higher physical register use mode represents a switch between dynamic binary translation and static compilation.

A physical register use threshold of the second thread is reduced from a higher physical register use threshold to a lower physical register use threshold, at block 322. In some embodiments, the threshold is reduced in response to determining that the first thread is attempting to enter the transitory higher physical register use mode (e.g., attempting to perform transactional execution). The minimum number of physical registers needed to ensure that the threads continue to make forward progress outside of the transitory higher physical register use mode may be insufficient to ensure that the threads make forward progress when the first thread enters the transitory higher physical register use mode. Accordingly, to help safeguard against unforeseen stalls, the lower physical register use thresholds may be set and used. As used herein, the terms "lower physical register use threshold" and "higher physical register use threshold" are relative terms (i.e., relative to one another), not absolute terms. In other words, the lower threshold is lower than the higher threshold. As one particular example, reducing the threshold may be by an amount between about 10 to about 30, or from about 15 to about 25, physical registers, although the scope of the invention is not so limited.

A determination is made that a physical register use value of the second thread is not within the lower physical register use threshold, at block 323. By way of example, the physical register use value may be a counter value from physical register use counter of the second thread. For example, each thread may have a physical register use counter that counts a number of physical registers that particular thread is using. As used herein, a value "within" a threshold encompasses the value being less than the threshold, the value being less than or equal to the threshold, the value being not greater than the threshold, etc., depending upon how the threshold is used in the particular implementation.

The first thread is prevented from entering the transitory higher physical register use mode (e.g., performing the transactional execution), at block 324. In some embodiments, the first thread is prevented from entering the transitory higher physical register use mode while the physical register use value of the second thread is not within the lower physical register use threshold. In some embodiments, preventing the first thread from entering the transitory higher physical register use mode may include temporarily stalling the first thread so long as the use value is not within the lower threshold. Advantageously, preventing the first thread from entering the transitory higher physical register use mode, while the physical register use value of the second thread is not within the lower physical register use threshold, may help to prevent, or at least reduce the likelihood of, the first thread stalling. The lower physical register use thresholds may take into account a change to the minimum number of physical registers needed to ensure that the first thread continues to make forward progress when the first thread is operating in the transitory higher physical register use mode, which may be different than when it is not.

Allocation of additional physical registers to the second thread is optionally prevented, at block 325. In some embodiments, the second thread may be stalled at allocation. In some embodiments, allocation of additional physical registers to the second thread is prevented while the physical register use value of the second thread is not within the lower physical register use threshold and so long as the first thread is still attempting to enter the transitory higher physical register use mode. In some embodiments, instructions of the second thread are allowed to commit and free physical registers so that the physical register use value of the second thread may decrease (e.g., decrease to within the lower threshold).

In some embodiments, such preventing of allocation may represent an embodiment of a cross- thread stall in which the first thread stalls the second thread temporarily while the use value of the second thread is allowed to reduce to below the lower threshold so that the first thread can safely enter the transitory higher physical register use mode with less risk of stalling due to physical register starvation. For example, a thread attempting to perform transactional execution may stall the other thread whose use value is at a level where there is a risk of physical register starvation if the first thread enters transactional execution. Commonly, due to the high instruction processing speed of modern processors, the use value of the cross stalled thread quickly decreases below the lower threshold. Consequently, a brief cross thread stall generally allows the first thread to again attempt to perform the transactional execution within a brief period of time, and since the use value is now within the threshold be allowed to perform the transactional execution now under conditions in which enough physical registers are available to avoid a more serious stall due to lack of physical registers.

Alternatively, in some embodiments, if the first thread is no longer attempting to perform transactional execution, it may be determined to increase the physical register use threshold back to the higher physical register use threshold, and then allow allocation of physical registers so long as the use value is within the higher threshold. In yet another embodiment, rather than preventing allocation of physical registers to the second thread, the first thread may merely be prevented from entering the transitory higher physical register use mode during times when the use value of the second thread is not within the lower threshold. In some embodiments, the method may loop back to block 321. Another option, in one embodiment, is to operate at the low threshold all the time (whether or not any thread is doing transactional execution or operating in a transitory higher physical register use mode), although this may tend to reduce performance.

Figure 4 is a block flow diagram of a detailed embodiment of a method 440 of dynamically adjusting physical register use thresholds of threads based on whether or not a thread is attempting to perform transactional execution, and preventing the thread from performing the transactional execution when a physical register use value is not within a physical register use threshold. While the method is illustrated for transactional execution, it also applies more generally to other types of transitory higher physical register use modes.

Physical register use thresholds for each of a plurality of threads are optionally initialized to higher physical register use thresholds, at block 421. This is optional not required. A determination is made whether any of the threads are attempting to perform a transactional execution, at block 442. If none of the threads are attempting to perform the transactional execution (i.e., "no" is the determination at block 442), then the method advances to block 443. At block 443, the physical register use thresholds for the threads are set to the higher physical register use thresholds.

A determination is made whether physical register use values of the plurality of threads are within the higher physical register use thresholds, at block 444. If the physical register use values of the threads are within the higher physical register use thresholds (i.e., "yes" is the determination at block 444), then the method advances to block 445. At block 445, physical register allocation to the threads is allowed. In some embodiments, the method then returns from block 445 to block 442. Alternatively, if one or more physical register use values of one or more of the threads are not within the higher physical register use thresholds (i.e., "no" is the determination at block 444), then the method advances to block 446. At block 446, physical register allocation to the thread(s) whose physical register use value(s) are not within the higher physical register use threshold(s) is prevented, while allowing instructions of the thread(s) to retire or commit. In some embodiments, the method returns from block 446 to block 442.

Referring again to block 442, if at least one of the threads is attempting to perform a transactional execution (i.e., "yes" is the determination at block 442), then the method advances to block 447. At block 447, the physical register use thresholds for one or more other threads, which are not attempting to perform the transactional execution, are set to lower physical register use thresholds. For example, if a first thread is attempting to perform a transactional execution, then a physical register use threshold of a second thread may be reduced from a higher physical register use threshold to a lower physical register use threshold.

A determination is made based on a comparison whether one or more physical register use values of the one or more other threads, which are not attempting to perform the transactional execution, are within the lower physical register use threshold(s), at block 448. By way of example, the physical register use values may be counter values from physical register use counters. If the physical register use value(s) of the other thread(s) are all within the lower physical register use threshold(s) (i.e., "yes" is the determination at block 448), then the method advances to block 449. At block 449, the thread attempting to perform the transactional execution is allowed to perform the transactional execution. At block 450, physical register allocation to the plurality of threads is allowed. In some embodiments, the method advances from block 450 to block 442.

Refer again to block 448. If one or more physical register use values of the one or more other threads, which are not attempting to perform the transactional execution, are not within the lower physical register use threshold(s) (i.e., "no" is the determination at block 448), then the method advances to block 451. At block 451 , the thread attempting to perform the transactional execution is prevented from performing the transactional execution, while the physical register use value(s) of the other thread(s) are not within the lower physical register use threshold(s).

[0002] Advantageously, this may help to prevent, or at least reduce the likelihood of, one or more threads stalling and/or a thread not in transactional execution stalling a thread in transactional execution. If instead the thread were allowed to perform transactional execution, for example, a load lock operation of the thread in transactional execution may set a lock in progress bit when the load lock operation retires. Another thread not in transactional execution may attempt a load lock operation at retirement, but may stall on the lock in progress bit set by the thread in transactional execution. The lock in progress bit can be reset only when the store unlock operation of the thread in transactional execution retires. However, this store unlock operation may not be able to retire because the thread in transactional execution may be stalled at allocation due to insufficient physical registers to maintain forward progress. The reason for the allocation stall of the thread in transactional execution could be that the other thread not in transactional execution may be hogging an inappropriately high number of physical registers. Since the load lock operation of the other thread not in transactional execution is unable to retire because of being blocked by the lock in progress bit, this inhibits freeing of physical registers. In this case, both threads may become stalled and not necessarily for a short period of time.

At block 452, physical register allocation to the thread(s) whose physical register use value(s) are not within the lower physical register use threshold(s) may optionally be prevented, while allowing instructions of the thread(s) to retire or commit, although this is not required. Allowing the instructions of the thread(s) to retire or commit helps to free the physical registers and reduce the physical register use value(s) for the thread(s). At some point, when the physical register allocation is prevented to the thread(s) whose physical register use value(s) are not within the lower thresholds, the physical register use value(s) for those thread(s) will continue to decrease, as instructions from those thread(s) retire or commit, until the value(s) are within the lower thresholds. This may allow the thread that had attempted to perform the transactional execution to retry the transaction execution and be permitted to perform the transactional execution (e.g., in a subsequent determination at block 448). Alternatively, in another embodiment, the thread attempting to perform the transactional execution may merely be prevented from performing the transactional execution, while the physical register use value(s) are not within the lower physical register use threshold(s), rather than preventing physical register allocation to the thread(s) whose value(s) are not within the lower threshold(s). In some embodiments, the method advances from block 452 to block 442.

Figure 5 is a block diagram of an embodiment of an apparatus 500 to handle physical register use. The apparatus may be included in a multi-threaded processor. The apparatus includes a first thread 503A and a second thread 503B. The first thread attempts to enter a transitory higher physical register use mode (e.g., to perform hardware based transactional execution). The first thread is coupled with a status 572. The status may represent a bit, a counter, a flag, or other logic or state that may be altered (e.g., a bit may be set) to indicate that the first thread is attempting to enter a transitory higher physical register use mode.

Threshold adjustment logic 570 is operable to observe, or be informed, that the first thread is attempting to enter the transitory higher physical register use mode. As shown, in one embodiment, the threshold adjustment logic may be coupled with the status 572 and may monitor alteration of the status as an indication of whether or not the first thread is attempting to enter the transitory higher physical register use mode. The threshold adjustment logic is operable to reduce a physical register use threshold 569 of the second thread from a higher physical register use threshold 567 to a lower physical register use threshold 568 in response to the first thread is attempting to enter the transitory higher physical register use mode.

Threshold comparison logic 571 is coupled with the physical register use threshold 569. The threshold comparison logic is also coupled with a physical register use counter 565 of the second thread. The threshold comparison logic is operable to determine that a physical register use value of the second thread, for example a counter value of the physical register use counter of the second thread, is not within the lower physical register use threshold.

The first thread includes first thread stall logic 574. The threshold comparison logic 571 is coupled with the first thread stall logic. The threshold comparison logic is operable to stall the first thread through the first thread stall logic. The first thread stall logic represents an embodiment of prevention logic that is operable to prevent the first thread from entering the transitory higher physical register use mode, while the physical register use value of the second thread is not within the lower physical register use threshold.

In some embodiments, the threshold comparison logic 571 may also stall the second thread. The second thread includes second thread stall logic 573. The threshold comparison logic is coupled with the second thread stall logic and is operable to stall the second thread while the physical register use value of the second thread is not within the lower physical register use threshold, and while allowing instructions of the second thread to commit. Such a stall represents an embodiment of a cross thread stall as described elsewhere herein. Figure 6 is a block diagram of a thread 603 having separate integer and vector physical register use counters 6651, 665V, separate integer and vector higher physical register use thresholds 6671, 667V, and separate integer and vector lower physical register use thresholds 6681, 668V. Such separate counters and thresholds may be appropriate, for example, when one set of physical registers is dedicated to integer registers and another set of physical registers is dedicated to vector registers. Alternatively, in another embodiment, a set of physical registers may be shared by integer and vector registers. In such an embodiment, a combined integer and vector physical register use counter, a combined integer and vector higher physical register use threshold, and a combined integer and vector lower physical register use threshold may be used.

Exemplary Core Architectures, Processors, and Computer Architectures

Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: 1) a general purpose in-order core intended for general-purpose computing; 2) a high performance general purpose out-of-order core intended for general-purpose computing; 3) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU including one or more general purpose in-order cores intended for general- purpose computing and/or one or more general purpose out-of-order cores intended for general- purpose computing; and 2) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: 1) the coprocessor on a separate chip from the CPU; 2) the coprocessor on a separate die in the same package as a CPU; 3) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and 4) a system on a chip that may include on the same die the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures.

Exemplary Core Architectures

In-order and out-of-order core block diagram

Figure 7A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the invention. Figure 7B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the invention. The solid lined boxes in Figures 7A-B illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

In Figure 7A, a processor pipeline 700 includes a fetch stage 702, a length decode stage 704, a decode stage 706, an allocation stage 708, a renaming stage 710, a scheduling (also known as a dispatch or issue) stage 712, a register read/memory read stage 714, an execute stage 716, a write back/memory write stage 718, an exception handling stage 722, and a commit stage 724.

Figure 7B shows processor core 790 including a front end unit 730 coupled to an execution engine unit 750, and both are coupled to a memory unit 770. The core 790 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core 790 may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.

The front end unit 730 includes a branch prediction unit 732 coupled to an instruction cache unit 734, which is coupled to an instruction translation lookaside buffer (TLB) 736, which is coupled to an instruction fetch unit 738, which is coupled to a decode unit 740. The decode unit 740 (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit 740 may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core 790 includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in decode unit 740 or otherwise within the front end unit 730). The decode unit 740 is coupled to a rename/allocator unit 752 in the execution engine unit 750. The execution engine unit 750 includes the rename/allocator unit 752 coupled to a retirement unit 754 and a set of one or more scheduler unit(s) 756. The scheduler unit(s) 756 represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s) 756 is coupled to the physical register file(s) unit(s) 758. Each of the physical register file(s) units 758 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point,, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit 758 comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s) 758 is overlapped by the retirement unit 754 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit 754 and the physical register file(s) unit(s) 758 are coupled to the execution cluster(s) 760. The execution cluster(s) 760 includes a set of one or more execution units 762 and a set of one or more memory access units 764. The execution units 762 may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s) 756, physical register file(s) unit(s) 758, and execution cluster(s) 760 are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster - and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) 764). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order. The set of memory access units 764 is coupled to the memory unit 770, which includes a data TLB unit 772 coupled to a data cache unit 774 coupled to a level 2 (L2) cache unit 776. In one exemplary embodiment, the memory access units 764 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 772 in the memory unit 770. The instruction cache unit 734 is further coupled to a level 2 (L2) cache unit 776 in the memory unit 770. The L2 cache unit 776 is coupled to one or more other levels of cache and eventually to a main memory.

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline 700 as follows: 1) the instruction fetch 738 performs the fetch and length decoding stages 702 and 704; 2) the decode unit 740 performs the decode stage 706; 3) the rename/allocator unit 752 performs the allocation stage 708 and renaming stage 710; 4) the scheduler unit(s) 756 performs the schedule stage 712; 5) the physical register file(s) unit(s) 758 and the memory unit 770 perform the register read/memory read stage 714; the execution cluster 760 perform the execute stage 716; 6) the memory unit 770 and the physical register file(s) unit(s) 758 perform the write back/memory write stage 718; 7) various units may be involved in the exception handling stage 722; and 8) the retirement unit 754 and the physical register file(s) unit(s) 758 perform the commit stage 724.

The core 790 may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, CA; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, CA), including the instruction(s) described herein. In one embodiment, the core 790 includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), thereby allowing the operations used by many multimedia applications to be performed using packed data.

It should be understood that the core may support multithreading (executing two or more parallel sets of operations or threads), and may do so in a variety of ways including time sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof (e.g., time sliced fetching and decoding and simultaneous multithreading thereafter such as in the Intel® Hyperthreading technology). While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes separate instruction and data cache units 734/774 and a shared L2 cache unit 776, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (LI) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor.

Specific Exemplary In- Order Core Architecture

Figures 8A-B illustrate a block diagram of a more specific exemplary in-order core architecture, which core would be one of several logic blocks (including other cores of the same type and/or different types) in a chip. The logic blocks communicate through a high-bandwidth interconnect network (e.g., a ring network) with some fixed function logic, memory I/O interfaces, and other necessary I/O logic, depending on the application.

Figure 8A is a block diagram of a single processor core, along with its connection to the on- die interconnect network 802 and with its local subset of the Level 2 (L2) cache 804, according to embodiments of the invention. In one embodiment, an instruction decoder 800 supports the x86 instruction set with a packed data instruction set extension. An LI cache 806 allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit 808 and a vector unit 810 use separate register sets (respectively, scalar registers 812 and vector registers 814) and data transferred between them is written to memory and then read back in from a level 1 (LI) cache 806, alternative embodiments of the invention may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).

The local subset of the L2 cache 804 is part of a global L2 cache that is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache 804. Data read by a processor core is stored in its L2 cache subset 804 and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 804 and is flushed from other subsets, if necessary. The ring network ensures coherency for shared data. The ring network is bi-directional to allow agents such as processor cores, L2 caches and other logic blocks to communicate with each other within the chip. Each ring data-path is 1012-bits wide per direction.

Figure 8B is an expanded view of part of the processor core in Figure 8A according to embodiments of the invention. Figure 8B includes an LI data cache 806A part of the LI cache 804, as well as more detail regarding the vector unit 810 and the vector registers 814. Specifically, the vector unit 810 is a 16-wide vector processing unit (VPU) (see the 16-wide ALU 828), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit 820, numeric conversion with numeric convert units 822A-B, and replication with replication unit 824 on the memory input. Write mask registers 826 allow predicating resulting vector writes.

Processor with integrated memory controller and graphics

Figure 9 is a block diagram of a processor 900 that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention. The solid lined boxes in Figure 9 illustrate a processor 900 with a single core 902A, a system agent 910, a set of one or more bus controller units 916, while the optional addition of the dashed lined boxes illustrates an alternative processor 900 with multiple cores 902A-N, a set of one or more integrated memory controller unit(s) 914 in the system agent unit 910, and special purpose logic 908.

Thus, different implementations of the processor 900 may include: 1) a CPU with the special purpose logic 908 being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores 902A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); 2) a coprocessor with the cores 902A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores 902A-N being a large number of general purpose in-order cores. Thus, the processor 900 may be a general- purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor 900 may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS. The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units 906, and external memory (not shown) coupled to the set of integrated memory controller units 914. The set of shared cache units 906 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit 912 interconnects the integrated graphics logic 908, the set of shared cache units 906, and the system agent unit 910/integrated memory controller unit(s) 914, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units 906 and cores 902-A-N.

In some embodiments, one or more of the cores 902A-N are capable of multi-threading. The system agent 910 includes those components coordinating and operating cores 902A-N. The system agent unit 910 may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores 902A-N and the integrated graphics logic 908. The display unit is for driving one or more externally connected displays.

The cores 902A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 902A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.

Exemplary Computer Architectures

Figures 10-13 are block diagrams of exemplary computer architectures. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.

Referring now to Figure 10, shown is a block diagram of a system 1000 in accordance with one embodiment of the present invention. The system 1000 may include one or more processors 1010, 1015, which are coupled to a controller hub 1020. In one embodiment the controller hub 1020 includes a graphics memory controller hub (GMCH) 1090 and an Input/Output Hub (IOH) 1050 (which may be on separate chips); the GMCH 1090 includes memory and graphics controllers to which are coupled memory 1040 and a coprocessor 1045; the IOH 1050 is couples input/output (I/O) devices 1060 to the GMCH 1090. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory 1040 and the coprocessor 1045 are coupled directly to the processor 1010, and the controller hub 1020 in a single chip with the IOH 1050.

The optional nature of additional processors 1015 is denoted in Figure 10 with broken lines. Each processor 1010, 1015 may include one or more of the processing cores described herein and may be some version of the processor 900.

The memory 1040 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 1020 communicates with the processor(s) 1010, 1015 via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection 1095.

In one embodiment, the coprocessor 1045 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub 1020 may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources 1010, 1015 in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

In one embodiment, the processor 1010 executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor 1010 recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor 1045. Accordingly, the processor 1010 issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor 1045. Coprocessor(s) 1045 accept and execute the received coprocessor instructions.

Referring now to Figure 11, shown is a block diagram of a first more specific exemplary system 1100 in accordance with an embodiment of the present invention. As shown in Figure 11, multiprocessor system 1100 is a point-to-point interconnect system, and includes a first processor 1170 and a second processor 1180 coupled via a point-to-point interconnect 1150. Each of processors 1170 and 1180 may be some version of the processor 900. In one embodiment of the invention, processors 1170 and 1180 are respectively processors 1010 and 1015, while coprocessor 1138 is coprocessor 1045. In another embodiment, processors 1170 and 1180 are respectively processor 1010 coprocessor 1045.

Processors 1170 and 1180 are shown including integrated memory controller (IMC) units 1172 and 1182, respectively. Processor 1170 also includes as part of its bus controller units point- to-point (P-P) interfaces 1176 and 1178; similarly, second processor 1180 includes P-P interfaces 1186 and 1188. Processors 1170, 1180 may exchange information via a point-to-point (P-P) interface 1150 using P-P interface circuits 1178, 1188. As shown in Figure 11, IMCs 1172 and 1182 couple the processors to respective memories, namely a memory 1132 and a memory 1134, which may be portions of main memory locally attached to the respective processors.

Processors 1170, 1180 may each exchange information with a chipset 1190 via individual P-P interfaces 1152, 1154 using point to point interface circuits 1176, 1194, 1186, 1198. Chipset 1190 may optionally exchange information with the coprocessor 1138 via a high-performance interface 1139. In one embodiment, the coprocessor 1138 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

A shared cache (not shown) may be included in either processor or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.

Chipset 1190 may be coupled to a first bus 1116 via an interface 1196. In one embodiment, first bus 1116 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present invention is not so limited.

As shown in Figure 11, various I/O devices 1114 may be coupled to first bus 1116, along with a bus bridge 1118 which couples first bus 1116 to a second bus 1120. In one embodiment, one or more additional processor(s) 1115, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus 1116. In one embodiment, second bus 1120 may be a low pin count (LPC) bus. Various devices may be coupled to a second bus 1120 including, for example, a keyboard and/or mouse 1122, communication devices 1127 and a storage unit 1128 such as a disk drive or other mass storage device which may include instructions/code and data 1130, in one embodiment. Further, an audio I/O 1124 may be coupled to the second bus 1120. Note that other architectures are possible. For example, instead of the point-to-point architecture of Figure 11, a system may implement a multi-drop bus or other such architecture.

Referring now to Figure 12, shown is a block diagram of a second more specific exemplary system 1200 in accordance with an embodiment of the present invention. Like elements in Figures 11 and 12 bear like reference numerals, and certain aspects of Figure 11 have been omitted from Figure 12 in order to avoid obscuring other aspects of Figure 12.

Figure 12 illustrates that the processors 1170, 1180 may include integrated memory and I/O control logic ("CL") 1172 and 1182, respectively. Thus, the CL 1172, 1182 include integrated memory controller units and include I/O control logic. Figure 12 illustrates that not only are the memories 1132, 1134 coupled to the CL 1172, 1182, but also that I/O devices 1214 are also coupled to the control logic 1172, 1182. Legacy I/O devices 1215 are coupled to the chipset 1190.

Referring now to Figure 13, shown is a block diagram of a SoC 1300 in accordance with an embodiment of the present invention. Similar elements in Figure 9 bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. In Figure 13, an interconnect unit(s) 1302 is coupled to: an application processor 1310 which includes a set of one or more cores 202A-N and shared cache unit(s) 906; a system agent unit 910; a bus controller unit(s) 916; an integrated memory controller unit(s) 914; a set or one or more coprocessors 1320 which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit 1330; a direct memory access (DMA) unit 1332; and a display unit 1340 for coupling to one or more external displays. In one embodiment, the coprocessor(s) 1320 include a special -purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the invention may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Program code, such as code 1130 illustrated in Figure 11, may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that has a processor, such as, for example; a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

The program code may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.

One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as "IP cores" may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.

Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk readonly memories (CD-ROMs), compact disk rewritable's (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.

Accordingly, embodiments of the invention also include non-transitory, tangible machine- readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.

Emulation (including binary translation, code morphing, etc.)

In some cases, an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction to one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on processor, off processor, or part on and part off processor.

Figure 14 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 14 shows a program in a high level language 1402 may be compiled using an x86 compiler 1404 to generate x86 binary code 1406 that may be natively executed by a processor with at least one x86 instruction set core 1416. The processor with at least one x86 instruction set core 1416 represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core or (2) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. The x86 compiler 1404 represents a compiler that is operable to generate x86 binary code 1406 (e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one x86 instruction set core 1416. Similarly, Figure 14 shows the program in the high level language 1402 may be compiled using an alternative instruction set compiler 1408 to generate alternative instruction set binary code 1410 that may be natively executed by a processor without at least one x86 instruction set core 1414 (e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, CA and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, CA). The instruction converter 1412 is used to convert the x86 binary code 1406 into code that may be natively executed by the processor without an x86 instruction set core 1414. This converted code is not likely to be the same as the alternative instruction set binary code 1410 because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter 1412 represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code 1406.

All optional features of the above described apparatus may also be implemented with respect to the methods described herein. Moreover, the apparatus may implement all optional features of the previously described methods. It is to be appreciated that the previously described methods may also be performed by either the same or different apparatus, and that the apparatus may perform either the same or different methods.

In the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiments of the invention. It will be apparent however, to one skilled in the art, that one or more other embodiments may be practiced without some of these specific details. The particular embodiments described are not provided to limit the invention but to illustrate it. The scope of the invention is not to be determined by the specific examples provided above but only by the claims below. In other instances, well-known circuits, structures, devices, and operations have been shown in block diagram form or without detail in order to avoid obscuring the understanding of the description. Where considered appropriate, reference numerals or terminal portions of reference numerals have been repeated among the figures to indicate corresponding or analogous elements, which may optionally have similar characteristics. Various operations and methods have been described. Some of the methods have been described in a basic form in the flow diagrams, but operations may optionally be added to and/or removed from the methods. In addition, while the flow diagrams show a particular order of the operations according to example embodiments, it is to be understood that that particular order is exemplary. Alternate embodiments may optionally perform the operations in different order, combine certain operations, overlap certain operations, etc. Many modifications and adaptations may be made to the methods and are contemplated. Certain operations may be performed by hardware components. The operations may also optionally be performed by a combination of hardware and software.

One or more embodiments includes an article of manufacture (e.g., a computer program product) that includes a machine-accessible and/or machine-readable medium. The medium may include, a mechanism that provides, for example stores or transmits, information in a form that is accessible and/or readable by the machine. The machine-accessible and/or machine-readable medium may provide, or have stored thereon, one or more or a sequence of instructions and/or data structures that if executed by a machine causes or results in the machine performing, and/or causes the machine to perform, one or more or a portion of the operations or methods or the techniques shown in the figures disclosed herein.

In one embodiment, the machine-readable medium may include a tangible non-transitory machine-readable storage media. For example, the tangible non-transitory machine-readable storage media may include a floppy diskette, an optical storage medium, an optical disk, a CD-ROM, a magnetic disk, a magneto-optical disk, a read only memory (ROM), a programmable ROM

(PROM), an erasable-and-programmable ROM (EPROM), an electrically-erasable-and- programmable ROM (EEPROM), a random access memory (RAM), a static-RAM (SRAM), a dynamic-RAM (DRAM), a Flash memory, a phase-change memory, or a combinations thereof. The tangible medium may include one or more solid or tangible physical materials, such as, for example, a semiconductor material, a phase change material, a magnetic material, etc.

Examples of suitable machines include, but are not limited to, computer systems, desktops, laptops, notebooks, netbooks, nettops, Mobile Internet devices (MIDs), network devices, routers, switches, cellular phones, media players, and other electronic devices having one or more processors or other instruction execution devices. Such electronic devices typically include one or more processors coupled with one or more other components, such as one or more storage devices (non- transitory machine-readable storage media), user input/output devices (e.g., a keyboard, a touchscreen, and/or a display), and/or network connections. The coupling of the processors and other components is typically through one or more busses and bridges (also termed bus controllers). Thus, the storage device of a given electronic device may stores code and/or data for execution on the one or more processors of that electronic device. Alternatively, one or more parts of an embodiment of the invention may be implemented using different combinations of software, firmware, and/or hardware.

It should also be appreciated that reference throughout this specification to "one embodiment", "an embodiment", or "one or more embodiments", for example, means that a particular feature may be included in the practice of the invention. Similarly, it should be appreciated that in the description various features are sometimes grouped together in a single embodiment, Figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the invention requires more features than are expressly recited in each claim.

Rather, as the following claims reflect, inventive aspects may lie in less than all features of a single disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of the invention.

The following clauses and/or examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments.

In one embodiment, a first method in a processor of handling physical register use includes determining that a first thread is attempting to enter a transitory higher physical register use mode. A physical register use threshold of a second thread is reduced from a higher physical register use threshold to a lower physical register use threshold, in response to determining that the first thread is attempting to enter the transitory higher physical register use mode. It is determined that a physical register use value of the second thread is not within the lower physical register use threshold. The first thread is prevented from entering the transitory higher physical register use mode, while the physical register use value of the second thread is not within the lower physical register use threshold.

Embodiments include the first method in which allocation of additional physical registers to the second thread is prevented, while the physical register use value of the second thread is not within the lower physical register use threshold, and while allowing instructions of the second thread to commit.

Embodiments include the above method, in which after preventing the first thread from entering the transitory higher physical register use mode, a determination is made that an updated physical register use value of the second thread is within the lower physical register use threshold due to the instructions of the second thread being allowed to commit. The first thread is allowed to enter the transitory higher physical register use mode, while the updated physical register use value is within the lower physical register use threshold.

Embodiments include the first method in which determining that the first thread is attempting to enter the transitory higher physical register use mode includes determining that the first thread is attempting to perform hardware based transactional execution. Allocation of additional physical registers to the second thread is prevented, while the physical register use value of the second thread is not within the lower physical register use threshold, and while allowing instructions of the second thread to commit. It is determined that an updated physical register use value of the second thread is within the lower physical register use threshold. The first thread is allowed to perform the hardware based transactional execution in response to determining that the updated physical register use value of the second thread is within the lower physical register use threshold. In an aspect, reducing the physical register use threshold from the higher threshold to the lower threshold may include reducing the physical register use threshold by at least 10 (e.g., 10 to 50) physical registers.

Embodiments include the first method in which after preventing the first thread from entering the transitory higher physical register use mode, a determination is made that the first thread is no longer attempting to enter the transitory higher physical register use mode. The physical register use threshold of the second thread is increased from the lower physical register use threshold to the higher physical register use threshold, in response to determining that the first thread is no longer attempting to enter the transitory higher physical register use mode.

Embodiments include any of the above methods in which reducing the physical register use threshold from the higher threshold to the lower threshold includes reducing the physical register use threshold by at least 10 physical registers.

Embodiments include any of the above methods in which determining that the first thread is attempting to enter the transitory higher physical register use mode includes determining that the first thread is attempting to perform hardware based transactional execution. In one embodiment, a first apparatus to handle physical register use includes threshold adjustment logic to reduce a physical register use threshold of a second thread from a higher physical register use threshold to a lower physical register use threshold, in response to a first thread attempting to enter a transitory higher physical register use mode. Threshold comparison logic is included to determine that a physical register use value of the second thread is not within the lower physical register use threshold. Prevention logic is included to prevent the first thread from entering the transitory higher physical register use mode, while the physical register use value of the second thread is not within the lower physical register use threshold.

Embodiments include the first apparatus including thread stall logic to stall the second thread, while the physical register use value of the second thread is not within the lower physical register use threshold, and while allowing instructions of the second thread to commit.

Embodiments include the above apparatus, in which the threshold comparison logic, after determining that the physical register use value of the second thread is not within the lower physical register use threshold, is to determine that an updated physical register use value of the second thread is within the lower physical register use threshold. In response, the prevention logic is no longer to prevent the first thread from entering the transitory higher physical register use mode.

Embodiments include any of the above apparatus including logic to determine that the first thread is attempting to enter the transitory higher physical register use mode. In an aspect, the higher physical register use mode includes hardware based transactional execution.

Embodiments include the first apparatus including thread stall logic to stall the second thread, while the physical register use value of the second thread is not within the lower physical register use threshold, and while allowing instructions of the second thread to commit. In an aspect, the higher physical register use mode includes hardware based transactional execution.

In one embodiment, a system to handle physical register includes an interconnect. A processor is coupled with the interconnect. The processor includes a higher physical register use threshold of a second thread that is to be used when a first thread is not attempting to enter a transitory higher physical register use mode. A lower physical register use threshold of the second thread is to be used when the first thread is attempting to enter the transitory higher physical register use mode. Prevention logic of the processor is to prevent the first thread from entering the transitory higher physical register use mode when a physical register use value of the second thread is not within the lower physical register use threshold. The system includes a dynamic random access memory (DRAM) coupled with the interconnect.

Embodiments include the system in which the transitory higher physical register use mode includes a transactional execution mode.

Embodiments include any of the above systems including thread stall logic to stall the second thread, while the physical register use value of the second thread is not within the lower physical register use threshold, and while allowing instructions of the second thread to commit.

In one embodiment, an article of manufacture includes a machine-accessible medium that provides instructions that if executed result in a machine performing operations including determining that a first thread is attempting to enter a transitory higher physical register use mode. The operations also include reducing a physical register use threshold of a second thread from a higher physical register use threshold to a lower physical register use threshold, in response to determining that the first thread is attempting to enter the transitory higher physical register use mode. The operations also include determining that a physical register use value of the second thread is not within the lower physical register use threshold. The operations also include preventing the first thread from entering the transitory higher physical register use mode, while the physical register use value of the second thread is not within the lower physical register use threshold.

Embodiments include the article in which the instructions to determine that the first thread is attempting to enter the higher physical register use mode include instructions that if executed result in the machine determining that the first thread is attempting to perform hardware based transactional execution.

Embodiments include any of the above articles including in which the machine-accessible medium further provides instructions that if executed result in the machine performing operations including preventing allocation of additional physical registers to the second thread, while the physical register use value of the second thread is not within the lower physical register use threshold, and while allowing instructions of the second thread to commit.

In one embodiment, a second apparatus to handle physical register use includes means for determining that a first thread is attempting to enter a transitory higher physical register use mode. Also included are means for reducing a physical register use threshold of a second thread from a higher physical register use threshold to a lower physical register use threshold, in response to determining that the first thread is attempting to enter the transitory higher physical register use mode. The apparatus also includes means for determining that a physical register use value of the second thread is not within the lower physical register use threshold. Additionally including means for preventing the first thread from entering the transitory higher physical register use mode, while the physical register use value of the second thread is not within the lower physical register use threshold.

Embodiments include the second apparatus including means for preventing allocation of additional physical registers to the second thread, while the physical register use value of the second thread is not within the lower physical register use threshold, and while allowing instructions of the second thread to commit.

In one embodiment, at least one machine-readable medium includes instructions that in response to being executed on a computing device cause the computing device to carry out any of the methods disclosed herein.

In one embodiment, an apparatus is configured to perform any of the methods disclosed herein.

Claims

CLAIMS What is claimed is:

1. A method in a processor of handling physical register use comprising:

determining that a first thread is attempting to enter a transitory higher physical register use mode; reducing a physical register use threshold of a second thread from a higher physical register use threshold to a lower physical register use threshold, in response to determining that the first thread is attempting to enter the transitory higher physical register use mode;

determining that a physical register use value of the second thread is not within the lower physical register use threshold; and

preventing the first thread from entering the transitory higher physical register use mode, while the physical register use value of the second thread is not within the lower physical register use threshold.

2. The method of claim 1, further comprising preventing allocation of additional physical registers to the second thread, while the physical register use value of the second thread is not within the lower physical register use threshold, and while allowing instructions of the second thread to commit.

3. The method of claim 2, further comprising:

after preventing the first thread from entering the transitory higher physical register use mode, determining that an updated physical register use value of the second thread is within the lower physical register use threshold due to the instructions of the second thread being allowed to commit; allowing the first thread to enter the transitory higher physical register use mode, while the updated physical register use value is within the lower physical register use threshold.

4. The method of any of claims 1 to 3, wherein determining that the first thread is attempting to enter the transitory higher physical register use mode comprises determining that the first thread is attempting to perform hardware based transactional execution.

5. The method of claim 1, wherein determining that the first thread is attempting to enter the transitory higher physical register use mode comprises determining that the first thread is attempting to perform hardware based transactional execution, and further comprising:

preventing allocation of additional physical registers to the second thread, while the physical register use value of the second thread is not within the lower physical register use threshold, and while allowing instructions of the second thread to commit; determining that an updated physical register use value of the second thread is within the lower physical register use threshold;

allowing the first thread to perform the hardware based transactional execution in response to determining that the updated physical register use value of the second thread is within the lower physical register use threshold, wherein reducing the physical register use threshold from the higher threshold to the lower threshold comprises reducing the physical register use threshold by at least 10 physical registers.

6. The method of claim 1, further comprising:

after preventing the first thread from entering the transitory higher physical register use mode, determining that the first thread is no longer attempting to enter the transitory higher physical register use mode; and

increasing the physical register use threshold of the second thread from the lower physical register use threshold to the higher physical register use threshold, in response to determining that the first thread is no longer attempting to enter the transitory higher physical register use mode.

7. The method of claim 1, wherein reducing the physical register use threshold from the higher threshold to the lower threshold comprises reducing the physical register use threshold by at least 10 physical registers.

8. An apparatus to handle physical register use comprising:

threshold adjustment logic to reduce a physical register use threshold of a second thread from a higher physical register use threshold to a lower physical register use threshold, in response to a first thread attempting to enter a transitory higher physical register use mode;

threshold comparison logic to determine that a physical register use value of the second thread is not within the lower physical register use threshold; and

prevention logic to prevent the first thread from entering the transitory higher physical register use mode, while the physical register use value of the second thread is not within the lower physical register use threshold.

9. The apparatus of claim 8, further comprising logic to determine that the first thread is attempting to enter the transitory higher physical register use mode, wherein the higher physical register use mode comprises hardware based transactional execution.

10. The apparatus of any of claims 8 to 9, further comprising thread stall logic to stall the second thread, while the physical register use value of the second thread is not within the lower physical register use threshold, and while allowing instructions of the second thread to commit.

11. The apparatus of claim 10, wherein the threshold comparison logic, after determining that the physical register use value of the second thread is not within the lower physical register use threshold, is to determine that an updated physical register use value of the second thread is within the lower physical register use threshold, and wherein in response the prevention logic is no longer to prevent the first thread from entering the transitory higher physical register use mode.

12. The apparatus of claim 8, further comprising thread stall logic to stall the second thread, while the physical register use value of the second thread is not within the lower physical register use threshold, and while allowing instructions of the second thread to commit, and wherein the higher physical register use mode comprises hardware based transactional execution.

13. A system to handle physical register use comprising:

an interconnect;

a processor coupled with the interconnect, the processor including:

a higher physical register use threshold of a second thread that is to be used when a first thread is not attempting to enter a transitory higher physical register use mode; a lower physical register use threshold of the second thread that is to be used when the first thread is attempting to enter the transitory higher physical register use mode; and

prevention logic to prevent the first thread from entering the transitory higher physical register use mode when a physical register use value of the second thread is not within the lower physical register use threshold; and

a dynamic random access memory (DRAM) coupled with the interconnect.

14. The system of claim 13, wherein the transitory higher physical register use mode comprises a transactional execution mode.

15. The system of any of claims 13 and 14, further comprising thread stall logic to stall the second thread, while the physical register use value of the second thread is not within the lower physical register use threshold, and while allowing instructions of the second thread to commit.

16. An article of manufacture comprising: a machine-accessible medium that provides instructions that if executed result in a machine performing operations including,

determining that a physical register use value of the second thread is not within the lower physical register use threshold;

17. The article of manufacture of claim 16, wherein the instructions to determine that the first thread is attempting to enter the higher physical register use mode comprise instructions that if executed result in the machine determining that the first thread is attempting to perform hardware based transactional execution.

18. The article of manufacture of any of claims 16 and 17, wherein the machine-accessible medium further provides instructions that if executed result in the machine performing operations including preventing allocation of additional physical registers to the second thread, while the physical register use value of the second thread is not within the lower physical register use threshold, and while allowing instructions of the second thread to commit.

19. An apparatus to handle physical register use comprising:

means for determining that a first thread is attempting to enter a transitory higher physical register use mode;

means for reducing a physical register use threshold of a second thread from a higher physical register use threshold to a lower physical register use threshold, in response to determining that the first thread is attempting to enter the transitory higher physical register use mode;

means for determining that a physical register use value of the second thread is not within the lower physical register use threshold; and

means for preventing the first thread from entering the transitory higher physical register use mode, while the physical register use value of the second thread is not within the lower physical register use threshold.

20. The apparatus of claim 19, further comprising means for preventing allocation of additional physical registers to the second thread, while the physical register use value of the second thread is not within the lower physical register use threshold, and while allowing instructions of the second thread to commit.

21. At least one machine-readable medium comprising instructions that in response to being executed on a computing device cause the computing device to carry out a method according to any of claims 1 to 3.

22. An apparatus configured to perform the method of any one of claims 1 to 3.