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WO2013146646A1 - Dispositif de laser à semi-conducteurs - Google Patents

Dispositif de laser à semi-conducteurs Download PDF

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Publication number
WO2013146646A1
WO2013146646A1 PCT/JP2013/058516 JP2013058516W WO2013146646A1 WO 2013146646 A1 WO2013146646 A1 WO 2013146646A1 JP 2013058516 W JP2013058516 W JP 2013058516W WO 2013146646 A1 WO2013146646 A1 WO 2013146646A1
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WIPO (PCT)
Prior art keywords
submount
semiconductor element
materials
thermal expansion
longitudinal direction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2013/058516
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English (en)
Japanese (ja)
Inventor
和典 別所
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ushio Denki KK
Original Assignee
Ushio Denki KK
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Filing date
Publication date
Application filed by Ushio Denki KK filed Critical Ushio Denki KK
Publication of WO2013146646A1 publication Critical patent/WO2013146646A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0235—Method for mounting laser chips
    • H01S5/02355—Fixing laser chips on mounts
    • H01S5/0237—Fixing laser chips on mounts by soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/023—Mount members, e.g. sub-mount members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0233—Mounting configuration of laser chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0235—Method for mounting laser chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3732—Diamonds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/024—Arrangements for thermal management
    • H01S5/02476—Heat spreaders, i.e. improving heat flow between laser chip and heat dissipating elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/40—Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30
    • H01S5/4025—Array arrangements, e.g. constituted by discrete laser diodes or laser bar

Definitions

  • the present invention relates to a semiconductor laser device, and more particularly to a semiconductor laser device including a submount portion on which a semiconductor element is mounted.
  • Patent Document 1 discloses a technique shown as a conventional example in FIG.
  • the submount unit 3 includes a submount substrate 7 having a linear thermal expansion coefficient different from that of the semiconductor element 2 to be mounted.
  • the first surface of the submount 7 is covered with a thickness such that the linear thermal expansion coefficient of the submount portion 3 is substantially equal to the linear thermal expansion coefficient of the semiconductor element 2.
  • a layer 8 and a second covering layer 9 are provided.
  • the semiconductor laser device provided with such a submount portion 3 the residual thermal stress generated during the temperature rise and fall before and after the joining of the semiconductor element 2 and the submount portion 3 during the manufacturing and during the operation of the semiconductor element 2. It is said that stress can be reduced.
  • Typical materials used for the submount substrate 7 include diamond and aluminum nitride having an electrical insulating function.
  • first coating layer 8 and the second coating layer 9 that are coated on the front and back surfaces of the submount substrate 7 copper or gold is used.
  • 2b is a gold plating layer
  • 2c is a gold-tin solder layer.
  • a material having a high thermal conductivity is selected as the submount substrate 7, and the first In addition to the coating layer 8, a material having a high thermal conductivity is selected as the second coating layer 9.
  • diamond is used for the submount substrate 7, and copper is used for the first coating layer 8 and the second coating layer 9.
  • Diamond is a material having a low coefficient of linear thermal expansion and a high rigidity, but copper is a substance having a high coefficient of linear thermal expansion and a low rigidity to diamond.
  • the thicknesses of the first copper coating layer 8 and the second copper coating layer 9 are set to be the same. It needs to be thick.
  • the ability to exhaust the amount of heat received from the semiconductor element 2 to the heat sink is reduced. For this reason, there exists a problem that the advantage of using diamond with high heat conductivity for the submount substrate 7 of the submount part 3 falls.
  • the present invention has been made in order to solve the above-described problems, and an object of the present invention is to improve the characteristics of a semiconductor laser device, ensure high thermal conductivity of diamond, and It is an object of the present invention to provide a semiconductor laser device including a submount portion having a diamond submount structure in which the coefficient of thermal expansion is adjusted.
  • the semiconductor laser device of the present invention is a semiconductor laser device comprising a semiconductor element and a submount portion on which the semiconductor element is mounted on one surface.
  • the submount includes at least one first submount material having a linear thermal expansion coefficient different from that of the semiconductor element, and at least one linear thermal expansion coefficient greater than that of the semiconductor element and the first submount material.
  • a second submount material, The first submount material and the second submount material have a first submount material portion formed by the first submount material and a second submount over a surface on which the semiconductor element of the submount portion is mounted.
  • the second submount material portions by the mount material are arranged so as to be alternately arranged in the longitudinal direction of the semiconductor element,
  • the first submount material is bonded to the semiconductor element via a bonding material,
  • the length in the longitudinal direction of the semiconductor element is L (mm)
  • the coefficient of linear thermal expansion of the semiconductor element is ⁇
  • the length in the longitudinal direction of the semiconductor element in the first submount material portion in the submount portion is L (mm)
  • L1 (mm) is the total length of the first submount material
  • ⁇ 1 is the linear thermal expansion coefficient of the first submount material
  • the semiconductor in the second submount material portion in the submount portion is L2 (mm)
  • L (mm) L1 (mm) + L2 (mm)
  • L (mm) ⁇ ⁇ L1 (mm) ⁇ ⁇ 1 + L2 (mm) ⁇ ⁇ 2
  • the semiconductor element is made of gallium arsenide (GaAs), and the submount portion is constituted by a first submount material made of diamond and a second submount material made of copper. It is preferable that
  • the submount portion is disposed between a plurality of the first submount materials and the first submount materials adjacent to each other in the plurality of first submount materials.
  • the second submount material, The plurality of first submount materials are arranged so as to support the semiconductor element via a bonding material in the vicinity of the plurality of light emitting portions formed in the semiconductor element,
  • the second submount material is disposed apart from the semiconductor element,
  • the number of light emitting portions of the semiconductor element is N, and the length in the longitudinal direction of the semiconductor element in the first submount material supporting the semiconductor element in the vicinity of each of the plurality of light emitting portions is D1 (mm).
  • the linear thermal expansion coefficient of a semiconductor element such as a laser diode and the linear thermal expansion coefficient of the submount can be equivalently equalized.
  • a material made of a material having high thermal conductivity such as diamond is used for the submount, the material can exhibit the maximum heat exhausting capacity, and the semiconductor element can be efficiently cooled.
  • a highly efficient semiconductor laser device can be provided.
  • FIG. 1 is an explanatory schematic view showing a semiconductor laser device according to a first embodiment of the present invention. It is the schematic for description which shows the semiconductor laser apparatus concerning the 2nd Example of this invention. It is the schematic for description which shows the semiconductor laser apparatus concerning the 3rd Example of this invention. It is explanatory drawing which shows an example of the submount structure in the conventional semiconductor laser apparatus.
  • the submount portion includes one or more first submount materials made of diamond and one or more second submount materials made of copper. is there.
  • the submount portion includes a first submount material portion made of the first submount material and a second submount material portion made of the second submount material over a surface on which the semiconductor element is mounted.
  • the linear thermal expansion coefficient is adjusted by arranging the semiconductor elements alternately in the longitudinal direction. Specific examples of the present invention are shown below.
  • FIG. 1 is an explanatory diagram showing an outline of a semiconductor laser device according to a first embodiment of the present invention.
  • a semiconductor laser device 1 of the present invention includes a rectangular parallelepiped semiconductor element 2 and a submount portion 3 for mounting the semiconductor element 2 on the upper surface (the upper surface in FIG. 1).
  • the submount unit 3 includes one or more (a plurality of) first submount materials 41 to 45 having a linear thermal expansion coefficient different from that of the semiconductor element 2, and the semiconductor element 2 and the first submount materials 41 to 41. And one or more (plural) second submount materials 51 to 54 having a linear thermal expansion coefficient larger than 45.
  • the plurality of first submount materials 41 to 45 and the plurality of second submount materials 51 to 54 each have a rectangular parallelepiped shape.
  • the first submount materials 41 to 45 and the second submount materials 51 to 54 are alternately arranged in the longitudinal direction of the semiconductor element 2 along the lower surface of the semiconductor element 2 (the lower surface in FIG. 1).
  • the first submount material and the second submount material adjacent to each other are joined to each other.
  • a first submount material portion is formed by each of the plurality of first submount materials 41 to 45, and the plurality of second submount materials 51 to 54 are formed.
  • a second submount material portion is formed by each.
  • the plurality of first submount material portions and the plurality of second submount material portions are alternately positioned over the upper surface of the submount portion 3 on which the semiconductor element 2 is mounted.
  • the first submount materials 41 to 45 are bonded to the semiconductor element 2 via the bonding material 11.
  • the second submount materials 51 to 54 are not joined to the semiconductor element 2 and are separated from the semiconductor element 2.
  • the semiconductor element 2 and the first submount materials 41 to 45 in the submount portion 3 are heated to a temperature at which the bonding material 11 is melted when they are bonded by the bonding material 11. If the temperature at the time of joining is T1, in the semiconductor element 2 and the submount part 3, the value obtained by multiplying the linear thermal expansion coefficient of the material constituting the semiconductor element 2 and the submount part 3 by T1 The material will stretch. If materials having different linear thermal expansion coefficients such as diamond and semiconductor are used for the submount portion 3 and the semiconductor element 2, the lengths of the submount portion 3 and the semiconductor element 2 match at the time of bonding.
  • the sum of the total length of the first submount material and the total length of the second submount material in the submount portion 3 at the room temperature T0 and the bonding temperature T1 is It is adjusted to be equal to the total length.
  • the length in the longitudinal direction of the semiconductor element 2 in the first submount materials 41 to 45 having a linear thermal expansion coefficient smaller than the linear thermal expansion coefficient of the semiconductor element 2, and the linear thermal expansion of the semiconductor element 2 The length in the longitudinal direction of the semiconductor element 2 in the second submount materials 51 to 54 having a linear thermal expansion coefficient larger than the coefficient is adjusted. Thereby, the difference in thermal expansion coefficient with the semiconductor element 2 is offset in the submount portion 3 as a whole so that it becomes equal to the linear thermal expansion coefficient of the semiconductor element 2.
  • the length in the longitudinal direction of the semiconductor element 2 is L (mm)
  • the linear thermal expansion coefficient of the semiconductor element 2 is ⁇
  • the total length of the first submount material in the submount portion 3 is L1 (mm)
  • the linear thermal expansion coefficient of the first submount material is ⁇ 1
  • the total length of the second submount material in the submount portion 3 is L2 (mm)
  • the linear thermal expansion coefficient of the second submount material is ⁇ 2.
  • L (mm) L1 (mm) + L2 (mm) (1)
  • L (mm) ⁇ ⁇ L1 (mm) ⁇ ⁇ 1 + L2 (mm) ⁇ ⁇ 2 (2)
  • the total length L1 (mm) of the first submount material means the semiconductor element in the first submount material portion of each of the first submount materials 41 to 45 constituting the submount portion 3. 2 is a value indicating the total length in the longitudinal direction. That is, in the first embodiment according to FIG. 1, the total length in the longitudinal direction of the semiconductor element 2 in the plurality of first submount members 41 to 45 constituting the submount portion 3 is obtained. Further, “the total length L2 (mm) of the second submount material” refers to the semiconductor element 2 in the second submount material portion of each of the second submount materials 51 to 54 constituting the submount portion 3. Is a value indicating the total length in the longitudinal direction. That is, in the first embodiment according to FIG.
  • the total length in the longitudinal direction of the semiconductor element 2 in the plurality of second submount members 51 to 54 constituting the submount portion 3 is obtained. Furthermore, “the length L (mm) in the longitudinal direction of the semiconductor element”, “the total length L1 (mm) of the first submount material”, and “the total length L2 (mm) of the second submount material” are respectively The length at room temperature T0 is shown. Of course, “the length in the longitudinal direction of the semiconductor element in the first submount material portion” related to the total length L1 (mm) of the first submount material and “the total length L2 (mm) of the second submount material” The “length in the longitudinal direction of the semiconductor element in the second submount material portion” also indicates the length at room temperature T0.
  • a GaAs-based semiconductor element 2 (external dimensions: thickness 0.3 mm ⁇ depth 0.3 mm ⁇ full length (length in the longitudinal direction) 3.6 mm, constituting a light emitting portion
  • the following submount unit 3 is used for the number of light emitting points (5: edge emitter type).
  • the submount portion 3 includes five first submount materials (outer dimensions: width (length in the longitudinal direction of the semiconductor element 2) 0.543 mm ⁇ thickness 0.3 mm ⁇ depth 0.3 mm) 41 made of diamond.
  • the first submount material is disposed at one end, the second submount material is disposed adjacently, and the first submount material is disposed adjacently.
  • the first submount materials 41 to 45 and the second submount materials 51 to 54 are alternately arranged to constitute the submount portion 3.
  • the second submount material made of copper is sandwiched by the first submount material made of diamond to form the submount portion 3.
  • the GaAs-based semiconductor device 2 and the first submount materials 41 to 45 made of diamond are bonded via the bonding material 11, but the second submount materials 51 to 54 made of copper are The semiconductor element 2 is not joined but is spaced apart.
  • the plurality of first submount members 41 to 45 forming the submount portion 3 are formed from a diamond plate having a total length of 3.6 mm, the outer dimensions are width 0.543 mm ⁇ thickness 0.3 mm ⁇ depth 0.3 mm. It is also possible to use a material obtained by cutting out five pieces of the material.
  • FIG. 2 is an explanatory view showing the outline of the semiconductor laser device according to the second embodiment of the present invention.
  • the semiconductor laser device 1 of the present invention includes a rectangular parallelepiped semiconductor element 2 and a submount portion 3 for mounting the semiconductor element 2 on the upper surface (the upper surface in FIG. 2).
  • the submount portion 3 has one first submount material 4 having a linear thermal expansion coefficient different from that of the semiconductor element 2 and a larger linear thermal expansion coefficient than the semiconductor element 2 and the first submount material 4.
  • One or more (plural) second submount materials 51 to 54 are included.
  • the first submount material 4 has a substantially rectangular parallelepiped appearance, and the upper surface (the upper surface in FIG.
  • the second submount materials 54 to 54 have a rectangular parallelepiped shape suitable for the slit portion in the first submount material 4.
  • the first submount material 4 and the second submount materials 51 to 54 have a structure in which the second submount materials 51 to 54 are embedded in the slit portion of the first submount material 4. ing. In this way, in the submount portion 3, the first submount 4 by the first submount material 4 extends along the lower surface (the lower surface in FIG. 1) of the semiconductor element 2 over the upper surface on which the semiconductor element 2 is mounted.
  • the mount material portions and the second submount material portions by the second submount materials 54 to 54 are alternately arranged in the longitudinal direction of the semiconductor element 2.
  • the first submount material portion is formed by each of the convex portions adjacent to the slit portion in the first submount material 4
  • the second submount material portion is the second submount.
  • Each of the materials 51 to 54 is formed.
  • the first submount material 4 is bonded to the semiconductor element 2 via the bonding material 11 in the first submount material portion.
  • the second submount materials 51 to 54 are not joined to the semiconductor element 2 and are separated from the semiconductor element 2.
  • the length in the longitudinal direction of the semiconductor element 2 in the portion joined to the semiconductor element 2 (the length excluding the length in the longitudinal direction of the semiconductor element in the plurality of slit portions) ) Is adopted as “the total length L1 of the first submount material”. That is, the length of the semiconductor element 2 in the longitudinal direction is L (mm), the linear thermal expansion coefficient of the semiconductor element 2 is ⁇ , and the total length of the first submount material in the submount portion 3 (the semiconductor in the plurality of slit portions).
  • the length excluding the length in the longitudinal direction of the element 2) is L1 (mm)
  • the linear thermal expansion coefficient of the first submount material is ⁇ 1
  • the total length of the second submount material in the submount portion 3 is L2. (Mm)
  • the semiconductor element 2 when the linear expansion coefficient of the second submount material is ⁇ 2, the semiconductor element 2, the first submount material 4 and the second submount material 2 are set so as to satisfy the following two expressions simultaneously.
  • the length of the submount materials 51 to 54 (the length in the longitudinal direction of the semiconductor element 2) and the substance to be used are set.
  • L (mm) L1 (mm) + L2 (mm) (1)
  • L (mm) ⁇ ⁇ L1 (mm) ⁇ ⁇ 1 + L2 (mm) ⁇ ⁇ 2 (2)
  • a GaAs-based semiconductor element 2 (external dimensions: thickness 0.3 mm ⁇ depth 0.3 mm ⁇ full length (length in the longitudinal direction) 3.6 mm, constituting a light emitting portion
  • the following submount unit 3 is used for the number of light emitting points (5: edge emitter type).
  • the submount portion 3 is a diamond-made first submount material 4 having an outer dimension of 0.3 mm thick ⁇ 0.3 mm deep ⁇ full length (length in the longitudinal direction of the semiconductor element 2) 3.6 mm.
  • Each plate-shaped material is provided with a material in which four slit portions each having a width of 0.222 mm and a depth of 0.25 mm are provided.
  • a second copper submount material (outside dimension: width (length in the longitudinal direction of the semiconductor element 2) 0.222 mm ⁇ thickness 0.2 mm ⁇ depth 0) is formed in the slit portion of the first submount material 4. .3 mm) 51 to 54 are embedded.
  • the GaAs-based semiconductor element 2 and the first submount material 4 made of diamond are bonded via the bonding material 11, while the second submount materials 51 to 54 made of copper are bonded to the semiconductor element 2.
  • the second submount materials 51 to 54 forming the submount portion 3 are formed on the first submount material 4 having an outer dimension of 0.3 mm thickness ⁇ 0.3 mm depth ⁇ 3.6 mm overall length. It may be produced by vapor-depositing or copper-plating copper on the four slit portions.
  • FIG. 3 is an explanatory diagram showing an outline of a semiconductor laser device according to the third embodiment of the present invention.
  • the semiconductor laser device 1 includes a rectangular parallelepiped semiconductor element 2 and a submount portion 3 for mounting the semiconductor element 2 on the upper surface (the upper surface in FIG. 1).
  • the semiconductor element 2 is an array type element having a plurality of light emitting points (emitters) 2a, and includes a light emitting portion composed of five light emitting points 2a.
  • the first submount materials 41 to 45 are disposed so as to support the semiconductor element via the bonding material 11 in the vicinity of the plurality of light emitting points 2 a formed in the semiconductor element 2.
  • the bonding material 11 is provided between the semiconductor element 2 and the semiconductor element 2 so as to correspond to the light emitting point 2a (directly under the light emitting point 2a in the drawing).
  • a plurality of first submount materials 41 to 45 are arranged therebetween.
  • a plurality of second submount materials 51 to 54 are disposed between the plurality of first submount materials 41 to 45.
  • the number of light emitting points 2a of the semiconductor element 2 is N, and the vicinity of the light emitting points 2a.
  • the length in the longitudinal direction of the semiconductor element 2 in the first submount materials 41 to 45 supporting the semiconductor element 2 is D1 (mm)
  • the length in the longitudinal direction of the semiconductor element 2 in the second submount materials 51 to 54 is When D2 (mm), in addition to the formula (1) and the formula (2), the total length L1 (mm) of the first submount material and the total length L2 (mm) of the second submount material are as follows: It satisfies the relationship shown in
  • L1 (mm) N ⁇ D1 (mm) (3)
  • L2 (mm) (N ⁇ 1) ⁇ D2 (mm) (4)
  • the other components of the submount unit 3 are similar to those of the first embodiment shown in FIG.
  • One or more (a plurality of) first submount materials 41 to 45 having different expansion coefficients, and one or more first submount materials 41 to 45 having a linear thermal expansion coefficient larger than that of the semiconductor element 2 and the first submount materials 41 to 45 A plurality of second submount materials 51 to 54.
  • the plurality of first submount materials 41 to 45 and the plurality of second submount materials 51 to 54 each have a rectangular parallelepiped shape.
  • the first submount materials 41 to 45 and the second submount materials 51 to 54 are alternately arranged in the longitudinal direction of the semiconductor element 2 along the lower surface of the semiconductor element 2 (the lower surface in FIG. 1).
  • the first submount material and the second submount material which are arranged and are adjacent to each other are joined.
  • a first submount material portion is formed by each of the first submount materials 41 to 45
  • a submount is formed by each of the second submount materials 51 to 54.
  • a material portion is formed.
  • the plurality of first submount material portions and the plurality of second submount material portions are alternately positioned over one surface of the submount portion 3 on which the semiconductor element 2 is mounted.
  • the first submount materials 41 to 45 are bonded to the semiconductor element 2 via the bonding material 11.
  • the second submount materials 51 to 54 are not joined to the semiconductor element 2 and are separated from the semiconductor element 2.
  • the submount portion 3 has a length of the first submount materials 41 to 45 having a linear thermal expansion coefficient smaller than that of the semiconductor element 2 (length in the longitudinal direction of the semiconductor element 2).
  • the length of the second submount materials 51 to 54 having a larger linear thermal expansion coefficient than the linear thermal expansion coefficient of the semiconductor element 2 (the length in the longitudinal direction of the semiconductor element 2) is adjusted. Thereby, the difference in thermal expansion coefficient with the semiconductor element 2 is offset in the submount portion 3 as a whole so that it becomes equal to the linear thermal expansion coefficient of the semiconductor element 2.
  • the semiconductor element 2 is an array type semiconductor element having a plurality of light emitting points 2a, and the semiconductor element 2 with respect to the submount portion 3 is used.
  • the heat load from is very large.
  • the semiconductor element 2 can be obtained.
  • the submount part 3 with no difference in expansion coefficient can be provided. Therefore, there is no need to interpose a material for reducing the difference in linear thermal expansion coefficient between each of the first submount materials 41 to 45 made of diamond in the submount portion 3 and the semiconductor element 2.
  • the first submount materials 41 to 45 made of a material having high thermal conductivity such as diamond can exhibit the maximum heat removal capability, and the semiconductor element 2 is efficiently cooled. As a result, there is an advantage that a highly efficient semiconductor laser device 1 can be provided.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)
PCT/JP2013/058516 2012-03-30 2013-03-25 Dispositif de laser à semi-conducteurs Ceased WO2013146646A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012-078889 2012-03-30
JP2012078889A JP2013211303A (ja) 2012-03-30 2012-03-30 半導体レーザ装置

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WO2013146646A1 true WO2013146646A1 (fr) 2013-10-03

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018157136A (ja) * 2017-03-21 2018-10-04 三菱マテリアル株式会社 熱電変換モジュール

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9812375B2 (en) * 2015-02-05 2017-11-07 Ii-Vi Incorporated Composite substrate with alternating pattern of diamond and metal or metal alloy
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