WO2013143385A1 - Calcul de décalage temporel - Google Patents
Calcul de décalage temporel Download PDFInfo
- Publication number
- WO2013143385A1 WO2013143385A1 PCT/CN2013/072354 CN2013072354W WO2013143385A1 WO 2013143385 A1 WO2013143385 A1 WO 2013143385A1 CN 2013072354 W CN2013072354 W CN 2013072354W WO 2013143385 A1 WO2013143385 A1 WO 2013143385A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- time
- downlink
- test signal
- uplink
- master device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
- H04B10/075—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
- H04B10/077—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using a supervisory or additional signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
Definitions
- a clock distribution system is required for synchronising one or more clocks in the communication system of each segment.
- the architecture of a clock distribution system may for example be based on NTP
- the one or more clocks may for example be an ordinary clock, a boundary clock or a transparent clock.
- the plurality of clocks may include a source of synchronisation reference - a master device - and a destination for the synchronisation reference - a slave device, and the master and slave devices are generally connected via an uplink connection for transmissions from the slave device to the master device, and a downlink connection for transmission from the master device to the slave device, where the uplink and downlink connections may be optical waveguides such as optical fibres.
- Figure 1 is a schematic representation of a
- Figure 2 is a flow diagram of an example of a clock synchronisation method
- Figure 3 is a schematic diagram of an example of a communication system
- Figure 4 is a modification of the communication system of Figure 3.
- a slave device calculates a time offset based on a downlink delay time and an uplink delay time between a master device and the slave device so as to synchronised with reference to the master device.
- the slave device obtains the
- the slave device obtains the uplink delay time based on a second transmission time and a second reception time by sending a second test signal via an uplink optical waveguide to the master device and recording the second transmission time, and receiving the second test signal looped back by the master device via the uplink optical waveguide and recording the second reception time.
- test signals are looped back by the master device, it is possible to minimise any processing time at the master device, and obtain only the time delay caused by the transit over the uplink and downlink connections. Moreover, as both the transmission time and the reception time of a test signal may be collected at the slave device, which is the side to be synchronised, the efficiency of time
- FIG. 1 An example of a communication system is schematically shown in Figure 1, which comprises a master device 110 and a slave device 120.
- Figure 2 is a flow diagram depicting an example of a method for determining a time delay between a master device and a slave device, for example the master device 110 and the slave device 120, in order to perform clock synchronization for a communication system.
- the slave device 120 is connected to the master device 110 via a downlink connection and an uplink connection such as optical fibres.
- the slave device 120 obtains a downlink delay time that is a transit time for transmission to travel between the slave device 120 and the master device 110 via the downlink connection.
- the slave device 120 sends a downlink delay test message (first test signal) via the downlink optical fibre to the master device 110, and records the time at which the downlink delay test message was transmitted as a first transmission time Tl down .
- the master device 110 loops the downlink delay test message back to the slave device 120 via the downlink optical fibre.
- the master device 110 may perform the loopback using a loopback module 115 such as a commercially
- the slave device 120 records the time at which the looped back downlink delay test message is received as a first reception time T2 down . Using the first transmission time and the first reception time, the slave device 120 calculates the
- the slave device 120 obtains an uplink delay time that is a transit time for transmission to travel between the slave device 120 and the master device 110 via the uplink connection.
- the slave device 120 sends an uplink delay test message (second test signal) via the uplink optical fibre to the master device 110, and records the time at which the uplink delay test message was
- the master device 110 Upon receiving the uplink delay test message, the master device 110 loops the uplink delay test message back to the slave device 120 via the uplink optical fibre using a suitable loopback module 115.
- the slave device 120 records the time at which the looped back uplink delay test message is received as a second reception time T2 up . Using the second transmission time and the second reception time, the slave device 120 calculates the uplink delay time.
- the slave device 120 calculates a time offset between the master device 110 and the slave device 120 based on the obtained downlink delay time and uplink delay time.
- separately obtained downlink delay time and uplink delay time are used for determining the time offset between the master device and the slave device.
- the present example is able to obtain a more
- T2 down - Tl down is a round-trip time, it is divided by 2 to obtain the path delay for a single trip.
- the downlink delay may be obtained by repeating the measurement of Tl down and T2 down a plurality of times to calculate the respective PathDelay d0W n, and
- the uplink delay time may be
- the uplink delay may be obtained by repeating the measurement of Tl up and T2 up a plurality of times and calculating the respective PathDelay up , and averaging the plurality of PathDelay up . In the case where multiple values of PathDelay up are obtained, it may be desirable to eliminate any values of PathDelay up that appears abnormal before averaging the plurality of
- the clock synchronisation between the master device and the slave device may be performed according to a IEEE1588 protocol or any other suitable clock synchronisation protocols.
- the offset between the master device and the slave device may be calculated using the expression
- Asm is an absolute delay between the slave device and the master device.
- the absolute delay Asm represents systematic delays between the time at which the master device sends a signal until the time at which the slave device receives the signal, which may include processes that take place within the master device from the time the signal is generated to the time the signal is timestamped by the master device, and from the time the signal is timestamped to the time at which the signal arrives at the physical interface of the master device.
- the downlink path delay PathDelay down and the uplink path delay PathDelay up represent delays caused only by network connections that respectively form the downlink connection and the uplink connection.
- the slave device may then adjust its clock accordingly to be in synchronisation with the master device.
- PathDelay d0W n and PathDelay up may be
- the quantity (PathDelay d0W n - PathDelay Up ) /2 represents the asymmetry between the delay in the downlink connection and the delay in the uplink connection.
- FIG. 3 and Figure 4 An example of a communication system that performs clock synchronisation using the method described above is shown in Figure 3 and Figure 4.
- the communication system comprises a master device 310 or 310' and a slave device 320.
- the slave device 320 is connected to the master device 310 or 310' via a downlink connection and an uplink connection.
- the connections may be optical waveguides such as optical fibres.
- connections may include multiple connections, for example, via a switch or a router.
- the master device 310 comprises a synchronization module 311, a network interface controller such as a MAC chip 312, a timestamp module 313, a clock module 314 and a loopback module 315.
- the loopback module 315 may be a loopback device, an optical beam splitter, or any other devices suitable for looping back an optical signal.
- the slave device 320 comprises a synchronization module 321, a network interface controller such as a MAC chip 322, a timestamp module 323, a clock module 324 and an optical module 325.
- the slave device 320 is connected to the master device 310 by a downlink optical fibre and an uplink optical fibre. One end of the downlink optical fibre is connected to the slave device 320 via the optical module 325. The other end of the downlink optical fibre is connected to the master device 310 via the loopback module 315. [0027] In the example, referring to Figure 3, the
- the optical module 325 sends the downlink delay test message down the downlink optical fibre, and the timestamp module 323 records the time at which the downlink delay test message is sent as a first transmission time Tl down .
- the loopback module 315 of the master device 310 receives the downlink delay test message via the downlink optical fibre and loops the downlink delay test message back down the downlink optical fibre.
- the optical module 325 receives the downlink delay test message looped back by the master device 310 via the downlink optical fibre, and the timestamp module 323 records the time at which the downlink delay test message is received as a first reception time T2 down .
- the timestamp module 323 then calculates a downlink delay time based on the first transmission time Tl down and the first reception time T2 down .
- the timestamp module may be
- the slave device 320 in Figure 4 is essentially the same as the slave device 320 in Figure 3.
- the master device 310' is an alternative
- the loopback module 315' is connected to the uplink optical fibre instead of the downlink optical fibre.
- the loopback module 315 may simply be moved from the downlink optical fibre to the uplink optical fibre, thus preserving measurement consistency.
- a loopback module 315' different from the loopback module 315 may be used
- the master device 310 may be provided with two loopback modules each respectively connected to the downlink optical fibre and the uplink optical fibre.
- the synchronization module 311 of the slave device 320 then generates an uplink delay test message (second test signal) and forwards the uplink delay test message to the optical module 325 via the MAC chip 322.
- the optical module 325 sends the uplink delay test message down the uplink optical fibre, and the timestamp module 323 records the time at which the uplink delay test message is sent as a second transmission time Tl up .
- the loopback module 315' of the master device 310 receives the uplink delay test message via the uplink optical fibre and loops the uplink delay test message back down the uplink optical fibre.
- the optical module 325 receives the uplink delay test message looped back by the master device 310 via the uplink optical fibre, and the timestamp module 323 records the time at which the uplink delay test message is received as a second reception time T2 up .
- the timestamp module 323 then calculates an uplink delay time based on the second transmission time Tl up and the second reception time T2 up .
- the timestamp module 323 calculates a time offset between the master device and the slave device based on the downlink delay time and the uplink delay time. [0036] In an example, the timestamp module 323 may be configured to calculate the uplink delay time by
- the optical module 325 may be any suitable optical module including a single strand
- the loopback module 315 and 315' may be any suitable loopback device including a beam splitter.
- transmission time and the reception time of a test signal may be collected at the slave device that is the side to be synchronised, thus it is possible to improve efficiency.
- the clock synchronisation method is applied to IEEE1588 protocol.
- the clock synchronisation method may be applied to various versions of IEEE1588 and other time synchronisation protocols such as NTP.
- the flow diagrams described above show a specific order of execution, the order of execution may differ from that which is depicted.
- the above examples can be implemented by hardware, software, firmware, or a combination thereof.
- the various methods and functional modules described herein may be implemented by a processor (the term processor is to be interpreted broadly to include a CPU, processing unit, ASIC, logic unit, or programmable gate array etc.) .
- the methods and functional modules may all be performed by a single processor or divided amongst several processers.
- the methods and functional modules may be implemented as machine readable instructions executable by one or more processors, hardware logic circuitry of the one or more processors, or a combination thereof. Further, the
- teachings herein may be implemented in the form of a software product, the computer software product being stored in a storage medium and comprising a plurality of instructions for making a computer device (e.g. a personal computer, a server or a network device such as a router, switch, access point etc.) implement the method recited in the examples of the present disclosure.
- a computer device e.g. a personal computer, a server or a network device such as a router, switch, access point etc.
- a computer device e.g. a personal computer, a server or a network device such as a router, switch, access point etc.
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- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Optical Communication System (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/373,869 US20150244455A1 (en) | 2012-03-27 | 2013-03-08 | Calculating time offset |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210084146.XA CN102638324B (zh) | 2012-03-27 | 2012-03-27 | 一种实现精确时间同步的方法和装置 |
| CN201210084146.X | 2012-03-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2013143385A1 true WO2013143385A1 (fr) | 2013-10-03 |
Family
ID=46622580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/CN2013/072354 Ceased WO2013143385A1 (fr) | 2012-03-27 | 2013-03-08 | Calcul de décalage temporel |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102638324B (fr) |
| WO (1) | WO2013143385A1 (fr) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3334090A1 (fr) * | 2016-12-08 | 2018-06-13 | InCoax Networks Europe AB | Procédé et système de synchronisation de dispositifs de noeud dans un réseau coaxial |
| US11199868B2 (en) | 2016-12-08 | 2021-12-14 | Zhengzhou Yunhai Information Technology Co., Ltd. | Clock skew correction method, device and system |
| WO2023106922A1 (fr) * | 2021-12-08 | 2023-06-15 | Technische Universiteit Delft | Procédé et système de détermination d'une latence aller-retour d'un canal de communication quantique |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102638324B (zh) * | 2012-03-27 | 2014-12-17 | 杭州华三通信技术有限公司 | 一种实现精确时间同步的方法和装置 |
| CN104168077B (zh) * | 2014-07-04 | 2017-02-08 | 上海交通大学 | 高精度光纤双向时间比对方法与系统 |
| CN104202137A (zh) * | 2014-07-09 | 2014-12-10 | 北京东土科技股份有限公司 | 一种基于e1链路的ieee1588时钟同步方法、系统及装置 |
| CN104464247B (zh) * | 2014-12-12 | 2018-01-02 | 武汉中原电子信息公司 | 一种降低集中器公网对时误差的方法 |
| CN104993900B (zh) * | 2015-07-06 | 2018-03-09 | 江苏省电力公司南京供电公司 | 一种基于ieee1588时钟模型的同步校正方法 |
| CN108234056B (zh) * | 2018-01-17 | 2019-12-24 | 四川泰富地面北斗科技股份有限公司 | 采用同波长半双工方式的单纤双向时间传递方法与系统 |
| CN113439397B (zh) * | 2019-02-25 | 2022-12-27 | 华为技术有限公司 | 一种时间同步方法、装置及系统 |
| CN112085868A (zh) * | 2020-09-18 | 2020-12-15 | 陕西千山航空电子有限责任公司 | 一种多采集记录系统时统方法及系统 |
| CN114696896B (zh) * | 2020-12-30 | 2024-11-29 | 华为技术有限公司 | 一种延时测量方法以及装置 |
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| CN101296048B (zh) * | 2008-06-17 | 2011-04-20 | 杭州华三通信技术有限公司 | 一种时间同步方法及设备 |
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| CN102255791B (zh) * | 2010-05-21 | 2013-12-18 | 中国移动通信集团公司 | 确定设备间链路延迟量的方法及系统 |
| CN102325019B (zh) * | 2011-08-23 | 2014-10-15 | 西安电子科技大学 | 一种实时工业以太网EtherCAT冗余系统的时钟同步方法 |
-
2012
- 2012-03-27 CN CN201210084146.XA patent/CN102638324B/zh active Active
-
2013
- 2013-03-08 WO PCT/CN2013/072354 patent/WO2013143385A1/fr not_active Ceased
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101018086A (zh) * | 2006-02-10 | 2007-08-15 | 大唐移动通信设备有限公司 | 时分同步码分多址系统中中继放大器的同步收发控制方法与系统 |
| CN101102131A (zh) * | 2006-07-03 | 2008-01-09 | 中兴通讯股份有限公司 | 远端射频单元的传输延时测量方法 |
| CN102104572A (zh) * | 2009-12-22 | 2011-06-22 | 华为技术有限公司 | 传输系统中的时间同步方法、设备及系统 |
| JP2012034080A (ja) * | 2010-07-29 | 2012-02-16 | Fuji Electric Co Ltd | ネットワークシステム |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3334090A1 (fr) * | 2016-12-08 | 2018-06-13 | InCoax Networks Europe AB | Procédé et système de synchronisation de dispositifs de noeud dans un réseau coaxial |
| WO2018106178A1 (fr) * | 2016-12-08 | 2018-06-14 | Incoax Networks Ab | Procédé et système de synchronisation de dispositifs de nœud dans un réseau coaxial |
| CN110100388A (zh) * | 2016-12-08 | 2019-08-06 | 因库艾克斯网络公司 | 用于同轴网络中节点设备的同步的方法和系统 |
| US10749779B2 (en) | 2016-12-08 | 2020-08-18 | Incoax Networks Ab | Method and system for synchronization of node devices in a coaxial network |
| US11199868B2 (en) | 2016-12-08 | 2021-12-14 | Zhengzhou Yunhai Information Technology Co., Ltd. | Clock skew correction method, device and system |
| WO2023106922A1 (fr) * | 2021-12-08 | 2023-06-15 | Technische Universiteit Delft | Procédé et système de détermination d'une latence aller-retour d'un canal de communication quantique |
| NL2030076B1 (en) * | 2021-12-08 | 2023-06-22 | Univ Delft Tech | Method and system for determining a round-trip latency of a communication channel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102638324B (zh) | 2014-12-17 |
| CN102638324A (zh) | 2012-08-15 |
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