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WO2013032279A1 - Method of manufacturing substrate for chip packages - Google Patents

Method of manufacturing substrate for chip packages Download PDF

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Publication number
WO2013032279A1
WO2013032279A1 PCT/KR2012/007002 KR2012007002W WO2013032279A1 WO 2013032279 A1 WO2013032279 A1 WO 2013032279A1 KR 2012007002 W KR2012007002 W KR 2012007002W WO 2013032279 A1 WO2013032279 A1 WO 2013032279A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit pattern
chip packages
pattern layers
layers
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2012/007002
Other languages
French (fr)
Inventor
Tea Hyuk Kang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Innotek Co Ltd
Original Assignee
LG Innotek Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Innotek Co Ltd filed Critical LG Innotek Co Ltd
Publication of WO2013032279A1 publication Critical patent/WO2013032279A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages

Definitions

  • the present invention relates to a method of manufacturing a substrate for chip packages.
  • a silicon chip or an LED (light emitting diode) chip, a smart IC chip and the like are bonded onto a substrate using a wire bonding method or an LOC (lead on chip) bonding method.
  • FIG. 1 is a view showing a conventional process of manufacturing a substrate for chip packages.
  • an insulation layer 110 is first prepared (S1).
  • the insulation layer 110 may be formed of an insulating film, for example, a polyimide film.
  • via holes 112 are formed in the insulation layer 110 (S2).
  • a metal layer 120 is laminated on the insulation layer 120 (S3).
  • the metal layer 120 may be composed of Cu.
  • a surface of the metal layer is activated through various chemical treatments, a photoresist is then applied thereto, and exposure and development processes are performed.
  • a necessary circuit is formed by an etching process, and a circuit pattern layer 120 is formed by peeling off the photoresist (S4).
  • one surface of the circuit pattern layer 120 namely, an upper surface becomes a contact area.
  • Another surface of the circuit pattern layer 120 namely, a lower surface is bonded to the substrate of chip packages. Therefore, the surface bonded to the substrate of the circuit pattern layer 120 becomes a bonding area.
  • the contact area of the circuit pattern layer 120 may be plated with Ni, Pd, and Au in order.
  • the bonding area of the circuit pattern layer 120 may be plated with Ni, and Au in order.
  • the insulation layer 110 which is exposed to the outside by a circuit pattern of the insulation layer 110 and the circuit pattern layer 120 may be composed of an insulating material such as polyimide or resins. Thus, the insulation layer is not plated in principle.
  • the bonding area of the circuit pattern layer 120 and the contact area of the circuit pattern layer 120 may be plated with different methods or materials from each other in order to implement their own physical properties or desired characteristics.
  • the bonding area of the circuit pattern layer 120 is plated, the bonding area of the circuit pattern layer 120 is masked on the insulation layer 110 using a first mask part 120 so that the plating of the contact area of the circuit pattern layer 120 has no effect on the bonding area of the circuit pattern layer 120, and the contact area of the circuit pattern layer 120 is plated (S5).
  • the present invention has been made keeping in mind the above problems, and an aspect of the present invention provides a method of manufacturing a substrate for chip packages which simplifies processes of the substrate for chip packages.
  • a method of manufacturing a substrate for chip packages comprising: forming two substrates for chip packages comprising circuit pattern layers having bonding areas on one surface and contact areas on another surface, insulation layers bonded to the bonding areas of the circuit pattern layers, respectively; attaching the insulation layers of the two substrates for chip packages to both surfaces of a first double-sided adhesive sheet, respectively; plating the contact areas of the circuit pattern layers of the two substrates for chip packages; separating the insulation layers from the first double-sided adhesive sheet; attaching the contact areas of the circuit pattern layers of the two substrates for chip packages to both surfaces of a second double-sided adhesive sheet, respectively; and plating the bonding areas of the circuit pattern layers of the two substrates for chip packages.
  • the method of manufacturing the substrate for chip packages may further include separating the contact areas of the circuit pattern layers from the second double-sided adhesive sheet.
  • the method of manufacturing the substrate for chip packages may further include plating the contact areas of the circuit pattern layers using Ni, Pd, and Au in order.
  • the method of manufacturing the substrate for chip packages may further include plating the bonding areas of the circuit pattern layers using Ni and Au in order.
  • the plating of the contact areas of the circuit pattern layers may be performed by a different method from the plating of the bonding areas of the circuit pattern layers.
  • the first double-sided adhesive sheet and the second double-sided adhesive sheet may be implemented as one sheet.
  • the forming of the substrate for chip packages may include forming via holes in the insulation layer, laminating a metal layer on one surface of the insulation layer, and forming the circuit pattern layer by patterning the metal layer.
  • the metal layer may be composed of Cu.
  • the metal layer may be patterned by an etching process.
  • the contact areas or the bonding areas of two substrates for chip packages can be plated at a time using the double-sided adhesive film or the sheet without a masking process.
  • FIG. 1 is a view showing a conventional process of manufacturing a substrate for chip packages.
  • FIG. 2 is a view showing a process of manufacturing a substrate for chip packages according to a preferred exemplary embodiment of the present invention.
  • FIG. 2 is a view showing a process of manufacturing a substrate for chip packages according to a preferred exemplary embodiment of the present invention.
  • an insulation layer 210 is first prepared (S10).
  • the insulation layer 210 may be formed of a polyimide film.
  • via holes 112 are formed in the insulation layer 210 (S20).
  • the via holes formed by passing through the insulation layer 210 may include an optical device, namely, via holes on which chips are mounted, via holes for electrically connecting each layer, thermal via holes for easily diffusing heat, and via holes which become a basis for the array of each layer.
  • a metal layer 220 is laminated on the insulation layer 220 (S30).
  • the metal layer 220 may be composed of Cu.
  • a surface of the metal layer is activated through various chemical treatments, a photoresist is then applied thereto, and exposure and development processes are performed.
  • a necessary circuit is formed by an etching process, and a circuit pattern layer 220 is formed by peeling off the photoresist (S40). That is, the circuit pattern layer is formed by patterning the metal layer 220.
  • one surface of the circuit pattern layer 220 namely, an upper surface becomes a contact area.
  • Another surface of the circuit pattern layer 220 namely, a lower surface is bonded to the substrate of LED packages. Therefore, the surface which is bonded to the substrate of the circuit pattern layer 220 becomes a bonding area.
  • the insulation layer 210 in which the via holes 212 are formed, and a substrate for chip packages 310 to which the circuit pattern layer 220 are bonded may be manufactured.
  • the insulation layer 210 in which the via holes 212 are formed, and a substrate for chip packages 310 to which the circuit pattern layer 220 are bonded may be manufactured.
  • at least two substrates for chip packages 310 and 320 may be manufactured.
  • the insulation layers 210 of the two substrates for the chip packages manufactured as described above are attached to a film whose both surfaces are coated with an adhesive or both surfaces of a double-sided adhesive sheet 230, respectively (S50).
  • each insulation layer 210 of the two substrates for chip packages 310 is attached to the film or the both surfaces of the sheet 230. That is, the insulation layer 210 of one substrate for chip packages 310 is attached to the adhesive film or one surface of the sheet 230.
  • the insulation layer 210 of another substrate for chip packages 320 is attached to the adhesive film or another surface of the sheet 230.
  • the insulation layers of the substrate for chip packages 310 and 320 are masked by the adhesive film or the sheet 230.
  • a part of the circuit pattern layer 220 which is exposed by the via holes of the insulation layers 210, namely, the bonding areas of the circuit pattern layer 220 are also masked.
  • the contact area of the circuit pattern layer 220 of one substrate for chip packages 310, and the contact area of the circuit pattern layer 220 of another one substrate for chip packages 320 are exposed to the outside. Then, the contact areas of the circuit pattern layer 220 of two substrates for chip packages 310 and 320 may be plated at a time and using the same method.
  • the contact areas of the circuit pattern layer 220 are plated several times using a plurality of metals, for example, Ni, Pd, and Au in order (S50).
  • the present invention is not limited to this, and the circuit pattern layer 220 may be plated using one metal.
  • the insulation layer 210 which is exposed to the outside by a circuit pattern of the circuit pattern layer 120 may be composed of an insulating material such as polyimide or resins. Thus, the insulation layer is not plated in principle.
  • the two substrates for chip packages 310 and 320 are separated from the adhesive film or the sheet 230 (S60).
  • the contact areas of the circuit pattern layer 220 of the two substrates for chip packages 310 and 320 are attached to a film whose both surfaces are coated with an adhesive, or both surfaces of a double-sided adhesive sheet 240, respectively (S70).
  • each circuit pattern layer 220 of the two substrates for chip packages 310 and 320 are attached to the film or both surfaces of the sheet 240. That is, the contact area of the circuit pattern layer 220 of one substrate for chip packages 310 is attached to the adhesive film or one surface of the sheet 240. Furthermore, the contact area of the circuit pattern layer 220 of another one substrate for chip packages 320 is attached to the adhesive film or another surface of the sheet 240.
  • the contact areas of the circuit pattern layers of the substrates for chip packages 310 and 320 are masked by the adhesive film or the sheet 240.
  • some parts of the circuit pattern layers are exposed by the via holes of the insulation layers 210.
  • the bonding area of the circuit pattern layer 220 of one substrate for chip packages 310, and the bonding area of the circuit pattern layer 220 of another one substrate for chip packages 320 are exposed to the outside.
  • the bonding areas of the circuit pattern layer 220 of two substrates for chip packages 310 and 320 may be plated at a time and using the same method.
  • the bonding areas of the circuit pattern layer 220 are plated several times using the plurality of metals, for example, Ni, and Au in order.
  • the present invention is not limited to this, and the bonding area of the circuit pattern layer 220 may be plated using one metal.
  • the insulation layer 110 may be composed of the insulating material such as polyimide or resins. Thus, the insulation layer is not plated in principle.
  • the contact area of the circuit pattern layer 220 is plated, and thereafter, the bonding area of the circuit pattern layer 220 is plated, but the present invention is not limited to this.
  • the orders of the processes of plating the contact areas of the circuit pattern layer 220 and the bonding areas of the circuit pattern layer 220 may be changed according to a condition for the manufacturing process or other conditions.
  • the adhesive film or the sheet 230 attached to the insulation layers 210 is different from the adhesive film or the sheet 240 attached to the contact areas of the circuit pattern layers.
  • these adhesive sheets 230 and 240 may be implemented as one adhesive sheet.
  • these adhesive sheets 230 and 240 may be formed of a same material as each other. For example, after plating the contact areas of the circuit pattern layers or after plating the bonding areas of the circuit pattern layers 220, the insulation layers or the circuit pattern layers are separated from the adhesive film or the sheet so that they can be again used.
  • the contact areas or the bonding areas of the two substrates for chip packages may be plated at a time using the double-sided adhesive film or the sheet without any masking process.
  • the processes for plating the contact areas or the bonding areas of the two substrates for chip packages are simplified, thereby reducing the costs and time.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Provided is a method of manufacturing a substrate for chip packages, comprising: forming two substrates for chip packages comprising circuit pattern layers having bonding areas on one surface thereof and contact areas on another surface thereof, and insulation layers bonded to the bonding areas of the circuit pattern layers, respectively; attaching the insulation layers of the two substrates for chip packages to both surfaces of a first double-sided adhesive sheet, respectively; plating the contact areas of the circuit pattern layers of the two substrates for chip packages separating the insulation layers from the first double-sided adhesive sheet; attaching the contact areas of the circuit pattern layers of the two substrate for chip packages to both surfaces of a second double-sided adhesive sheet, respectively; and plating the bonding areas of the circuit pattern layers of the two substrate for chip packages.

Description

METHOD OF MANUFACTURING SUBSTRATE FOR CHIP PACKAGES
The present invention relates to a method of manufacturing a substrate for chip packages.
The technologies relating to a semiconductor or an optical device have been steadily developed to meet the requirements for high densification, miniaturization, and high performance. However, because the technologies have relatively fallen behind technologies for manufacturing a semiconductor, attempts have been recently made to settle the requirements for high performance, miniaturization and high densification by the development of technologies relating to packages.
With regard to semiconductors/optical device packages, a silicon chip or an LED (light emitting diode) chip, a smart IC chip and the like are bonded onto a substrate using a wire bonding method or an LOC (lead on chip) bonding method.
FIG. 1 is a view showing a conventional process of manufacturing a substrate for chip packages.
Referring to FIG. 1, an insulation layer 110 is first prepared (S1). The insulation layer 110 may be formed of an insulating film, for example, a polyimide film. After preparing the insulation layer 110, via holes 112 are formed in the insulation layer 110 (S2).
Subsequently, a metal layer 120 is laminated on the insulation layer 120 (S3). The metal layer 120 may be composed of Cu. Then, a surface of the metal layer is activated through various chemical treatments, a photoresist is then applied thereto, and exposure and development processes are performed. After completing the development process, a necessary circuit is formed by an etching process, and a circuit pattern layer 120 is formed by peeling off the photoresist (S4).
Here, one surface of the circuit pattern layer 120, namely, an upper surface becomes a contact area. Another surface of the circuit pattern layer 120, namely, a lower surface is bonded to the substrate of chip packages. Therefore, the surface bonded to the substrate of the circuit pattern layer 120 becomes a bonding area.
Here, the contact area of the circuit pattern layer 120 may be plated with Ni, Pd, and Au in order. The bonding area of the circuit pattern layer 120 may be plated with Ni, and Au in order. In this case, the insulation layer 110 which is exposed to the outside by a circuit pattern of the insulation layer 110 and the circuit pattern layer 120 may be composed of an insulating material such as polyimide or resins. Thus, the insulation layer is not plated in principle.
Like this, the bonding area of the circuit pattern layer 120 and the contact area of the circuit pattern layer 120 may be plated with different methods or materials from each other in order to implement their own physical properties or desired characteristics. In this case, when the contact area of the circuit pattern layer 120 is plated, the bonding area of the circuit pattern layer 120 is masked on the insulation layer 110 using a first mask part 120 so that the plating of the contact area of the circuit pattern layer 120 has no effect on the bonding area of the circuit pattern layer 120, and the contact area of the circuit pattern layer 120 is plated (S5).
That is, to be similar to this, when the bonding area of the circuit pattern layer 120 is plated, an exposed surface, namely, the contact area of the circuit pattern layer 120 is masked using a first mask part 140 so that the plating of the bonding area of the circuit pattern layer 120 has no effect on the contact area of the circuit pattern layer 120, and the bonding area of the circuit pattern layer 120 is plated (S6).
Like this, the conventional process in which the bonding area of the circuit pattern layer 120 and the contact area of the circuit pattern layer 120 are separately plated is very complex. Furthermore, and the process required much time and costs.
The present invention has been made keeping in mind the above problems, and an aspect of the present invention provides a method of manufacturing a substrate for chip packages which simplifies processes of the substrate for chip packages.
According to an aspect of the present invention, there is provided a method of manufacturing a substrate for chip packages according to an exemplary embodiment, the method comprising: forming two substrates for chip packages comprising circuit pattern layers having bonding areas on one surface and contact areas on another surface, insulation layers bonded to the bonding areas of the circuit pattern layers, respectively; attaching the insulation layers of the two substrates for chip packages to both surfaces of a first double-sided adhesive sheet, respectively; plating the contact areas of the circuit pattern layers of the two substrates for chip packages; separating the insulation layers from the first double-sided adhesive sheet; attaching the contact areas of the circuit pattern layers of the two substrates for chip packages to both surfaces of a second double-sided adhesive sheet, respectively; and plating the bonding areas of the circuit pattern layers of the two substrates for chip packages.
The method of manufacturing the substrate for chip packages may further include separating the contact areas of the circuit pattern layers from the second double-sided adhesive sheet.
The method of manufacturing the substrate for chip packages may further include plating the contact areas of the circuit pattern layers using Ni, Pd, and Au in order.
The method of manufacturing the substrate for chip packages may further include plating the bonding areas of the circuit pattern layers using Ni and Au in order.
The plating of the contact areas of the circuit pattern layers may be performed by a different method from the plating of the bonding areas of the circuit pattern layers.
The first double-sided adhesive sheet and the second double-sided adhesive sheet may be implemented as one sheet.
The forming of the substrate for chip packages may include forming via holes in the insulation layer, laminating a metal layer on one surface of the insulation layer, and forming the circuit pattern layer by patterning the metal layer.
The metal layer may be composed of Cu.
The metal layer may be patterned by an etching process.
In accordance with the exemplary embodiment of the present invention, the contact areas or the bonding areas of two substrates for chip packages can be plated at a time using the double-sided adhesive film or the sheet without a masking process. Thus, according to the present invention, it is advantageous that the processes for plating the contact areas or the bonding areas of the two substrates for chip packages are simplified, thereby reducing the costs and time.
The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain principles of the present invention. In the drawings:
FIG. 1 is a view showing a conventional process of manufacturing a substrate for chip packages.
FIG. 2 is a view showing a process of manufacturing a substrate for chip packages according to a preferred exemplary embodiment of the present invention.
Exemplary embodiments according to the present invention will now be described more fully hereinafter with reference to the accompanying drawings. Meanwhile, when it is determined that specific descriptions regarding publicly known relevant functions or configurations may unnecessarily be beside main points of the present invention, corresponding descriptions are omitted.
Furthermore, sizes of each element in the drawings can be exaggerated for the convenience of the descriptions, which does not reflect the actual sizes of the corresponding elements.
FIG. 2 is a view showing a process of manufacturing a substrate for chip packages according to a preferred exemplary embodiment of the present invention.
Referring to FIG. 2, an insulation layer 210 is first prepared (S10). The insulation layer 210 may be formed of a polyimide film. After preparing the insulation layer 210, via holes 112 are formed in the insulation layer 210 (S20). The via holes formed by passing through the insulation layer 210 may include an optical device, namely, via holes on which chips are mounted, via holes for electrically connecting each layer, thermal via holes for easily diffusing heat, and via holes which become a basis for the array of each layer.
Subsequently, a metal layer 220 is laminated on the insulation layer 220 (S30). The metal layer 220 may be composed of Cu. Then, a surface of the metal layer is activated through various chemical treatments, a photoresist is then applied thereto, and exposure and development processes are performed. After completing the development process, a necessary circuit is formed by an etching process, and a circuit pattern layer 220 is formed by peeling off the photoresist (S40). That is, the circuit pattern layer is formed by patterning the metal layer 220.
Here, one surface of the circuit pattern layer 220, namely, an upper surface becomes a contact area. Another surface of the circuit pattern layer 220, namely, a lower surface is bonded to the substrate of LED packages. Therefore, the surface which is bonded to the substrate of the circuit pattern layer 220 becomes a bonding area.
Like this, through processes S10 to S40, the insulation layer 210 in which the via holes 212 are formed, and a substrate for chip packages 310 to which the circuit pattern layer 220 are bonded may be manufactured. By repeatedly or simultaneously performing the processes, at least two substrates for chip packages 310 and 320 may be manufactured.
Subsequently, the insulation layers 210 of the two substrates for the chip packages manufactured as described above are attached to a film whose both surfaces are coated with an adhesive or both surfaces of a double-sided adhesive sheet 230, respectively (S50). Specifically, each insulation layer 210 of the two substrates for chip packages 310 is attached to the film or the both surfaces of the sheet 230. That is, the insulation layer 210 of one substrate for chip packages 310 is attached to the adhesive film or one surface of the sheet 230. Furthermore, the insulation layer 210 of another substrate for chip packages 320 is attached to the adhesive film or another surface of the sheet 230.
As a result of this, the insulation layers of the substrate for chip packages 310 and 320 are masked by the adhesive film or the sheet 230. Thus, a part of the circuit pattern layer 220 which is exposed by the via holes of the insulation layers 210, namely, the bonding areas of the circuit pattern layer 220 are also masked.
Therefore, as illustrated in FIG. 2, the contact area of the circuit pattern layer 220 of one substrate for chip packages 310, and the contact area of the circuit pattern layer 220 of another one substrate for chip packages 320 are exposed to the outside. Then, the contact areas of the circuit pattern layer 220 of two substrates for chip packages 310 and 320 may be plated at a time and using the same method. The contact areas of the circuit pattern layer 220 are plated several times using a plurality of metals, for example, Ni, Pd, and Au in order (S50). Of course, the present invention is not limited to this, and the circuit pattern layer 220 may be plated using one metal. In this case, the insulation layer 210 which is exposed to the outside by a circuit pattern of the circuit pattern layer 120 may be composed of an insulating material such as polyimide or resins. Thus, the insulation layer is not plated in principle.
Then, the two substrates for chip packages 310 and 320 are separated from the adhesive film or the sheet 230 (S60).
Subsequently, the contact areas of the circuit pattern layer 220 of the two substrates for chip packages 310 and 320 are attached to a film whose both surfaces are coated with an adhesive, or both surfaces of a double-sided adhesive sheet 240, respectively (S70).
Specifically, the contact areas of each circuit pattern layer 220 of the two substrates for chip packages 310 and 320 are attached to the film or both surfaces of the sheet 240. That is, the contact area of the circuit pattern layer 220 of one substrate for chip packages 310 is attached to the adhesive film or one surface of the sheet 240. Furthermore, the contact area of the circuit pattern layer 220 of another one substrate for chip packages 320 is attached to the adhesive film or another surface of the sheet 240.
As a result of this, the contact areas of the circuit pattern layers of the substrates for chip packages 310 and 320 are masked by the adhesive film or the sheet 240. Thus, some parts of the circuit pattern layers are exposed by the via holes of the insulation layers 210. In other words, the bonding area of the circuit pattern layer 220 of one substrate for chip packages 310, and the bonding area of the circuit pattern layer 220 of another one substrate for chip packages 320 are exposed to the outside.
Subsequently, the bonding areas of the circuit pattern layer 220 of two substrates for chip packages 310 and 320 may be plated at a time and using the same method. The bonding areas of the circuit pattern layer 220 are plated several times using the plurality of metals, for example, Ni, and Au in order. Of course, the present invention is not limited to this, and the bonding area of the circuit pattern layer 220 may be plated using one metal. When plating the bonding area of the circuit pattern layer, the insulation layer 110 may be composed of the insulating material such as polyimide or resins. Thus, the insulation layer is not plated in principle.
Meanwhile, in the present exemplary embodiment, the contact area of the circuit pattern layer 220 is plated, and thereafter, the bonding area of the circuit pattern layer 220 is plated, but the present invention is not limited to this. In other words, the orders of the processes of plating the contact areas of the circuit pattern layer 220 and the bonding areas of the circuit pattern layer 220 may be changed according to a condition for the manufacturing process or other conditions.
Furthermore, in the present exemplary embodiment, it is illustrated that the adhesive film or the sheet 230 attached to the insulation layers 210 is different from the adhesive film or the sheet 240 attached to the contact areas of the circuit pattern layers. However, these adhesive sheets 230 and 240 may be implemented as one adhesive sheet. Alternatively, these adhesive sheets 230 and 240 may be formed of a same material as each other. For example, after plating the contact areas of the circuit pattern layers or after plating the bonding areas of the circuit pattern layers 220, the insulation layers or the circuit pattern layers are separated from the adhesive film or the sheet so that they can be again used.
According to the present exemplary embodiment of the present invention, in a case where the contact areas and the bonding areas of the substrate for chip packages 310 having the insulation layers 210 in which the via holes 212 are formed, and the circuit pattern layers 220 located on the insulation layer 210 are plated using different methods from each other or with different materials from each other, or different numbers of times from each other, the contact areas or the bonding areas of the two substrates for chip packages may be plated at a time using the double-sided adhesive film or the sheet without any masking process. Thus, according to the present invention, it is advantageous that the processes for plating the contact areas or the bonding areas of the two substrates for chip packages are simplified, thereby reducing the costs and time.
As previously described, in the detailed description of the invention, having described the detailed exemplary embodiments of the invention, it should be apparent that modifications and variations can be made by persons skilled without deviating from the spirit or scope of the invention. Therefore, it is to be understood that the foregoing is illustrative of the present invention and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims and their equivalents.

Claims (14)

  1. A method of manufacturing a substrate for chip packages, comprising:
    forming two substrates for chip packages comprising circuit pattern layers having bonding areas on one surface thereof and contact areas on another surface thereof, and insulation layers bonded to the bonding areas of the circuit pattern layers, respectively;
    attaching the insulation layers of the two substrates for chip packages to both surfaces of a first double-sided adhesive sheet, respectively;
    plating the contact areas of the circuit pattern layers of the two substrates for chip packages;
    separating the insulation layers from the first double-sided adhesive sheet;
    attaching the contact areas of the circuit pattern layers of the two substrate for chip packages to both surfaces of a second double-sided adhesive sheet, respectively; and
    plating the bonding areas of the circuit pattern layers of the two substrate for chip packages.
  2. The method of claim 1, further comprising separating the contact areas of the circuit pattern layers from the second double-sided adhesive sheet.
  3. The method of claim 1, further comprising plating the contact areas of the circuit pattern layers using Ni, Pd, and Au in order.
  4. The method of claim 1, further comprising plating the bonding areas of the circuit pattern layers using Ni and Au in order.
  5. The method of claim 1,wherein the plating of the contact areas of the circuit pattern layers is carried out by a different method from the plating of the bonding areas of the circuit pattern layers.
  6. The method of claim 1, wherein the first double-sided adhesive sheet and the second double-sided adhesive sheet is implemented as one sheet.
  7. The method of claim 1, wherein the forming of the substrate for chip packages comprises: forming via holes in the insulation layers laminating a metal layer on one surface of the insulation layers and patterning the metal layer to form the circuit pattern layers.
  8. The method of claim 7, wherein the metal layer is composed of Cu.
  9. The method of claim 7, wherein the metal layer is patterned by an etching process.
  10. A method of manufacturing a substrate for chip packages, comprising:
    forming two substrates for chip packages comprising circuit pattern layers having bonding areas on one surface thereof and contact areas on another surface thereof, and insulation layers bonded to the bonding areas of the circuit pattern layers, respectively;
    attaching the contact areas of the circuit pattern layers of the two substrates for chip packages to both surfaces of a first double-sided adhesive sheet, respectively;
    plating the bonding areas of the circuit pattern layers of the two substrates for chip packages;
    separating the circuit pattern layers from the first double-sided adhesive sheet;
    attaching the insulation layers of the two substrates for chip packages to both surfaces of a second double-sided adhesive sheet, respectively; and
    plating the contact areas of the circuit pattern layers of the two substrates for chip packages.
  11. The method of claim 10, further comprising separating the insulation layers from the second double-sided sheet.
  12. The method of claim 10, further comprising plating the contact areas of the circuit pattern layers using Ni, Pd, and Au in order.
  13. The method of claim 10, further comprising the bonding areas of the circuit pattern layers using Ni and Au in order.
  14. The method of claim 1, wherein the plating of the contact areas of the circuit pattern layers is performed by a different method from the plating of the bonding areas of the circuit pattern layers.
PCT/KR2012/007002 2011-09-02 2012-08-31 Method of manufacturing substrate for chip packages Ceased WO2013032279A1 (en)

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KR10-2011-0089070 2011-09-02
KR1020110089070A KR101776322B1 (en) 2011-09-02 2011-09-02 Method of manufacturing chip package member

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CN105701532B (en) * 2014-11-25 2018-09-11 茂邦电子有限公司 The wafer package part and its molding sheet shape package board and forming method of chip card

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JP2003179188A (en) * 2002-11-29 2003-06-27 Hitachi Chem Co Ltd Substrate for semiconductor package
US20060131755A1 (en) * 2004-03-31 2006-06-22 Endicott Interconnect Technologies, Inc. Method of making circuitized substrate
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JP2003179188A (en) * 2002-11-29 2003-06-27 Hitachi Chem Co Ltd Substrate for semiconductor package
US20060131755A1 (en) * 2004-03-31 2006-06-22 Endicott Interconnect Technologies, Inc. Method of making circuitized substrate
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KR20130025640A (en) 2013-03-12
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TW201330742A (en) 2013-07-16

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