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WO2013024128A1 - Ensemble de photocellules - Google Patents

Ensemble de photocellules Download PDF

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Publication number
WO2013024128A1
WO2013024128A1 PCT/EP2012/065979 EP2012065979W WO2013024128A1 WO 2013024128 A1 WO2013024128 A1 WO 2013024128A1 EP 2012065979 W EP2012065979 W EP 2012065979W WO 2013024128 A1 WO2013024128 A1 WO 2013024128A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
electrical
photocell
block
arrangement according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2012/065979
Other languages
German (de)
English (en)
Inventor
Harry Hedler
Susanne Kornely
Meinrad Schienle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Publication of WO2013024128A1 publication Critical patent/WO2013024128A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/103—Integrated devices the at least one element covered by H10F30/00 having potential barriers, e.g. integrated devices comprising photodiodes or phototransistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Definitions

  • the invention relates to an arrangement with a substrate with a photocell according to claim 1. Furthermore, the invention relates to a method for producing a device with a photocell according to claim 8.
  • various embodiments of photomultipliers are known. For example, from WO
  • the photomultiplier has an array of detector pixels, each detector pixel containing an array of detector cells.
  • Each detector cell includes a photodiode and a digital circuit coupled to the photodiode.
  • the digital circuit is designed to output a first digital value for an idle state and a second digital value for the detection of a photon by the photodiode.
  • the photocell is arranged on a silicon substrate. Furthermore, each photocell is associated with an electronic circuit for reading the signals.
  • the object of the invention is to provide an arrangement with a photocell and an electrical circuit, which is simple in construction and cost can be Herge ⁇ provides.
  • the object of the invention is achieved by the arrangement according to claim 1.
  • the object of the invention is to provide a cost-effective and simple method for producing an arrangement with a photocell and an electrical circuit. This object is achieved by the method according to claim 8. Further advantageous exporting ⁇ approximately embodiments of the invention are specified in the dependent claims.
  • the arrangement according to the invention has the advantage that a photocell with an electrical circuit in a simple and cost-effective manner can be made space-optimized.
  • the arrangement has a substrate which has a photocell on an upper side.
  • a via is provided, via which an electrically conductive connection between the photocell and a lower side of the substrate is produced.
  • a block with an electronic ⁇ African circuit is arranged, which performs a processing of the signal of the photocell.
  • the chosen arrangement a compact design can be achieved. Specifically, a short length of cable between the photocell and the electro ⁇ African block is er canal through the conductive via through the substrate.
  • a simply structured substrate with egg ner photocell can be used, wherein a further signal ⁇ processing is performed in a separate module.
  • the described method allows a simple and kos ⁇ -effective manufacture of a photomultiplier with an electronic circuit for processing the signal of the photocell.
  • electrical contacts are provided on the underside of the substrate, wherein the electrical ⁇ rule contacts with contacts of a further substrate are elekt ⁇ driven conductive contact.
  • a space-saving arrangement of the substrate with the photocell can be produced on a further substrate, for example a printed circuit board. Characterized a space-saving arrangement of the sub ⁇ strats can be allowed on the additional substrate in spite of the arrangement of the electrical block.
  • the via has two sections, wherein a first section, which extends from the top of the substrate a predetermined depth into the substrate, has a smaller diameter than the second section, which led from the bottom of the substrate to the first section is.
  • the required area on the upper side of the substrate, on which the photocells are arranged kept small and still achieved a low electrical resistance of the via.
  • the diameter of the first section are in the range from ⁇ 3-10 ym and the diameter of the second portion is in the range of 20 to 40 ym.
  • the electrical contacts of the underside of the substrate, which are connected to the further contacts of the further substrate are preferably in the form of ball contacts. In this way, a secure contact with low electrical resistance is possible.
  • an electrical circuit in particular a switch, is assigned to a photocell, wherein the read-out of the photocell can be influenced, in particular controlled, via the electrical circuit, in particular via the switch.
  • a switch for example, a transistor, in particular an NMOS transistor may be provided.
  • the block may be embodied, for example, as a CMOS-ASIC block.
  • CMOS-ASIC complementary metal-oxide-semiconductor
  • a reliable processing of the signal of the photocell can be made possible with a known technology.
  • a contact box provided which surrounds the at least fürmorie ⁇ tion and partially with an electrically conductive material of the via is electrically connected.
  • the contact surface may be applied to the top and / or the bottom prior to filling the via.
  • further line surfaces can be provided simultaneously with the contact surfaces, which are used for example for the electrical connection of the module or the photocell.
  • the plated-through hole is filled up with a warm liquid material, after which the liquid material changes into a solid state after a cooling process and represents the electrically conductive plated-through hole.
  • the substrate is at least partially constructed of silicon. In this way, a simple production of the photocells is made possible.
  • FIG. 1 shows a schematic side view of a
  • Figure 2 shows a partial schematic representation ei ⁇ ner plan view of the convex-assembly
  • FIG. 3 shows an arrangement with a substrate, an electrical component, wherein the sub-assembly strat on a further substrate angeord ⁇ net is;
  • FIG. 4 shows a schematic representation of a
  • FIGS. 5 to 13 show schematic representations of method sections for producing the substrate with the electrical component
  • Figure 14 is an evaluation circuit for the block.
  • FIG. 1 shows a schematic sectional view of a substrate 1 which has an active layer 2 with photocells on a top side.
  • Through-connections 3 are provided in the substrate 1, which realize an electrically conductive connection between an upper side of the substrate 1 and a lower side of the substrate 1.
  • a block 4 is arranged, which is electrically conductively connected to the plated-through holes 3.
  • contacts 5 in the form of contact balls are laterally offset on opposite sides of the module 4. Depending on the selected embodiment, it is possible to dispense with the contacts 5 or the contacts 5 can be formed in the form of a different geometry.
  • the contacts 5 are connected via not shown further electrical ⁇ cal lines with terminals of the module 4 and / or with at least one of the vias 3.
  • the photocells, not shown in Figure 1 are electrically connected via electrical lines at least one of the vias 3.
  • corresponding lines or line surfaces are provided on the upper side of the substrate 1, which are electrically connected to at least one of the plated-through holes 3.
  • the plated-through holes 3 are in the form of electrically conductive, for example perpendicular to the surface of the substrate
  • contact surfaces 6, 7 may be arranged on the upper side and / or on the underside of the substrate 1 for an improved electrically conductive connection.
  • the contact surfaces 6, 7 are made of an electrically conductive material and at least partially adjoin end pieces of the plated-through holes 3.
  • Preferably environmentally give the contact surfaces 6, 7 of the end pieces für Arimorie ⁇ stanchions 3 completely, for example in the form of a Ringflä ⁇ surface.
  • the module 4 has on a top side terminals 8 in the form of conductive contact surfaces which are connected to further associated terminals 9 of the substrate 1 or directly to the plated-through holes 3.
  • the module 4 may have electrical and / or electronic circuits, with which a processing of the signal of the photocells, in particular a digitization of the signal of the photocells, is performed and via the terminals, for example, to the contacts 5, forwarded.
  • the electrical and / or electronic circuit of the block 4 may be formed, for example, in the form of a CMOS-ASIC circuit.
  • the module 4 may also be formed in another semiconductor technology.
  • the plated-through holes 3 have two sections 10, 11 in the illustrated embodiment. From a first ⁇ cut 10 extends from the top of the substrate 1 to an egg ⁇ ner specified depth in the substrate 1. The second portion 11 extends from the underside of the substrate 1 to the first portion 10. The first and the second section 10
  • the diameter of the first portion 10 in the range of 3 to 10 ym and the diameter of the second portion 11 in the range of 20 to 40 yards.
  • the chosen embodiment saves 1 area on the upper side of the substrate and nevertheless a via is provided with a low electrical resistance.
  • the via can also have a constant diameter, which also need not have a diameter in the form of a circular disk.
  • the Englishjorierun- gen 3 comprise an electrically conductive material beispielswei ⁇ se SnAg (tin / silver) and are in direct contact with the first and second contact surfaces 6, 7.
  • the substrate is, for example, at least partly of Si ⁇ lizium prepared, in particular in the form of formed of a silicon layer.
  • the thickness of the substrate may be in the range of 100 ⁇ .
  • the arrangement according to FIG. 1 represents, for example, a silicon photomultiplier with avalanche photodiodes.
  • Figure 2 shows a schematic plan view of a Sectionaus ⁇ section of the surface of the substrate 1, wherein the fürkon- taktmaschineen 3 are shown.
  • the plated-through holes 3 are arranged offset from each other laterally, wherein the first diameter 12 of the first portion 10 in the form of a solid circular line and the second diameter 13 in the form of a dashed line in Figure 2 are shown.
  • FIG. 3 shows, in a further schematic representation, the arrangement of FIG. 1, which is arranged on a further substrate 14.
  • the contacts 5 are applied to third Victorflä ⁇ surfaces 15 of the further substrate 14 and electrically and mechanically connected to the third contact surfaces 15 °.
  • the further substrate 14 may for example comprise further electrical ⁇ -specific and / or electronic circuits for further processing of the signal of the photocells or be formed only in the form of a carrier with electrical lines via which the signal of the device is forwarded.
  • the further substrate 14 may also be formed as a carrier for a housing, with which the substrate 1 is covered from ⁇ .
  • signal lines 16 of the active layer 2, which are each connected to a through-connection 3, are shown on the upper side.
  • the signal lines 16 are in the illustrated embodiment with multiple Photozel ⁇ len in connection.
  • the individual photocells can preferably be activated via switches for reading out a signal to the signal line 16.
  • FIG. 4 shows an equivalent circuit diagram of a photocell 17 with a switch 18 in the form of a transistor.
  • the photocell 17 has a photodiode 19, which is formed for example in the form of an avalanche photodiode.
  • the photodiode 19 is connected in series with a resistor 20, which serves as an erosion resistor.
  • the photodiode 19 is connected to the positive supply voltage is applied with a supply line ⁇ Ver 21st
  • the resistor 20 is in turn connected to a ground line 22.
  • a control terminal 23 of the switch 18 is connected to a connecting line between the resistor 20 and the photodiode 19, a control terminal 23 of the switch 18 is connected.
  • a gate terminal of the transistor is connected to the connection line between the resistor 20 and the photodiode 19.
  • the switch 18 is disposed between ground and the signal line 16.
  • the supply voltage is applied in the reverse direction to the cathode of the photodiode 19.
  • the photocells work in Geiger mode, ie the supply voltage is a DC voltage, which is slightly higher than the breakdown voltage of the photodiode. If a photon hits the photodiode, an avalanche current is generated in the photodiode, which is only interrupted by a lowering of the bias voltage at the photodiode. The lowering of the bias voltage upon the arrival of a photon is achieved automatically by the resistor 20. The avalanche breakthrough process is very fast.
  • the control terminal 23 of the switch 18 is high-impedance and detects the falling between the Pho ⁇ todiode and the resistor bias and outputs a corresponding signal to the signal line 16.
  • the signal line 16 is conducted via the via 3 to the module 4, which detects and evaluates the incidence of a photon in the photocell as a function of the voltage signal on the signal line 16.
  • ground terminals for the switches 18 and for the Masselei ⁇ device 22 and the power supply for the supply line 21 are not shown in the figures shown.
  • plated-through holes 3 are used.
  • FIGS. 5 to 13 show various method sections for a method for producing an arrangement having a substrate 1 with photocells 17 and a module 4 according to FIG. 1.
  • FIG. 5 shows a substrate 1 with an active layer 2 with a multiplicity of photocells, switches, control lines 16 and the further lines with connections according to FIG.
  • an opening 30 is introduced, so that an upper side of the substrate 1 is exposed ⁇ .
  • About the opening 30 is in the upper side of a first hole 31, for example using an etching process, is introduced ⁇ .
  • the first hole 30 has a circular cross section with a first diameter and extends into the substrate 1 up to a predetermined depth perpendicular to the substrate surface.
  • FIG. 6 shows the substrate with the first hole 31. Subsequently, from the underside of the substrate 1 a second hole 32 introduced into the substrate 1, preferably etched.
  • the second hole 32 has a circular cross section with a second diameter, is arranged concentrically to the first hole 31 and led to the first hole 31 led.
  • the second diameter of the second hole 32 is larger than the first diameter of the first hole 31.
  • Figure 7 shows the substrate 1 with the second hole 32.
  • This Ver ⁇ drive stand is shown in FIG. 8
  • is brought to the top of the substrate 1 at ⁇ adjacent to the first hole 31 has a first contact surface 6 up.
  • the first contact surface 6 consists of a elekt ⁇ driven conductive material. This process status is shown in FIG.
  • a second contact surface 7 adjacent to the opening of the second hole 32 is applied to the underside of the substrate 1.
  • further conductor tracks 34 are applied to the underside, which are required for the subsequent electrical connection of the module 4 and the contacts 5. This process status is shown in FIG.
  • the block 4 is fixed to the underside of the substrate 1, wherein the connec ⁇ se of the block with associated terminals, that is electrically conductively connected to the further conductor track 34 and / or the second contact surface 7 of the substrate. 1
  • the more Lei ⁇ terbahn 34 is partially covered with a further insulating layer 36th
  • the block can ⁇ example, be attached to the underside of the substrate 1 by means of an electrically conductive polymer with the aid of a flip-chip bonding technique. This process status is shown in FIG. 11.
  • the holes 31, 32 are filled with an electrically conductive material 35.
  • a liquid material is filled in the holes 31, 32 and then cooled.
  • the cooled Materi ⁇ al represents an electrically conductive via 3.
  • solder material for example, SuAg can be used as the electrically conductive material.
  • the first and second contact surfaces 6, 7 are brought into contact with the electrically conductive material 35.
  • contacts 5 are applied to the underside of the substrate 1 and electrically conductively connected to the other conductor 34.
  • contacts 5 solder balls for example, can be used.
  • Figure 13 now shows an arrangement according to figure 1.
  • the substrate 1 is ⁇ example, a silicon substrate is used.
  • the substrate 1 can be used as a carrier for the attached module 4.
  • the substrate 1 may be fixed with egg ⁇ nem further substrate in the attachment of the contacts. 5
  • the substrate 1 may, for example, a thickness of 250 ym have ⁇ . This results in a short line length for the via 3 and thus a low line capacitance of, for example,> 5 pF. Thus, a fast temporal ⁇ ches response of the block 4 as an evaluation circuit for the photocells is possible. Furthermore, a symmetrical routing of the digital lines, ie the signal lines 16, a large uniformity of the signal regardless of the location of the Photozel ⁇ le achieved. In addition, the described arrangement allows the construction of a photodetector in 3D integration.
  • FIG. 14 shows a schematic representation of an electrical equivalent circuit diagram for the use of the photodiodes for detecting a digital time signal and an analog energy signal.
  • the signal line is passed to a ⁇ ers th input of the block 4 16, wherein the first input is connected to a discriminator 41 and a TDC circuit 42 and in this way detects a digital time signal for the impact of the photons and outputs via a first output 43.
  • the ground line 22 is connected to a second input 44 of the module 4, which determines an energy signal via an amplifier 45, a shaping circuit 46, an integrator circuit 47 and an ADC circuit 48 and outputs it via a second output 49.
  • the module may also have other and / or further evaluation circuits.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photometry And Measurement Of Optical Pulse Characteristics (AREA)

Abstract

L'invention concerne un ensemble comprenant : un substrat qui comporte sur une face au moins une photocellule ; au moins une ligne électrique reliée à la photocellule ; une connexion transversale électroconductrice entre la face supérieure et une face inférieure du substrat, laquelle connexion transversale est reliée à la ligne électrique ; un module comprenant au moins un circuit électrique, ledit module étant fixé sur la face inférieure du substrat et un raccord du module étant relié électriquement à la connexion transversale.
PCT/EP2012/065979 2011-08-17 2012-08-16 Ensemble de photocellules Ceased WO2013024128A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102011081100.1 2011-08-17
DE102011081100A DE102011081100A1 (de) 2011-08-17 2011-08-17 Anordnung mit Photozellen

Publications (1)

Publication Number Publication Date
WO2013024128A1 true WO2013024128A1 (fr) 2013-02-21

Family

ID=46727197

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2012/065979 Ceased WO2013024128A1 (fr) 2011-08-17 2012-08-16 Ensemble de photocellules

Country Status (2)

Country Link
DE (1) DE102011081100A1 (fr)
WO (1) WO2013024128A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016114204B4 (de) * 2016-08-01 2018-12-20 Ketek Gmbh Strahlungsdetektor und Verfahren zur Herstellung einer Mehrzahl von Strahlungsdetektoren

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030134509A1 (en) * 2002-01-11 2003-07-17 Yoshihide Iwazaki Manufacturing method of semiconductor device
EP1492168A1 (fr) * 2002-03-08 2004-12-29 Hamamatsu Photonics K.K. Detecteur
US20050233581A1 (en) * 2004-03-31 2005-10-20 Nec Electronics Corporation Method for manufacturing semiconductor device
WO2006111883A2 (fr) 2005-04-22 2006-10-26 Koninklijke Philips Electronics, N.V. Photomultiplicateur numerique au silicium pour tof-pet
WO2007105478A1 (fr) * 2006-02-27 2007-09-20 Mitsumasa Koyanagi Dispositif semiconducteur de type en couches dote d'un capteur integre
JP2008235478A (ja) * 2007-03-19 2008-10-02 Nikon Corp 撮像素子
US20100200940A1 (en) * 2007-06-04 2010-08-12 Fan Ji Photodetector for Imaging System

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4012743B2 (ja) * 2002-02-12 2007-11-21 浜松ホトニクス株式会社 光検出装置
JP2008277511A (ja) * 2007-04-27 2008-11-13 Fujifilm Corp 撮像素子及び撮像装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030134509A1 (en) * 2002-01-11 2003-07-17 Yoshihide Iwazaki Manufacturing method of semiconductor device
EP1492168A1 (fr) * 2002-03-08 2004-12-29 Hamamatsu Photonics K.K. Detecteur
US20050233581A1 (en) * 2004-03-31 2005-10-20 Nec Electronics Corporation Method for manufacturing semiconductor device
WO2006111883A2 (fr) 2005-04-22 2006-10-26 Koninklijke Philips Electronics, N.V. Photomultiplicateur numerique au silicium pour tof-pet
WO2007105478A1 (fr) * 2006-02-27 2007-09-20 Mitsumasa Koyanagi Dispositif semiconducteur de type en couches dote d'un capteur integre
JP2008235478A (ja) * 2007-03-19 2008-10-02 Nikon Corp 撮像素子
US20100200940A1 (en) * 2007-06-04 2010-08-12 Fan Ji Photodetector for Imaging System

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