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WO2013021786A1 - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
WO2013021786A1
WO2013021786A1 PCT/JP2012/068059 JP2012068059W WO2013021786A1 WO 2013021786 A1 WO2013021786 A1 WO 2013021786A1 JP 2012068059 W JP2012068059 W JP 2012068059W WO 2013021786 A1 WO2013021786 A1 WO 2013021786A1
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WIPO (PCT)
Prior art keywords
thin film
sic substrate
semiconductor device
thickness
nanoparticle
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PCT/JP2012/068059
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French (fr)
Japanese (ja)
Inventor
博明 岡部
洋介 中西
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2013527943A priority Critical patent/JP5734435B2/en
Publication of WO2013021786A1 publication Critical patent/WO2013021786A1/en
Anticipated expiration legal-status Critical
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/60Schottky-barrier diodes 
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048Making electrodes
    • H01L21/0485Ohmic electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325Silicon carbide

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a silicon carbide (SiC) semiconductor.
  • SiC silicon carbide
  • SiC silicon carbide
  • the on-resistance of the semiconductor device is determined by the sum of resistance values of paths through which current flows.
  • the on-resistance of the semiconductor device includes a resistance generated by an ohmic electrode that plays a role of connecting the semiconductor and various wirings. Therefore, it is required to form an ohmic electrode having a sufficiently low resistance compared to the resistance of the silicon carbide substrate and the drift layer.
  • an ohmic electrode on SiC there is a method of depositing a metal thin film to be an ohmic electrode on a SiC substrate and irradiating the deposited metal thin film with laser light (see, for example, Patent Documents 1 to 3).
  • a metal thin film is deposited on a SiC substrate and the deposited metal thin film is irradiated with laser light, the metal thin film absorbs the energy of the laser light, and the absorbed energy is changed to heat. With this heat, the metal thin film and SiC are alloyed. Thereby, since the contact between the metal thin film and SiC becomes an ohmic contact, a low-resistance ohmic electrode can be obtained.
  • a second conductivity type impurity doped layer is formed on a first conductivity type silicon carbide substrate, a metal thin film is provided on the formed impurity doped layer, and a metal An ohmic electrode is formed by irradiating laser light from the upper surface of the thin film.
  • a back surface of a semiconductor substrate made of single crystal silicon carbide is polished to form irregularities on the back surface, and then a metal thin film is formed on the back surface of the semiconductor substrate.
  • the ohmic electrode is formed by irradiating the metal thin film with laser light.
  • an ohmic electrode is formed by irradiating a metal thin film with laser light as disclosed in Patent Documents 1 to 3
  • the laser light having an energy density necessary for obtaining a low resistance ohmic electrode is applied on the metal thin film. It is necessary to scan with. Accordingly, the process of irradiating the metal thin film with the laser beam to form the ohmic electrode is performed by a single wafer process in which the substrates are processed one by one. As the substrate becomes larger and the area to be irradiated with laser light becomes larger, the problem of processing time becomes more prominent.
  • the energy density of the laser beam necessary for obtaining a low-resistance ohmic electrode it is conceivable to reduce the energy density of the laser beam necessary for obtaining a low-resistance ohmic electrode. If the energy density of the laser beam necessary for obtaining a low-resistance ohmic electrode can be reduced, the beam diameter of the laser beam can be increased accordingly, so that the processing time by the laser beam irradiation apparatus can be shortened. Can do.
  • Laser light that contributes to the formation of the ohmic electrode is a component of the irradiated laser light that penetrates into the metal thin film and is absorbed and converted into thermal energy.
  • the component of the laser beam reflected on the surface of the metal surface does not contribute to the formation of the ohmic electrode, and is wasted energy.
  • the extent to which the laser beam is reflected on the surface of the metal thin film depends on the reflectance of the metal thin film with respect to the laser beam.
  • the reflectance of the metal thin film with respect to the laser beam is relatively large, and the energy of the reflected laser beam is relatively large among the energy of the irradiated laser beam.
  • an ohmic electrode having a low resistance can be efficiently formed by irradiation with laser light having a relatively low energy density.
  • the energy density of the laser light necessary for forming the low-resistance ohmic electrode can be reduced, so that the laser light beam diameter is increased and the processing time by the laser light irradiation apparatus is shortened accordingly. Can do.
  • the reflectance of the laser beam varies depending on the shape of the surface of the metal thin film. If the surface of the metal thin film has irregularities, the reflectance of the laser beam decreases. For example, as in the technique disclosed in Patent Document 2 described above, when irregularities are formed on the back surface of the semiconductor substrate, irregularities are formed on the surface of the metal thin film, so that it is possible to reduce the reflectance of the laser beam. is there.
  • a strained layer (hereinafter sometimes referred to as “worked strained layer”) is formed on the silicon carbide substrate.
  • the substrate is warped.
  • a grindstone with coarse abrasive grains must be used.
  • the coarser the abrasive grains the deeper the processing strain layer is formed on the silicon carbide substrate, and the greater the warpage of the substrate.
  • the warpage generated in the substrate causes an error in chucking the substrate and cracking the substrate in the subsequent process, hindering smooth substrate conveyance and hindering automation of the semiconductor manufacturing system.
  • the processed strain layer may adversely affect the reliability of the device.
  • the surface of the silicon carbide substrate is processed with ion plasma or the like so that (100% ⁇ reflectance ⁇ transmittance) is 80% or more at the wavelength of the laser beam.
  • a metal thin film is deposited and irradiated with laser light.
  • the laser beam is absorbed only by the metal thin film. Therefore, in the technique disclosed in Patent Document 3, the laser beam necessary for forming a low-resistance ohmic electrode is used. The effect of reducing the energy density cannot be obtained.
  • the metal thin film is nickel, the penetration depth of light having a wavelength of 100 nm to 1500 nm is about 10 nm to 20 nm.
  • An object of the present invention is to provide a semiconductor device manufacturing method capable of forming a low-resistance ohmic electrode by irradiating laser light with as low energy density as possible without impairing reliability.
  • the method for manufacturing a semiconductor device of the present invention includes a nano thin film forming step of forming a nano particle thin film, which is a metal thin film, with metal nanoparticles on one surface in the thickness direction of a silicon carbide substrate, and the nano thin film forming step. And an electrode forming step of forming an ohmic electrode by irradiating the nanoparticle thin film with a laser beam.
  • a nano particle thin film that is a metal thin film is formed on one surface in the thickness direction of the silicon carbide substrate by the metal nanoparticles.
  • An ohmic electrode is formed by irradiating the nanoparticle thin film formed in the nano thin film forming process with laser light in the electrode forming process.
  • the energy density of the laser light necessary to form a low-resistance ohmic electrode Can be reduced. Further, since the silicon carbide substrate is not polished, it is possible to prevent the generation of a processing strain layer, to prevent the silicon carbide substrate from being warped, and to prevent the reliability of the semiconductor device from being impaired. Therefore, a low resistance ohmic electrode can be formed by irradiating laser light with as low energy density as possible without impairing the reliability of the semiconductor device.
  • FIG. 5 is a cross-sectional view showing a state at a stage where formation of a silicide layer 17 is completed. It is a flowchart which shows the procedure of the back surface process in the manufacturing method of the semiconductor device of the 2nd Embodiment of this invention.
  • FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device 100 according to the first embodiment of the present invention.
  • the semiconductor device 100 is manufactured by the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • Semiconductor device 100 includes a silicon carbide semiconductor element (hereinafter sometimes simply referred to as “semiconductor element”) 1.
  • the semiconductor element 1 is a Schottky Barrier Diode (abbreviation: SBD) using silicon carbide (SiC).
  • SBD Schottky Barrier Diode
  • SiC silicon carbide
  • the semiconductor element 1 includes a silicon carbide (SiC) substrate 11, a silicon carbide (SiC) epitaxial layer 12, an ion implantation region 13, a junction termination extension (JTE) region 14, a Schottky electrode 15, a wiring electrode 16, and A silicide layer 17 is provided. Ion implantation region 13 is formed in SiC epitaxial layer 12.
  • the SiC substrate 11 has n-type conductivity.
  • SiC substrate 11 has a 4H type polytype in which the surface orientation on one side in the thickness direction is off by 4 ° or 8 ° from the ⁇ 0001> silicon surface, that is, inclined by 4 ° or 8 °. It is an n-type low resistance substrate.
  • the SiC epitaxial layer 12 which is a drift layer is provided on the surface of one side in the thickness direction of the SiC substrate 11.
  • the surface on one side in the thickness direction of the SiC substrate may be simply referred to as “the surface of the SiC substrate”.
  • SiC epitaxial layer 12 contains n-type impurities and has n-type conductivity.
  • the n-type impurity concentration in SiC epitaxial layer 12 varies depending on the assumed breakdown voltage, but is, for example, 5 ⁇ 10 15 cm ⁇ 3 to 5 ⁇ 10 16 cm ⁇ 3 .
  • the thickness of SiC epitaxial layer 12 (hereinafter sometimes referred to as “film thickness”) varies depending on the assumed breakdown voltage, but is, for example, 5 ⁇ m to 15 ⁇ m.
  • the SiC substrate 11 and the SiC epitaxial layer 12 may be collectively referred to as “SiC substrate 10”.
  • the ion implantation region 13 is formed in the vicinity of the surface on one side in the thickness direction of the SiC epitaxial layer 12.
  • the “surface vicinity portion” includes the surface and a portion in the vicinity thereof.
  • the ion implantation region 13 is formed in an annular shape, more specifically in a substantially rectangular shape, as viewed from one side in the thickness direction.
  • the ion implantation region 13 is a p-type activation region and contains a p-type impurity.
  • Ion implantation region 13 contains, for example, aluminum (Al) as a p-type impurity.
  • the ion implantation region 13 is formed by ion implantation of p-type impurity ions such as Al ions.
  • the implantation amount of p-type impurity ions such as Al ions in the ion implantation region 13 is, for example, 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 .
  • the JTE region 14 is formed in the vicinity of the surface on one side in the thickness direction of the SiC epitaxial layer 12.
  • the JTE region 14 is formed adjacent to the ion implantation region 13 when viewed from one side in the thickness direction.
  • the JTE region 14 is formed in an annular shape, more specifically in a substantially rectangular shape, when viewed from one side in the thickness direction. More specifically, the JTE region 14 is formed so as to surround the ion implantation region 13 when viewed from one side in the thickness direction.
  • the JTE region 14 is provided to increase the breakdown voltage. By providing the JTE region 14 at a portion outside the ion implantation region 13 that is the peripheral portion of the semiconductor element 1, the electric field strength on the surface on one side in the thickness direction of the SiC epitaxial layer 12 can be reduced.
  • the ion implantation region 13 and the JTE region 14 constitute a p-type termination structure.
  • a region surrounded by the ion implantation region 13 in the vicinity of the surface on one side in the thickness direction of the SiC epitaxial layer 12 is referred to as a Schottky region 18.
  • the Schottky electrode 15 is provided on the surface on one side in the thickness direction of the SiC epitaxial layer 12, more specifically, on the surface of the Schottky region 18 and on a part of the surface of the ion implantation region 13.
  • Examples of the material of the Schottky electrode 15 include titanium (Ti), tungsten (W), molybdenum (Mo), and chromium (Cr).
  • the Schottky electrode 15 is formed of one or more selected from these materials.
  • the wiring electrode 16 is provided on the surface of one side in the thickness direction of the Schottky electrode 15. Examples of the material of the wiring electrode 16 include Al.
  • the silicide layer 17 is provided on the surface opposite to the surface on one side in the thickness direction of the SiC substrate 11, that is, on the surface on the other side in the thickness direction of the SiC substrate 11.
  • the surface on the other side in the thickness direction of SiC substrate 11 corresponds to one surface in the thickness direction of the SiC substrate on which the metal thin film is formed.
  • the surface on the other side in the thickness direction of the SiC substrate may be referred to as “the back surface of the SiC substrate”.
  • the silicide layer 17 is a reaction between the contact electrode film and SiC, and is in ohmic contact with the SiC substrate 11.
  • Examples of the material for the contact electrode film include nickel (Ni), titanium (Ti), cobalt (Co), molybdenum (Mo), and tungsten (W).
  • a contact electrode film is formed of one or more selected from these materials.
  • an ohmic electrode formed on the surface of the other side in the thickness direction of the SiC substrate 11 in the semiconductor element 1 which is an SBD will be described as an example.
  • the SBD has been described as an example of the semiconductor element 1.
  • the semiconductor element 1 is not limited thereto, and the semiconductor element 1 is a metal-oxide-semiconductor field-effect transistor (Metal Oxide Semiconductor Field Effect Transistor; abbreviation: MOSFET). It may be.
  • the method for manufacturing a semiconductor device 100 including the SiC Schottky barrier diode that is the semiconductor element 1 shown in FIG. 1 includes a preparation process, a front surface processing process, and a back surface processing process.
  • materials and devices necessary for manufacturing the semiconductor device 100 such as the SiC substrate 11 are prepared.
  • SiC substrate 11 SiC substrate 11 having n-type conductivity, specifically, the surface orientation of the surface on one side in the thickness direction is off by 4 ° or 8 ° from the ⁇ 0001> silicon surface.
  • a 4H type polytype n-type low resistance SiC substrate 11 is prepared.
  • the SiC epitaxial layer 12 is grown on the surface of one side in the thickness direction of the SiC substrate 11. Thereby, the SiC substrate 10 is obtained.
  • the SiC epitaxial layer 12 is formed so that the doping concentration of the n-type impurity is 5 ⁇ 10 15 cm ⁇ 3 to 5 ⁇ 10 16 cm ⁇ 3 .
  • the SiC epitaxial layer 12 is formed so as to have a film thickness of 5 ⁇ m to 15 ⁇ m.
  • an oxide film is formed on the surface on one side in the thickness direction of the SiC epitaxial layer 12 by sacrificial oxidation.
  • a process for forming a p-type termination structure is performed. Specifically, first, a mask for ion implantation (hereinafter referred to as “ion implantation mask”) is formed on the oxide film formed on the surface of one side in the thickness direction of SiC epitaxial layer 12. A p-type impurity, for example, aluminum is ion-implanted from one side in the thickness direction of the ion implantation mask to selectively ion-implant the p-type impurity into a predetermined region of the SiC epitaxial layer 12 to form an ion implantation region 13. To do.
  • ion implantation mask a mask for ion implantation
  • the ion implantation region 13 has, for example, an implantation amount of 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 and an implantation depth of 0.5 ⁇ m to 1.0 ⁇ m at room temperature, for example, 25 ° C. It is formed by implanting p-type impurity ions such as aluminum ions at an energy of 40 keV to 700 keV with an implantation angle of 0 °.
  • a JTE mask for forming the JTE region 14 is formed on the oxide film.
  • a p-type impurity, for example, aluminum is ion-implanted from one side in the thickness direction of the JTE mask to selectively ion-implant the p-type impurity into a predetermined region of the SiC epitaxial layer 12, thereby forming the JTE region 14.
  • the JTE region 14 has, for example, an implantation amount of 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 and an implantation depth of 0.5 ⁇ m to 1.0 ⁇ m. Further, it is formed by implanting p-type impurity ions such as aluminum ions at an energy of 40 keV to 700 keV at a room temperature of 25 ° C. and an implantation angle of 0 °.
  • heat treatment is performed in order to activate p-type impurity ions such as implanted aluminum ions. Specifically, heat treatment is performed in an argon atmosphere at a temperature of 1500 ° C. to 2000 ° C. for 1 minute to 30 minutes. By this heat treatment step, the implanted ions are activated and a p-type termination structure is formed.
  • the Schottky electrode 15 is formed in the Schottky region 18 surrounded by the ion implantation region 13 so that the peripheral portion protrudes from the ion implantation region 13.
  • Examples of the material of the Schottky electrode 15 include titanium (Ti), tungsten (W), molybdenum (Mo), and chromium (Cr).
  • the Schottky electrode 15 is formed of one or more selected from these materials.
  • the wiring electrode 16 is formed on the surface on one side in the thickness direction of the Schottky electrode 15. Examples of the material of the wiring electrode 16 include Al.
  • the device portion is indicated as “device portion 20” with reference numeral “20”.
  • the back surface processing step is a silicide layer forming step.
  • a silicide layer 17 that is an ohmic electrode is formed on the back surface of the SiC substrate 11, that is, the surface on the other side in the thickness direction of the SiC substrate 11.
  • the silicide layer forming step is performed as follows.
  • FIG. 2 is a flowchart showing a procedure of a silicide layer forming step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • the silicide layer forming step includes a nano thin film forming step in step a1 and an electrode forming step in step a2.
  • the processing of the flowchart shown in FIG. 2 is started, and the process proceeds to the nano thin film forming step of step a1.
  • the nano thin film forming step includes a coating step of step a11 and a sintering step of step a12.
  • 3 to 5 are diagrams for explaining the silicide layer forming step. 3 to 5, the SiC epitaxial layer 12, the Schottky electrode 15, and the wiring electrode 16 including the ion implantation region 13 and the JTE region 14 shown in FIG.
  • FIG. 3 is a cross-sectional view showing a state in which the nanoparticle thin film 22 has been formed.
  • the nano particle thin film 22 is formed as shown in FIG. Specifically, first, in the coating step of step a11, a solvent containing metal nanoparticles 21 (hereinafter referred to as “nanoparticle coating liquid”) is formed on the surface on the other side in the thickness direction, which is one surface in the thickness direction of the SiC substrate 11. Apply).
  • the nanoparticle coating liquid is applied by spin coating, for example.
  • nickel nanoparticles are used as the metal nanoparticles 21.
  • the metal nanoparticles 21 have a particle size of 1 nm to 100 nm.
  • the applied nanoparticle coating solution is heat-treated at a temperature of about 100 ° C. to 300 ° C. to sinter the metal nanoparticles 21 in the nanoparticle coating solution. That is, the coated metal nanoparticles 21 are sintered by heat treatment with a solvent at a temperature of about 100 ° C. to 300 ° C.
  • a nanoparticle thin film 22 that is a metal thin film made of the metal nanoparticles 21 is formed.
  • the nanoparticle thin film 22 is a contact electrode film serving as a contact electrode.
  • the film thickness of the nanoparticle thin film 22 after sintering is 10 nm or more and 500 nm or less.
  • the nanoparticle thin film 22 which is a metal thin film, is formed from the metal nanoparticles 21.
  • the reflectance of a metal thin film can be made low compared with the case where a metal thin film is formed by other methods, such as vapor deposition, for example.
  • FIG. 4 is a cross-sectional view showing a state in which the nanoparticle thin film 22 is irradiated with laser light.
  • FIG. 5 is a cross-sectional view showing a state in which the formation of the silicide layer 17 has been completed.
  • the electrode formation step of step a2 in FIG. 2 is performed.
  • the electrode forming step first, as shown in FIG. 4, the nanoparticle thin film 22 is irradiated with a laser beam at an energy density necessary for forming an ohmic contact, whereby an annealing process using a laser beam (hereinafter referred to as “laser annealing process”).
  • laser annealing process an annealing process using a laser beam
  • the laser beam applied to the nanoparticle thin film 22 only needs to have a wavelength that is absorbed by the nanoparticle thin film 22.
  • the nanoparticle thin film 22 is a Ni thin film made of nickel (Ni) nanoparticles as in the present embodiment, for example, any one or two of the following (A) to (G) are used as the laser light: More than seeds can be used.
  • A Laser light whose wavelength of the YAG laser element is 1064 nm.
  • B Laser light from a YLF laser element.
  • C Of the laser light from the YVO 4 laser element, (a) a fundamental wave with a wavelength of 1064 nm, (b) a second harmonic with a wavelength of 532 nm, (c) a third harmonic with a wavelength of 355 nm, (d ) Quadruple wave with a wavelength of 266 nm.
  • D Laser light whose wavelength of the ArF excimer laser element is 193 nm.
  • E A laser beam having a wavelength of 248 nm of a KrF excimer laser element.
  • F A laser beam having a XeCl excimer laser element with a wavelength of 308 nm.
  • G A laser beam whose wavelength of the XeF excimer laser element is 351 nm.
  • laser light of various semiconductor laser elements other than the above (A) to (G) can be used.
  • these laser beams it is desirable to use a laser beam having a wavelength of 400 nm or less. The reason for this will be described below.
  • the nanoparticle thin film 22 has a film defect such as a pinhole 42 shown in FIG. 9 to be described later, or a process error that causes the nanoparticle thin film 22 to be thinner than a desired film thickness occurs.
  • the irradiated laser light is not absorbed by the nanoparticle thin film 22 and enters the SiC substrate 11.
  • the wavelength of the irradiated laser light is a wavelength that is not absorbed by silicon carbide constituting the SiC substrate 11, the irradiated laser light passes through the SiC substrate 11.
  • the laser beam that has passed through the SiC substrate 11 reaches the non-irradiated surface of the SiC substrate 11 that is not irradiated with the laser beam, specifically, the surface on one side in the thickness direction of the SiC substrate 11.
  • the laser light reaching the laser light non-irradiated surface is absorbed by the Schottky electrode 15 and the wiring electrode 16 formed on the laser light non-irradiated surface.
  • the device unit 20 is destroyed.
  • the device unit 20 in which Ti, Al, and the like are arranged, and the device unit 20 is heated to a high temperature. It may become.
  • the device unit 20 becomes high temperature, melting of Al, deterioration of the Schottky interface, and the like occur.
  • the laser beam In order to prevent heat conduction to the device unit 20, it is effective to irradiate the laser beam with a pulse as short as about 1 ns to 1000 ns, for example, with a repetition frequency as low as about 1 kHz to 1000 kHz. Specifically, it is preferable to scan and irradiate pulsed laser light having a pulse width of 1 ns to 1000 ns and a repetition frequency of 1 kHz to 1000 kHz.
  • Ni nickel
  • the laser beam irradiation in the laser annealing treatment is preferably performed in an inert gas atmosphere such as argon or nitrogen in order to prevent oxidation of the nanoparticle thin film 22 serving as an electrode.
  • the silicide layer 17 is formed as a reaction layer of metal and SiC constituting the nanoparticle thin film 22, in this embodiment as a reaction layer of Ni and SiC.
  • a low-resistance ohmic contact is obtained between the ohmic electrode formed of the silicide layer 17 as the reaction layer and the SiC substrate 11 as the SiC layer.
  • the process of irradiating a laser beam and forming an ohmic electrode is equivalent to an electrode formation process.
  • nanoparticle thin film 22 that is a metal thin film is formed by metal nanoparticles 21 on the surface of the other side in the thickness direction of SiC substrate 11 in the nanothin film formation step.
  • An ohmic electrode is formed by irradiating the nanoparticle thin film 22 which is a metal thin film formed in the nano thin film forming process with laser light in the electrode forming process.
  • the metal nanoparticles 21 can control the particle size. By controlling the particle size of the metal nanoparticles 21, irregularities can be formed in the nanoparticle thin film 22 which is a metal thin film, and thus the reflectance of the metal thin film can be reduced. Further, by forming a metal thin film with the metal nanoparticles 21, surface plasmons can be excited resonantly. In such a situation where surface plasmons can be excited, the energy of the irradiated laser light is deprived by the excitation of the surface plasmons, so that the reflectance of the metal thin film is lowered. Therefore, the reflectance of a metal thin film can be reduced by forming the nanoparticle thin film 22 as a metal thin film with the metal nanoparticles 21 as described above.
  • the reflectance of the metal thin film can be reduced without polishing the SiC substrate 11. Since the nanoparticle thin film 22, which is a metal thin film having a reduced reflectance in this way, is irradiated with laser light in the electrode forming step, the laser light enters the metal thin film and is absorbed and absorbed. The rate of change to energy can be increased. As a result, the energy density of laser light necessary for forming a low-resistance ohmic electrode can be reduced.
  • the energy density of the laser light necessary for the formation of the low-resistance ohmic electrode can be increased by sputtering, vapor deposition, or the like. It can reduce compared with the case where a metal thin film is formed by other methods. Thereby, the processing time required for laser beam irradiation can be shortened.
  • the ohmic electrode formed by the method of this embodiment does not have a processing strain layer at the interface with the SiC substrate 11, and the SiC substrate 11 warpage does not increase.
  • the warp of the SiC substrate 11 is 100 ⁇ (200 / T) Can be 2 ⁇ m or less.
  • the warp of the SiC substrate 11 can be reduced to 250 ⁇ (200 / t) 2 ⁇ m or less.
  • a low-resistance ohmic electrode can be formed by irradiating laser light with as low energy density as possible without impairing the reliability of the semiconductor device 100.
  • nickel (Ni) is used as the material of the metal nanoparticles 21 constituting the nanoparticle thin film 22.
  • the present invention is not limited to this, and titanium (Ti), cobalt (Co). Molybdenum (Mo), tungsten (W), or the like may be used. Even if these materials are used, the same effect as the case of using Ni can be obtained.
  • the material of the metal nanoparticles 21 preferably contains one or more selected from nickel (Ni), titanium (Ti), cobalt (Co), molybdenum (Mo), and tungsten (W).
  • the silicide layer 17 can be formed as an ohmic electrode having a lower resistance than in the case of using another material.
  • the metal nanoparticles 21 have a particle size of 1 nm to 100 nm.
  • the particle diameter of the metal nanoparticle 21 is not limited to this, it is preferable that it is 1 nm or more and 100 nm or less like this Embodiment. If the particle size of the metal nanoparticles 21 is less than 1 nm, the unevenness formed on the nanoparticle thin film 22 that is a metal thin film is small, and thus the effect of reducing the reflectance of the metal thin film may not be sufficiently obtained.
  • the particle size of the metal nanoparticles 21 is preferably 1 nm or more and 100 nm or less.
  • the particle diameter of the metal nanoparticles 21 is particularly preferably ⁇ / 4n, where ⁇ is the wavelength of the laser beam to be irradiated and n is the refractive index of the metal nanoparticles 21 at the wavelength ⁇ .
  • the refractive index n of Ni with respect to the wavelength 355 nm of the laser light is 1.63.
  • the film thickness of the nanoparticle thin film 22, specifically, the film thickness of the nanoparticle thin film 22 after sintering of the applied metal nanoparticles 21 is 10 nm or more and 500 nm or less in the present embodiment.
  • the film thickness of the nanoparticle thin film 22 is not limited to this, it is preferable that it is 10 nm or more and 500 nm or less like this Embodiment.
  • the film thickness of the nanoparticle thin film 22 is less than 10 nm, the silicide layer 17 obtained after the laser light irradiation is difficult to be uniform, and a uniform ohmic electrode may not be obtained. If the film thickness of the nanoparticle thin film 22 exceeds 500 nm, the irradiated laser light may not reach the interface between the nanoparticle thin film 22 and the SiC substrate 11. If the irradiated laser light cannot reach the interface between the nanoparticle thin film 22 and the SiC substrate 11, the reaction between the metal constituting the nanoparticle thin film 22 and SiC constituting the SiC substrate 11 does not proceed, and the silicide layer 17 may not be formed, and a low-resistance ohmic electrode may not be obtained. Therefore, the film thickness of the nanoparticle thin film 22 is preferably 10 nm or more and 500 nm or less.
  • the nanoparticle thin film 22 is formed by applying a solvent containing the metal nanoparticles 21 on the surface of the other side in the thickness direction of the SiC substrate 11 at the application stage of step a11 in FIG. It is formed by sintering the nanoparticles 21 in the sintering step. By doing in this way, the nanoparticle thin film 22 which is a metal thin film by the metal nanoparticle 21 can be formed easily.
  • the carrier passes through the SiC substrate 11 and travels in the vertical direction toward the paper surface of FIG. 1, specifically, in the thickness direction of the SiC substrate 11. Therefore, the resistance of the semiconductor element 1 can be reduced by reducing the thickness of the SiC substrate 11 serving as a current path.
  • the semiconductor element 1 is a SiC Schottky barrier diode (SBD).
  • the manufacturing method of the semiconductor device of the present embodiment is the same as that of the first embodiment until the back surface processing step. Specifically, first, in the preparation step, materials and devices necessary for manufacturing the semiconductor device 100 such as the SiC substrate 11 are prepared. As the SiC substrate 11, an n-type SiC substrate 11 is prepared. When materials and apparatuses necessary for manufacturing the semiconductor device 100 such as the SiC substrate 11 are prepared, the process proceeds to a surface processing step.
  • the SiC epitaxial layer 12 is grown on the surface of the SiC substrate 11.
  • the doping concentration of the n-type impurity in SiC epitaxial layer 12 is, for example, 5 ⁇ 10 15 cm ⁇ 3 to 5 ⁇ 10 16 cm ⁇ 3 .
  • the film thickness of SiC epitaxial layer 12 is, for example, 5 ⁇ m to 15 ⁇ m.
  • An oxide film is formed on the surface of one side in the thickness direction of SiC epitaxial layer 12 by sacrificial oxidation.
  • a process for forming a p-type termination structure is performed. Specifically, first, an ion implantation mask is formed on the oxide film formed on the surface on one side in the thickness direction of SiC epitaxial layer 12. A p-type impurity, for example, aluminum is ion-implanted from one side in the thickness direction of the ion implantation mask to selectively ion-implant the p-type impurity into a predetermined region of the SiC epitaxial layer 12 to form an ion implantation region 13. To do.
  • the ion implantation region 13 has, for example, an implantation amount of 1 ⁇ 10 16 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 and an implantation depth of 0.5 ⁇ m to 1.0 ⁇ m at room temperature, for example, 25 ° C. It is formed by implanting p-type impurity ions such as aluminum ions at an energy of 40 keV to 700 keV with an implantation angle of 0 °.
  • the ion implantation mask is removed, the JTE region 14 is formed in the same manner as in the first embodiment, and the JTE mask and the oxide film used for forming the JTE region 14 are removed. Thereafter, in order to activate p-type impurity ions such as implanted aluminum ions, heat treatment is performed at a temperature of 1500 ° C. to 2000 ° C. for 1 minute to 30 minutes, for example, in an argon atmosphere. By this heat treatment step, the implanted ions are activated and a p-type termination structure is formed.
  • p-type impurity ions such as implanted aluminum ions
  • the Schottky electrode 15 is formed in the Schottky region 18 surrounded by the ion implantation region 13 so that the peripheral portion protrudes from the ion implantation region 13.
  • the material of the Schottky electrode 15 include titanium (Ti), tungsten (W), molybdenum (Mo), and chromium (Cr).
  • the wiring electrode 16 is formed on the surface of the Schottky electrode 15 on one side in the thickness direction. Examples of the material of the wiring electrode 16 include Al.
  • FIG. 6 is a flowchart showing the procedure of the back surface processing step in the method for manufacturing a semiconductor device according to the second embodiment of the present invention.
  • the back surface processing step includes the thinning step of step b1 before the silicide layer forming step, specifically, before the nano thin film forming step of step a1. That is, the back surface processing process includes a thinning process in step b1, a nano thin film forming process in step a1, and an electrode forming process in step a2.
  • the nano thin film forming process in step a1 and the electrode forming process in step a2 constitute a silicide layer forming process.
  • the SiC substrate 11 is thinned. Specifically, by grinding the back surface of the SiC substrate 11, that is, the surface on the other side in the thickness direction, the thickness of the SiC substrate 11 (hereinafter sometimes referred to as “plate thickness”) is reduced. For example, when manufacturing semiconductor device 100 using SiC substrate 11 having a plate thickness of 400 ⁇ m, SiC substrate 11 is thinned so that the plate thickness becomes 200 ⁇ m or less by grinding the entire back surface of SiC substrate 11. .
  • a processing strain layer is formed on the back surface of the SiC substrate 11 by grinding in the thinning process.
  • the back surface of the SiC substrate 11 has an arithmetic average roughness Ra specified in JIS B 0601 of 10 nm or less. It is preferable to grind. Specifically, the arithmetic average roughness Ra of the back surface of the SiC substrate 11 is reduced to 10 nm or less by grinding the back surface of the SiC substrate 11 with a fine grindstone of number 1000 or more having an average abrasive grain size of 20 ⁇ m or less. It is preferable to do. By grinding so that the processing surface is flattened with a fine grindstone in this way, the depth at which the processing strain layer is formed can be reduced, so that the warp of the SiC substrate 11 can be suppressed. .
  • the thinning process of step b1 is provided to reduce the thickness of the SiC substrate 11 serving as a current path. Specifically, the SiC substrate 11 is thinned so that the plate thickness is 200 ⁇ m or less. Thereby, the resistance of the semiconductor element 1 can be reduced.
  • a silicide layer 17 that is an ohmic electrode is formed on the back surface of the SiC substrate 11 in the same manner as in the first embodiment. Specifically, first, a solvent containing metal nanoparticles 21 such as nickel nanoparticles having a particle size of 1 nm to 100 nm is applied to the back surface of the SiC substrate 11, that is, the surface on the other side in the thickness direction, for example, spin coating. .
  • the coated metal nanoparticles 21 such as nickel nanoparticles are sintered by a heat treatment at a temperature of about 100 ° C. to 300 ° C. to form a nanoparticle thin film 22 made of the metal nanoparticles 21.
  • the thickness of the nanoparticle thin film 22 formed of metal nanoparticles is large, the thickness of the silicide layer 17 which is an alloy layer formed by irradiating the nanoparticle thin film 22 with a laser beam to be silicided is also thick. As a result, the stress generated in the alloy layer increases. Accordingly, when the thick nanoparticle thin film 22 is formed on the thinned SiC substrate 11, the SiC substrate 11 is greatly warped. In the worst case, the SiC substrate 11 that has been thinned and reduced in strength cannot withstand the stress and cracks.
  • the nanoparticle thin film 22 having a thickness of 300 nm is formed by nickel nanoparticles on the 3 inch SiC substrate 11 thinned to 100 ⁇ m and irradiated with laser light, the thickness of the silicide layer 17 which is an alloy layer is increased. A large stress was generated, which caused the SiC substrate 11 to crack. Since the stress of the film is proportional to the thickness thereof, the stress of the alloy layer is proportional to the thickness of the nanoparticle thin film 22 to be formed.
  • FIG. 7 is a diagram for explaining the relationship between load and stress.
  • the warping and cracking of the SiC substrate 11 will be examined.
  • a disk-shaped wafer is assumed as the SiC substrate 11 and a load P is applied to the center of the wafer.
  • Calculate the maximum stress on the wafer is obtained by the following equation (1).
  • the warpage w max of the wafer is obtained by the following equations (2) and (3).
  • t represents the thickness of the wafer
  • represents the Poisson's ratio
  • D represents the rigidity per unit area of the wafer
  • E represents the longitudinal elastic modulus
  • FIG. 8 is a graph showing the relationship between the thickness of the SiC substrate 11 and the thickness of the Ni film when a crack occurs in the SiC substrate 11.
  • the horizontal axis represents the thickness [ ⁇ m] of the SiC substrate 11
  • the vertical axis represents the thickness [nm] of the Ni film that is the nanoparticle thin film 22 formed of nickel nanoparticles.
  • the warp of the SiC substrate 11 is inversely proportional to the square of the thickness of the SiC substrate 11, and is proportional to the film stress and the thickness of the nanoparticle thin film 22.
  • the stress generated in the SiC substrate 11 is calculated from the actual warpage of the SiC substrate 11 and the thickness of the nanoparticle thin film 22.
  • the thickness of the nanoparticle thin film 22 when the SiC substrate 11 breaks is calculated for the SiC substrate 11 of each thickness, the thickness is as shown in FIG.
  • the thickness of the nanoparticle thin film 22 is y and the thickness of the SiC substrate 11 is x
  • the relationship between the thickness of the SiC substrate 11 and the thickness of the nanoparticle thin film 22 when the SiC substrate 11 is broken is expressed by the following formula ( It is represented by a curve of a quadratic function that satisfies 4).
  • y 0.0347x 2 -0.8212x + 21.286 (4)
  • the nanoparticle thin film 22 must be thinner than the value of the thickness y represented by the equation (4) with respect to the thinned SiC substrate 11. That is, the thickness y of the nanoparticle thin film 22 needs to satisfy the following formula (5) with respect to the thickness x of the SiC substrate 11. y ⁇ 0.0347x 2 ⁇ 0.8212x + 21.286 (5)
  • the thickness y of the nanoparticle thin film 22 so as to satisfy the formula (5), cracking of the SiC substrate 11 and warping of the SiC substrate 11 can be suppressed.
  • the reflectance of the surface of the nanoparticle thin film 22 which is a metal thin film irradiated with laser light can be lowered without increasing the warp of the SiC substrate 11. Therefore, also in the present embodiment, the energy density of the laser beam necessary for forming the low-resistance ohmic electrode is reduced by reducing the reflectivity of the surface of the metal thin film without increasing the warp of the SiC substrate 11. be able to.
  • the warp of the SiC substrate 11 is 100 ⁇ (200 / T) Can be 2 ⁇ m or less.
  • the warp of the SiC substrate 11 can be reduced to 250 ⁇ (200 / t) 2 ⁇ m or less.
  • the ohmic electrode is formed by irradiating the nanoparticle thin film 22 with laser light in the same manner as in the first embodiment. .
  • the thin plate forming step is provided before the nano thin film forming step to thin the SiC substrate 11 that is the current path, specifically, the plate thickness is 200 ⁇ m or less.
  • the resistance of the semiconductor element 1 is reduced by reducing the thickness.
  • the back surface of the SiC substrate 11, that is, the surface on the other side in the thickness direction is ground.
  • the metal thin film formed on the back surface of the SiC substrate 11 is formed as the nanoparticle thin film 22 by the metal nanoparticles 21, so that irregularities are formed in the metal thin film. Therefore, it is not necessary to grind the back surface of the SiC substrate 11. Therefore, when the back surface of SiC substrate 11 is ground, it can be ground so that the processing surface becomes flat with a fine grindstone as described above. As a result, the depth at which the work strain layer is formed can be reduced, so that the warp of SiC substrate 11 can be suppressed.
  • the nanoparticle thin film 22 as a metal thin film by the metal nanoparticles 21, the reflectance of the surface of the metal thin film irradiated with the laser light is formed. Can be reduced. As a result, the energy density of the laser beam required to form a low-resistance ohmic electrode can be reduced compared to the case where a metal film is formed by sputtering, vapor deposition, etc., so the processing time by laser beam irradiation is shortened. can do.
  • a low-resistance ohmic electrode can be formed by irradiating laser light with as low energy density as possible without impairing the reliability of the semiconductor device 100, and the resistance of the semiconductor element 1 Can be reduced.
  • the back surface of the SiC substrate 11 is ground so that the arithmetic average roughness Ra is 10 nm or less. If the arithmetic mean roughness Ra of the back surface of the SiC substrate 11 after grinding exceeds 10 nm, a processed strain layer may be formed from the back surface of the SiC substrate 11 to a deep position, and the SiC substrate 11 is excessively warped. There is a fear. Therefore, when grinding the back surface of SiC substrate 11, it is preferable to grind so that arithmetic mean roughness Ra is 10 nm or less as in the present embodiment.
  • the depth of the processing strain layer formed on the back surface of the SiC substrate 11 that is the processed surface after grinding is allowed. Since it can be made as shallow as possible, warping of SiC substrate 11 can be more reliably suppressed. Therefore, the semiconductor device 100 with higher reliability can be obtained.
  • the back surface of SiC substrate 11 is a grindstone having an average abrasive grain size of 20 ⁇ m or less. Grinding.
  • the average abrasive grain size of the grindstone exceeds 20 ⁇ m, it becomes difficult to make the arithmetic average roughness Ra of the back surface of the SiC substrate 11 after grinding 10 nm or less. Therefore, the average abrasive grain size of the grindstone is preferably 20 ⁇ m or less.
  • the method of manufacturing the semiconductor device as shown in FIG. 1 has been described for the thinned SiC substrate 11.
  • the nanoparticle thin film 22 formed by the metal nanoparticles 21 is thick, the thickness of the alloy layer formed after the laser light irradiation is increased, and the stress of the alloy layer is increased. Thereby, the curvature of SiC substrate 11 increases.
  • the wafer may be cracked.
  • the nanoparticle thin film 22 becomes thin, it becomes difficult to form a uniform nanoparticle thin film 22 as a metal thin film.
  • pinholes are easily formed in the formed nanoparticle thin film 22. Therefore, the silicide layer 17 obtained after the laser beam irradiation is difficult to be uniform, and there is a possibility that a uniform ohmic electrode cannot be obtained, resulting in an increase in contact resistance and a decrease in the reliability of the semiconductor element 1.
  • the particle size of the metal nanoparticles will be described. As the particle size of the metal nanoparticles constituting the nanoparticle thin film 22 increases, the unevenness increases and the reflectance with respect to the laser beam decreases. However, when the particle size of the metal nanoparticles is large, it is difficult to form a uniform nanoparticle thin film 22 as a metal thin film when forming a thin metal thin film.
  • FIG. 9 is a cross-sectional view showing the nanoparticle thin film 22 in which the pinholes 42 are formed.
  • the thinned SiC substrate is indicated by a reference sign “41”.
  • the silicide layer 17 obtained after the laser light irradiation is difficult to be uniform, and there is a possibility that a uniform ohmic electrode cannot be obtained, resulting in an increase in contact resistance and a decrease in the reliability of the semiconductor element 1.
  • the particle size of the metal nanoparticles 21 is small, it is easy to form a thin and uniform nanoparticle thin film 22. Therefore, it is easy to form a thin and uniform alloy layer, a stable low contact resistance can be obtained, and a high element reliability can be obtained.
  • the unevenness of the nanoparticle thin film 22 is reduced and the reflectance with respect to the laser beam is increased, the energy of the laser beam required to obtain a low contact resistance is increased. Therefore, throughput and productivity are reduced.
  • the nanoparticle thin film 22 is formed on the thinned SiC substrate 41 and irradiated with laser light to form the ohmic electrode as follows.
  • the production of the semiconductor device 100 including the highly reliable semiconductor element 1 having a uniform and stable low contact resistance without increasing the warp of the SiC substrate 41 and cracking of the SiC substrate 41. Can be obtained by sex.
  • an SiC substrate 11, specifically, an n-type SiC substrate 11 is prepared.
  • SiC epitaxial layer 12 is grown on the surface of SiC substrate 11.
  • the doping concentration of the n-type impurity in SiC epitaxial layer 12 is, for example, 5 ⁇ 10 15 cm ⁇ 3 to 5 ⁇ 10 16 cm ⁇ 3 .
  • the film thickness of SiC epitaxial layer 12 is, for example, 5 ⁇ m to 15 ⁇ m.
  • An oxide film is formed on the surface of one side in the thickness direction of SiC epitaxial layer 12 by sacrificial oxidation.
  • a process for forming a p-type termination structure is performed. Specifically, first, an ion implantation mask is formed on the oxide film formed on the surface on one side in the thickness direction of SiC epitaxial layer 12.
  • a p-type impurity, for example, aluminum is ion-implanted from one side in the thickness direction of the ion implantation mask to selectively ion-implant the p-type impurity into a predetermined region of the SiC epitaxial layer 12 to form an ion implantation region 13.
  • the ion implantation region 13 has, for example, an implantation amount of 1 ⁇ 10 16 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 and an implantation depth of 0.5 ⁇ m to 1.0 ⁇ m at room temperature, for example, 25 ° C. It is formed by implanting p-type impurity ions such as aluminum ions at an energy of 40 keV to 700 keV with an implantation angle of 0 °.
  • the ion implantation mask is removed, the JTE region 14 is formed in the same manner as in the first embodiment, and the JTE mask and the oxide film used for forming the JTE region 14 are removed. Thereafter, in order to activate p-type impurity ions such as implanted aluminum ions, heat treatment is performed at a temperature of 1500 ° C. to 2000 ° C. for 1 minute to 30 minutes, for example, in an argon atmosphere. By this heat treatment step, the implanted ions are activated and a p-type termination structure is formed.
  • p-type impurity ions such as implanted aluminum ions
  • the Schottky electrode 15 is formed in the Schottky region 18 surrounded by the ion implantation region 13 so that the peripheral portion protrudes from the ion implantation region 13.
  • Examples of the material of the Schottky electrode 15 include titanium (Ti), tungsten (W), molybdenum (Mo), and chromium (Cr).
  • the wiring electrode 16 is formed on the surface on one side in the thickness direction of the Schottky electrode 15. Examples of the material of the wiring electrode 16 include Al.
  • the back surface of the SiC substrate 11, that is, the surface on the other side in the thickness direction is ground to reduce the thickness of the SiC substrate 11.
  • SiC substrate 11 is thinned so that the plate thickness becomes 200 ⁇ m or less by grinding the entire back surface of SiC substrate 11.
  • the fine grinding stone of 1000th or more having an average abrasive grain size of 20 ⁇ m or less on the back surface of the SiC substrate 11.
  • the arithmetic average roughness Ra of the back surface of the SiC substrate 11 is ground to 10 nm or less.
  • the nano particle thin film 22 is formed on the back surface of the SiC substrate 11.
  • the larger the metal nanoparticles have a larger particle size the larger the unevenness and the lower the reflectance with respect to the laser beam.
  • the particle size of the metal nanoparticles 21 is excessively large, it is difficult to form a uniform nanoparticle thin film 22, and pinholes 42 are easily formed in the formed nanoparticle thin film 22.
  • the particle size of the metal nanoparticles 21 is small, it is easy to form a thin and uniform nanoparticle thin film 22.
  • the particle diameter of the metal nanoparticles 21 is small, the unevenness of the nanoparticle thin film 22 is reduced, and the reflectance with respect to the laser light is increased.
  • metal nanoparticles having two or more particle size distribution peaks are used as the metal nanoparticles 21.
  • FIG. 10 is a cross-sectional view schematically showing the metal nanoparticles 21 used in the third embodiment of the present invention.
  • a relatively small metal nanoparticle hereinafter sometimes referred to as “small particle nanoparticle” 52 having a particle size of 1 nm or more and 50 nm or less, and a particle size exceeding 50 nm.
  • Metal nanoparticles 21 including relatively large metal nanoparticles (hereinafter sometimes referred to as “large particle size nanoparticles”) 51 of 100 nm or less are used.
  • the metal nanoparticle 21 has two or more particle size distribution peaks, and at least one of the particle size distribution peaks exists within a particle size range of 1 nm or more and less than 50 nm, and others. At least one of the above uses metal nanoparticles 21 present in a particle size range of 50 nm or more and less than 100 nm.
  • the metal nanoparticles 21 include the large particle size nanoparticles 51 and the small particle size nanoparticles 52. Therefore, as shown in FIG.
  • the nanoparticle thin film 22 can be formed. Thereby, the reflectance of the nanoparticle thin film 22 can be reduced. Moreover, since the pinhole 42 can be obstruct
  • the nanoparticle thin film 22 is formed as a metal thin film by the metal nanoparticles 21 as described above. Thereafter, the ohmic electrode is formed by irradiating the nanoparticle thin film 22 with laser light in the same manner as in the above-described embodiment.
  • the present embodiment there are two or more particle size distribution peaks, and at least one of the particle size distribution peaks is present within a particle size range of 1 nm or more and less than 50 nm, and other At least one of the metal nanoparticles 21 present in a particle size range of 50 nm or more and less than 100 nm is used.
  • the reflectance of the surface of the nanoparticle thin film 22 which is a metal thin film irradiated with laser light can be lowered, and the uniform nanoparticle thin film 22 without the pinhole 42 can be formed.
  • the reflectivity of the surface of the nanoparticle thin film 22 which is a metal thin film is reduced, and the energy density of the laser light necessary for forming the low resistance ohmic electrode is reduced.
  • the silicide layer 17 obtained after the laser light irradiation is uniform, a semiconductor device including the semiconductor element 1 having a uniform and stable low contact resistance and high reliability can be obtained with high productivity. Can do.
  • FIG. 11 is a flowchart showing the procedure of the back surface processing step in the semiconductor device manufacturing method according to the fourth embodiment of the present invention. Since the manufacturing method of the semiconductor device of this embodiment is the same as that of the second embodiment described above except that it includes the back surface processing step shown in FIG. 11, the description of the same steps is omitted.
  • the back surface processing step in the present embodiment is the second embodiment shown in FIG. 6 described above except that the film forming step of step c1 is provided between the thinning step of step b1 and the nano thin film forming step of step a1.
  • the back surface processing step in the present embodiment includes a thinning step in step b1, a film forming step in step c1, a nano thin film forming step in step a1, and an electrode forming step in step a2.
  • the nano thin film forming process in step a1 and the electrode forming process in step a2 constitute a silicide layer forming process.
  • FIG. 12 is a cross-sectional view showing a state at the stage where the silicide layer forming step is completed in the fourth embodiment of the present invention.
  • the base of the nanoparticle thin film 22 is formed by sputtering or vapor deposition as shown in FIG. A base metal thin film 61 is formed.
  • the silicide layer 17 is formed in the electrode forming process in step a2.
  • the film By forming the film by sputtering or vapor deposition, it is easy to form a uniform base metal thin film 61 without a pinhole.
  • the nanoparticle thin film 22 capable of reducing the surface reflectance on the surface of the underlying metal thin film 61, a uniform and low reflectance metal thin film can be formed.
  • the silicide layer 17 obtained after the laser light irradiation is made uniform.
  • the material of the base metal thin film 61 one or more selected from nickel (Ni), titanium (Ti), cobalt (Co), molybdenum (Mo), tungsten (W) and the like can be used.
  • the base metal thin film 61 Since the base metal thin film 61 has a large stress, if the thickness of the base metal thin film 61 is excessively large, the warp of the SiC substrate 11 is increased, and in the worst case, the SiC substrate 11 is cracked. In order to prevent this, it is desirable that the thickness of the base metal thin film 61 be 1 nm or more and 50 nm or less.
  • the material of the nanoparticle thin film 21 formed on the base metal thin film 61 is one or two selected from nickel (Ni), titanium (Ti), cobalt (Co), molybdenum (Mo), tungsten (W), and the like. The above can be used.
  • the material of the nanoparticle thin film 22 may be the same as or different from the material of the base metal thin film 61.
  • the thickness of the SiC substrate 11 must not be cracked by the stress of the alloy layer formed by the reaction between the base metal thin film 61, the nanoparticle thin film 22, and silicon carbide.
  • the total thickness of the base metal thin film 61 and the nanoparticle thin film 22 is smaller than the thickness of the SiC substrate 11. Therefore, it must be less than or equal to the value shown in equation (4) above.
  • the particle size of the metal nanoparticles is preferably 1 nm to 100 nm.
  • the nanoparticle thin film 22 as a metal thin film with metal nanoparticles on the surface of the base metal thin film 61 formed by sputtering or vapor deposition, a metal thin film is formed by another method such as vapor deposition. Compared with the case, the reflectance of a metal thin film can be made low. In addition, since an alloy layer with silicon carbide can be formed uniformly, a semiconductor device including a semiconductor element having a uniform and stable low contact resistance and high reliability can be obtained with high productivity.
  • the particle size distribution peaks there are two or more particle size distribution peaks, and at least one of the particle size distribution peaks is within the range of the particle size of 1 nm or more and less than 50 nm.
  • a more uniform nanoparticle thin film 22 can be formed by using the metal nanoparticles 21 that are present and at least one of them exists in a particle size range of 50 nm or more and less than 100 nm.
  • the film thickness of the base metal thin film 61 is preferably 1 nm or more and 50 nm or less. Further, when the total thickness of the nanoparticle thin film 22 and the base metal thin film 61 is z (nm) and the thickness of the SiC substrate 41 is x ( ⁇ m), the following formula (6) is satisfied. It is preferable. z ⁇ (0.0347x 2 ⁇ 0.8212x + 21.286) (6)
  • the SBD using SiC is exemplified as the semiconductor element 1, but the semiconductor element 1 is not limited to this, and may be, for example, a MOSFET. Even when the semiconductor element 1 is a MOSFET, a low-resistance ohmic electrode can be formed by the same method as in the present embodiment.
  • Ni nickel
  • Mo molybdenum
  • W tungsten
  • the present invention can freely combine the above-described embodiments within the scope of the invention, and can arbitrarily modify or omit any component of each embodiment.
  • nitride semiconductor element 10 SiC substrate, 11, 41 SiC substrate, 12 SiC epitaxial layer, 13 ion implantation region, 14 JTE region, 15 Schottky electrode, 16 wiring electrode, 17 silicide layer, 18 Schottky region, 20 device part, 21 metal nanoparticles, 22 nanoparticle thin film, 51 large particle size nanoparticle, 52 small particle size nanoparticle, 61 base metal thin film, 100 semiconductor device.

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Abstract

The purpose of the present invention is to provide a semiconductor device manufacturing method wherein, without deteriorating reliability, a low-resistance ohmic electrode can be formed by radiating laser light having lowest possible energy density. A metal thin film (22) is formed of metal nanoparticles (21) on one surface of a SiC substrate (11) in the thickness direction. Consequently, reflectance of the metal thin film (22) can be reduced without polishing the SiC substrate (11). Since an ohmic electrode is formed by radiating laser light to the metal thin film (22) having the reduced reflectance, laser light energy density necessary to form the ohmic electrode can be reduced. Furthermore, since the polishing is not performed to the SiC substrate (11), an increase of warpage of the SiC substrate (11) is eliminated by eliminating generation of deformed layer due to the process, and reliability of the semiconductor device is prevented from being deteriorated.

Description

半導体装置の製造方法Manufacturing method of semiconductor device

 本発明は、半導体装置の製造方法に関し、より詳細には、炭化珪素(SiC)半導体を用いた半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a silicon carbide (SiC) semiconductor.

 炭化珪素(SiC)半導体を用いると、珪素(Si)半導体を用いる場合に比べて、オン抵抗が低い半導体装置を製作することが可能である。したがって、SiC半導体を用いた半導体装置は、次世代の高電力用半導体装置として期待されている。 When a silicon carbide (SiC) semiconductor is used, it is possible to manufacture a semiconductor device having a lower on-resistance than when a silicon (Si) semiconductor is used. Therefore, a semiconductor device using a SiC semiconductor is expected as a next-generation high power semiconductor device.

 半導体装置のオン抵抗は、電流が流れる経路の抵抗値の総和によって決定される。半導体装置のオン抵抗には、半導体と各種配線とを連結する役割を担うオーミック電極で生じる抵抗が含まれる。したがって、炭化珪素基板およびドリフト層などの抵抗と比べて充分に低い抵抗のオーミック電極を形成することが求められる。 The on-resistance of the semiconductor device is determined by the sum of resistance values of paths through which current flows. The on-resistance of the semiconductor device includes a resistance generated by an ohmic electrode that plays a role of connecting the semiconductor and various wirings. Therefore, it is required to form an ohmic electrode having a sufficiently low resistance compared to the resistance of the silicon carbide substrate and the drift layer.

 SiCにオーミック電極を形成する方法として、SiC基板に、オーミック電極となる金属薄膜を堆積し、堆積した金属薄膜にレーザ光を照射する方法がある(たとえば、特許文献1~3参照)。SiC基板に金属薄膜を堆積し、堆積した金属薄膜にレーザ光を照射すると、金属薄膜がレーザ光のエネルギーを吸収して、吸収されたエネルギーが熱に変わる。この熱によって、金属薄膜とSiCとが合金化する。これによって、金属薄膜とSiCとの接触がオーミックコンタクトとなるので、低抵抗のオーミック電極を得ることができる。 As a method of forming an ohmic electrode on SiC, there is a method of depositing a metal thin film to be an ohmic electrode on a SiC substrate and irradiating the deposited metal thin film with laser light (see, for example, Patent Documents 1 to 3). When a metal thin film is deposited on a SiC substrate and the deposited metal thin film is irradiated with laser light, the metal thin film absorbs the energy of the laser light, and the absorbed energy is changed to heat. With this heat, the metal thin film and SiC are alloyed. Thereby, since the contact between the metal thin film and SiC becomes an ohmic contact, a low-resistance ohmic electrode can be obtained.

 たとえば、特許文献1に開示される半導体装置製造方法では、第1導電型の炭化珪素基板上に第2導電型の不純物ドープ層を形成し、形成した不純物ドープ層上に金属薄膜を設け、金属薄膜の上面からレーザ光を照射してオーミック電極を形成している。 For example, in the semiconductor device manufacturing method disclosed in Patent Document 1, a second conductivity type impurity doped layer is formed on a first conductivity type silicon carbide substrate, a metal thin film is provided on the formed impurity doped layer, and a metal An ohmic electrode is formed by irradiating laser light from the upper surface of the thin film.

 特許文献2に開示される半導体装置の製造方法では、単結晶炭化珪素から成る半導体基板の裏面を研磨して裏面に凹凸を形成した後、半導体基板の裏面上に金属薄膜を形成し、形成した金属薄膜にレーザ光を照射することによって、オーミック電極を形成している。 In the method of manufacturing a semiconductor device disclosed in Patent Document 2, a back surface of a semiconductor substrate made of single crystal silicon carbide is polished to form irregularities on the back surface, and then a metal thin film is formed on the back surface of the semiconductor substrate. The ohmic electrode is formed by irradiating the metal thin film with laser light.

 特許文献3に開示される炭化珪素半導体装置の製造方法では、炭化珪素基板の裏面をイオンプラズマなどで表面処理した後、裏面上に金属薄膜を形成し、形成した金属薄膜にレーザ光を照射することによって、オーミック電極を形成している。 In the method for manufacturing a silicon carbide semiconductor device disclosed in Patent Document 3, after the surface of the silicon carbide substrate is subjected to surface treatment with ion plasma or the like, a metal thin film is formed on the back surface, and the formed metal thin film is irradiated with laser light. Thus, an ohmic electrode is formed.

特開2004-158702号公報JP 2004-158702 A 特開2008-135611号公報JP 2008-135611 A 特開2011-91100号公報JP 2011-91100 A

 前述の特許文献1~3に開示されるように金属薄膜にレーザ光を照射してオーミック電極を形成する場合、低抵抗のオーミック電極を得るために必要なエネルギー密度のレーザ光を、金属薄膜上で走査する必要がある。したがって、金属薄膜にレーザ光を照射してオーミック電極を形成する処理は、基板を1枚ずつ処理する枚葉処理で行われるので、処理時間が長くなるという問題がある。基板が大口径化して、レーザ光を照射すべき面積が大きくなると、処理時間の問題はさらに顕著になる。 In the case where an ohmic electrode is formed by irradiating a metal thin film with laser light as disclosed in Patent Documents 1 to 3, the laser light having an energy density necessary for obtaining a low resistance ohmic electrode is applied on the metal thin film. It is necessary to scan with. Accordingly, the process of irradiating the metal thin film with the laser beam to form the ohmic electrode is performed by a single wafer process in which the substrates are processed one by one. As the substrate becomes larger and the area to be irradiated with laser light becomes larger, the problem of processing time becomes more prominent.

 レーザ光の照射によるオーミック電極の形成に要する処理時間を短縮するためには、オーミック電極の形成に必要なエネルギー密度を保持したまま、レーザ光のビーム径を大きくする必要がある。具体的には、レーザ光照射装置のレーザ素子の出力を大きくする必要がある。しかし、出力が大きくなると、レーザ素子の製造コストが高くなるので、レーザ光照射装置の製造コストが増大してしまう。また、レーザ素子が消耗しやすくなり、交換の頻度が増加するので、レーザ光照射装置のランニングコストも増大する。 In order to shorten the processing time required for forming an ohmic electrode by laser light irradiation, it is necessary to increase the beam diameter of the laser light while maintaining the energy density necessary for forming the ohmic electrode. Specifically, it is necessary to increase the output of the laser element of the laser beam irradiation apparatus. However, when the output increases, the manufacturing cost of the laser element increases, and thus the manufacturing cost of the laser beam irradiation apparatus increases. Further, since the laser element is easily consumed and the frequency of replacement increases, the running cost of the laser beam irradiation apparatus also increases.

 オーミック電極の形成に要する処理時間を短縮するための他の方法としては、低抵抗のオーミック電極を得るために必要なレーザ光のエネルギー密度を小さくすることが考えられる。低抵抗のオーミック電極を得るために必要なレーザ光のエネルギー密度を小さくすることができれば、その分、レーザ光のビーム径を大きくすることができるので、レーザ光照射装置による処理時間を短縮することができる。 As another method for shortening the processing time required for forming the ohmic electrode, it is conceivable to reduce the energy density of the laser beam necessary for obtaining a low-resistance ohmic electrode. If the energy density of the laser beam necessary for obtaining a low-resistance ohmic electrode can be reduced, the beam diameter of the laser beam can be increased accordingly, so that the processing time by the laser beam irradiation apparatus can be shortened. Can do.

 炭化珪素基板に堆積された金属薄膜にレーザ光を照射するとき、照射されるレーザ光の一部は金属薄膜の表面で反射し、その他のレーザ光は金属薄膜中に侵入して吸収され、熱エネルギーに変わる。オーミック電極の形成に寄与するレーザ光は、照射されるレーザ光のうち、金属薄膜中に侵入して吸収され、熱エネルギーに変わる成分である。金属表面の表面で反射するレーザ光の成分は、オーミック電極の形成には寄与せず、無駄なエネルギーとなってしまう。 When irradiating a metal thin film deposited on a silicon carbide substrate with laser light, a part of the irradiated laser light is reflected by the surface of the metal thin film, and the other laser light penetrates into the metal thin film and is absorbed and heated. It turns into energy. Laser light that contributes to the formation of the ohmic electrode is a component of the irradiated laser light that penetrates into the metal thin film and is absorbed and converted into thermal energy. The component of the laser beam reflected on the surface of the metal surface does not contribute to the formation of the ohmic electrode, and is wasted energy.

 金属薄膜の表面で、レーザ光がどの程度反射するかは、レーザ光に対する金属薄膜の反射率に依る。金属薄膜のレーザ光に対する反射率は比較的大きく、照射されるレーザ光のエネルギーのうち、反射して無駄になるエネルギーは比較的大きい。 The extent to which the laser beam is reflected on the surface of the metal thin film depends on the reflectance of the metal thin film with respect to the laser beam. The reflectance of the metal thin film with respect to the laser beam is relatively large, and the energy of the reflected laser beam is relatively large among the energy of the irradiated laser beam.

 金属薄膜の表面での反射率が低いと、その分金属薄膜中に侵入して吸収されて熱に変わるレーザ光のエネルギーは大きくなる。したがって、比較的小さいエネルギー密度のレーザ光の照射によって、効率良く低抵抗のオーミック電極を形成することができる。換言すれば、低抵抗のオーミック電極の形成に必要なレーザ光のエネルギー密度を小さくすることができるので、その分レーザ光のビーム径を大きくして、レーザ光照射装置による処理時間を短縮することができる。 If the reflectivity at the surface of the metal thin film is low, the energy of the laser beam that enters the metal thin film and is absorbed and converted into heat increases. Therefore, an ohmic electrode having a low resistance can be efficiently formed by irradiation with laser light having a relatively low energy density. In other words, the energy density of the laser light necessary for forming the low-resistance ohmic electrode can be reduced, so that the laser light beam diameter is increased and the processing time by the laser light irradiation apparatus is shortened accordingly. Can do.

 レーザ光の反射率は、金属薄膜の表面の形状によって変化する。金属薄膜の表面に凹凸があると、レーザ光の反射率は低下する。たとえば、前述の特許文献2に開示される技術のように、半導体基板の裏面に凹凸を形成すると、金属薄膜の表面に凹凸が形成されるので、レーザ光の反射率を低下させることが可能である。 レ ー ザ The reflectance of the laser beam varies depending on the shape of the surface of the metal thin film. If the surface of the metal thin film has irregularities, the reflectance of the laser beam decreases. For example, as in the technique disclosed in Patent Document 2 described above, when irregularities are formed on the back surface of the semiconductor substrate, irregularities are formed on the surface of the metal thin film, so that it is possible to reduce the reflectance of the laser beam. is there.

 しかし、特許文献2に開示される技術のように研磨加工によって凹凸を形成すると、炭化珪素基板に歪層(以下「加工歪層」という場合がある)が形成される。加工歪層が形成されると、基板に反りが発生してしまう。凹凸を大きくするためには、砥粒の粗い砥石を使用しなければならないが、砥粒が粗いほど、炭化珪素基板に加工歪層が深く形成されるので、基板の反りも大きくなってしまう。 However, when irregularities are formed by polishing as in the technique disclosed in Patent Document 2, a strained layer (hereinafter sometimes referred to as “worked strained layer”) is formed on the silicon carbide substrate. When the processing strain layer is formed, the substrate is warped. In order to increase the unevenness, a grindstone with coarse abrasive grains must be used. However, the coarser the abrasive grains, the deeper the processing strain layer is formed on the silicon carbide substrate, and the greater the warpage of the substrate.

 基板に発生した反りは、その後のプロセスにおいて、基板の吸着チャックエラーおよび基板の割れを引起こし、円滑な基板搬送を妨げ、半導体製造システムの自動化の妨げとなる。また加工歪層は、デバイスの信頼性にも悪影響を及ぼすおそれがある。 The warpage generated in the substrate causes an error in chucking the substrate and cracking the substrate in the subsequent process, hindering smooth substrate conveyance and hindering automation of the semiconductor manufacturing system. In addition, the processed strain layer may adversely affect the reliability of the device.

 また、特許文献3に開示される技術では、炭化珪素基板の表面を、レーザ光の波長において(100%-反射率-透過率)が80%以上になるようにイオンプラズマなどで加工した後、金属薄膜を堆積してレーザ光を照射する。金属薄膜の膜厚がレーザ光の侵入長以上に厚い場合、金属薄膜のみでレーザ光を吸収するので、特許文献3に開示される技術では、低抵抗のオーミック電極の形成に必要なレーザ光のエネルギー密度を小さくする効果は得られない。たとえば、金属薄膜がニッケルの場合、波長が100nm~1500nmの光の侵入長は10nm~20nm程度である。したがって、これ以上の膜厚の金属薄膜では、炭化珪素基板の表面をイオンプラズマなどで加工しても、低抵抗のオーミック電極の形成に必要なレーザ光のエネルギー密度は変わらない。 In the technique disclosed in Patent Document 3, the surface of the silicon carbide substrate is processed with ion plasma or the like so that (100% −reflectance−transmittance) is 80% or more at the wavelength of the laser beam. A metal thin film is deposited and irradiated with laser light. When the thickness of the metal thin film is larger than the penetration length of the laser beam, the laser beam is absorbed only by the metal thin film. Therefore, in the technique disclosed in Patent Document 3, the laser beam necessary for forming a low-resistance ohmic electrode is used. The effect of reducing the energy density cannot be obtained. For example, when the metal thin film is nickel, the penetration depth of light having a wavelength of 100 nm to 1500 nm is about 10 nm to 20 nm. Therefore, in a metal thin film having a thickness greater than this, even if the surface of the silicon carbide substrate is processed with ion plasma or the like, the energy density of the laser light necessary for forming the low-resistance ohmic electrode does not change.

 本発明の目的は、信頼性を損なうことなく、可及的に小さいエネルギー密度のレーザ光の照射によって低抵抗のオーミック電極を形成することができる半導体装置の製造方法を提供することである。 An object of the present invention is to provide a semiconductor device manufacturing method capable of forming a low-resistance ohmic electrode by irradiating laser light with as low energy density as possible without impairing reliability.

 本発明の半導体装置の製造方法は、炭化珪素基板の厚み方向の一表面上に、金属ナノ粒子によって、金属薄膜であるナノ粒子薄膜を形成するナノ薄膜形成工程と、前記ナノ薄膜形成工程で形成された前記ナノ粒子薄膜にレーザ光を照射することによってオーミック電極を形成する電極形成工程とを備えることを特徴とする。 The method for manufacturing a semiconductor device of the present invention includes a nano thin film forming step of forming a nano particle thin film, which is a metal thin film, with metal nanoparticles on one surface in the thickness direction of a silicon carbide substrate, and the nano thin film forming step. And an electrode forming step of forming an ohmic electrode by irradiating the nanoparticle thin film with a laser beam.

 本発明の半導体装置の製造方法によれば、ナノ薄膜形成工程において、炭化珪素基板の厚み方向の一表面上に、金属ナノ粒子によって、金属薄膜であるナノ粒子薄膜が形成される。このナノ薄膜形成工程で形成されたナノ粒子薄膜に、電極形成工程においてレーザ光が照射されることによって、オーミック電極が形成される。金属ナノ粒子によって、金属薄膜としてナノ粒子薄膜を形成することによって、炭化珪素基板に研磨加工を施すことなく、金属薄膜の反射率を低下させることができる。この反射率が低下された金属薄膜であるナノ粒子薄膜に、電極形成工程でレーザ光が照射されて、オーミック電極が形成されるので、低抵抗のオーミック電極の形成に必要なレーザ光のエネルギー密度を低減することができる。また炭化珪素基板には研磨加工が施されないので、加工歪層の発生を防いで炭化珪素基板の反りの増加を防ぎ、半導体装置の信頼性が損なわれることを防ぐことができる。したがって、半導体装置の信頼性を損なうことなく、可及的に小さいエネルギー密度のレーザ光の照射によって、低抵抗のオーミック電極を形成することができる。 According to the method of manufacturing a semiconductor device of the present invention, in the nano thin film forming step, a nano particle thin film that is a metal thin film is formed on one surface in the thickness direction of the silicon carbide substrate by the metal nanoparticles. An ohmic electrode is formed by irradiating the nanoparticle thin film formed in the nano thin film forming process with laser light in the electrode forming process. By forming the nanoparticle thin film as a metal thin film with the metal nanoparticles, the reflectance of the metal thin film can be reduced without polishing the silicon carbide substrate. The nanoparticle thin film, which is a metal thin film with a reduced reflectivity, is irradiated with laser light in the electrode formation process to form an ohmic electrode. Therefore, the energy density of the laser light necessary to form a low-resistance ohmic electrode Can be reduced. Further, since the silicon carbide substrate is not polished, it is possible to prevent the generation of a processing strain layer, to prevent the silicon carbide substrate from being warped, and to prevent the reliability of the semiconductor device from being impaired. Therefore, a low resistance ohmic electrode can be formed by irradiating laser light with as low energy density as possible without impairing the reliability of the semiconductor device.

 この発明の目的、特徴、局面、および利点は、以下の詳細な説明と添付図面とによって、より明白となる。 The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

本発明の第1の実施の形態における半導体装置100の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device 100 in the 1st Embodiment of this invention. 本発明の第1の実施の形態の半導体装置100の製造方法におけるシリサイド層形成工程の手順を示すフローチャートである。It is a flowchart which shows the procedure of the silicide layer formation process in the manufacturing method of the semiconductor device 100 of the 1st Embodiment of this invention. ナノ粒子薄膜22を形成した状態を示す断面図である。It is sectional drawing which shows the state in which the nanoparticle thin film 22 was formed. ナノ粒子薄膜22にレーザ光を照射する様子を示す断面図である。It is sectional drawing which shows a mode that a nanoparticle thin film 22 is irradiated with a laser beam. シリサイド層17の形成が終了した段階の状態を示す断面図である。FIG. 5 is a cross-sectional view showing a state at a stage where formation of a silicide layer 17 is completed. 本発明の第2の実施の形態の半導体装置の製造方法における裏面加工工程の手順を示すフローチャートである。It is a flowchart which shows the procedure of the back surface process in the manufacturing method of the semiconductor device of the 2nd Embodiment of this invention. 荷重と応力との関係を説明するための図である。It is a figure for demonstrating the relationship between a load and a stress. SiC基板11に割れが生じるときのSiC基板11の厚みとNi膜の厚みとの関係を示すグラフである。It is a graph which shows the relationship between the thickness of SiC substrate 11, and the thickness of Ni film when a crack arises in SiC substrate 11. ピンホール42が形成されたナノ粒子薄膜22を示す断面図である。It is sectional drawing which shows the nanoparticle thin film 22 in which the pinhole 42 was formed. 本発明の第3の実施の形態で用いられる金属ナノ粒子21を模式的に示す断面図である。It is sectional drawing which shows typically the metal nanoparticle 21 used in the 3rd Embodiment of this invention. 本発明の第4の実施の形態の半導体装置の製造方法における裏面加工工程の手順を示すフローチャートである。It is a flowchart which shows the procedure of the back surface process in the manufacturing method of the semiconductor device of the 4th Embodiment of this invention. 本発明の第4の実施の形態においてシリサイド層形成工程が終了した段階の状態を示す断面図である。It is sectional drawing which shows the state of the stage which the silicide layer formation process was complete | finished in the 4th Embodiment of this invention.

 <第1の実施の形態>
 図1は、本発明の第1の実施の形態における半導体装置100の構成を示す断面図である。半導体装置100は、本発明の第1の実施の形態の半導体装置の製造方法によって製造される。半導体装置100は、炭化珪素半導体素子(以下、単に「半導体素子」という場合がある)1を備える。本実施の形態では、半導体素子1は、炭化珪素(SiC)を用いたショットキバリアダイオード(Schottky Barrier Diode;略称:SBD)である。SBDでは、金属と半導体との接触が大きな役割を果たす。
<First Embodiment>
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device 100 according to the first embodiment of the present invention. The semiconductor device 100 is manufactured by the method for manufacturing a semiconductor device according to the first embodiment of the present invention. Semiconductor device 100 includes a silicon carbide semiconductor element (hereinafter sometimes simply referred to as “semiconductor element”) 1. In the present embodiment, the semiconductor element 1 is a Schottky Barrier Diode (abbreviation: SBD) using silicon carbide (SiC). In SBD, the contact between a metal and a semiconductor plays a major role.

 半導体素子1は、炭化珪素(SiC)基板11、炭化珪素(SiC)エピタキシャル層12、イオン注入領域13、ジャンクション終端拡張(Junction Termination Extension;略称:JTE)領域14、ショットキ電極15、配線電極16およびシリサイド層17を備えて構成される。イオン注入領域13はSiCエピタキシャル層12に形成される。 The semiconductor element 1 includes a silicon carbide (SiC) substrate 11, a silicon carbide (SiC) epitaxial layer 12, an ion implantation region 13, a junction termination extension (JTE) region 14, a Schottky electrode 15, a wiring electrode 16, and A silicide layer 17 is provided. Ion implantation region 13 is formed in SiC epitaxial layer 12.

 SiC基板11は、n型の導電性を有する。SiC基板11は、本実施の形態では、厚み方向一方側の表面の面方位が<0001>シリコン面から4°または8°オフした、すなわち4°または8°傾斜した4H型のポリタイプを有するn型低抵抗基板である。 The SiC substrate 11 has n-type conductivity. In this embodiment, SiC substrate 11 has a 4H type polytype in which the surface orientation on one side in the thickness direction is off by 4 ° or 8 ° from the <0001> silicon surface, that is, inclined by 4 ° or 8 °. It is an n-type low resistance substrate.

 ドリフト層であるSiCエピタキシャル層12は、SiC基板11の厚み方向一方側の表面上に設けられている。以下の説明では、SiC基板の厚み方向一方側の表面を、単に「SiC基板の表面」という場合がある。SiCエピタキシャル層12は、n型不純物を含有しており、n型の導電型を有している。 The SiC epitaxial layer 12 which is a drift layer is provided on the surface of one side in the thickness direction of the SiC substrate 11. In the following description, the surface on one side in the thickness direction of the SiC substrate may be simply referred to as “the surface of the SiC substrate”. SiC epitaxial layer 12 contains n-type impurities and has n-type conductivity.

 SiCエピタキシャル層12におけるn型不純物の濃度は、想定する耐圧によって異なるが、たとえば、5×1015個cm-3~5×1016個cm-3である。SiCエピタキシャル層12の厚み(以下「膜厚」という場合がある)は、想定する耐圧によって異なるが、たとえば5μm~15μmである。以下の説明では、SiC基板11とSiCエピタキシャル層12とを合わせて、「SiC基体10」という場合がある。 The n-type impurity concentration in SiC epitaxial layer 12 varies depending on the assumed breakdown voltage, but is, for example, 5 × 10 15 cm −3 to 5 × 10 16 cm −3 . The thickness of SiC epitaxial layer 12 (hereinafter sometimes referred to as “film thickness”) varies depending on the assumed breakdown voltage, but is, for example, 5 μm to 15 μm. In the following description, the SiC substrate 11 and the SiC epitaxial layer 12 may be collectively referred to as “SiC substrate 10”.

 イオン注入領域13は、SiCエピタキシャル層12の厚み方向一方側の表面近傍部に形成されている。「表面近傍部」は、表面とその近傍の部分とを含む。イオン注入領域13は、厚み方向一方側から見た平面形状が環状、より詳細には略矩形の環状に形成されている。 The ion implantation region 13 is formed in the vicinity of the surface on one side in the thickness direction of the SiC epitaxial layer 12. The “surface vicinity portion” includes the surface and a portion in the vicinity thereof. The ion implantation region 13 is formed in an annular shape, more specifically in a substantially rectangular shape, as viewed from one side in the thickness direction.

 イオン注入領域13は、p型の活性化領域であり、p型不純物を含有する。イオン注入領域13は、たとえばアルミニウム(Al)をp型不純物として含有する。イオン注入領域13は、Alイオンなどのp型不純物イオンをイオン注入することによって形成される。イオン注入領域13におけるAlイオンなどのp型不純物イオンの注入量は、たとえば、1×1017個cm-3~1×1018個cm-3である。 The ion implantation region 13 is a p-type activation region and contains a p-type impurity. Ion implantation region 13 contains, for example, aluminum (Al) as a p-type impurity. The ion implantation region 13 is formed by ion implantation of p-type impurity ions such as Al ions. The implantation amount of p-type impurity ions such as Al ions in the ion implantation region 13 is, for example, 1 × 10 17 cm −3 to 1 × 10 18 cm −3 .

 JTE領域14は、SiCエピタキシャル層12の厚み方向一方側の表面近傍部に形成されている。JTE領域14は、厚み方向一方側から見て、イオン注入領域13に隣接して形成されている。JTE領域14は、厚み方向一方側から見た平面形状が環状、より詳細には略矩形の環状に形成される。より詳細には、JTE領域14は、厚み方向一方側から見て、イオン注入領域13を囲繞するように形成されている。 The JTE region 14 is formed in the vicinity of the surface on one side in the thickness direction of the SiC epitaxial layer 12. The JTE region 14 is formed adjacent to the ion implantation region 13 when viewed from one side in the thickness direction. The JTE region 14 is formed in an annular shape, more specifically in a substantially rectangular shape, when viewed from one side in the thickness direction. More specifically, the JTE region 14 is formed so as to surround the ion implantation region 13 when viewed from one side in the thickness direction.

 JTE領域14は、耐圧を上げるために設けられる。JTE領域14を、半導体素子1の周辺部であるイオン注入領域13の外側の部分に設けることによって、SiCエピタキシャル層12の厚み方向一方側の表面における電界強度を緩和することができる。 The JTE region 14 is provided to increase the breakdown voltage. By providing the JTE region 14 at a portion outside the ion implantation region 13 that is the peripheral portion of the semiconductor element 1, the electric field strength on the surface on one side in the thickness direction of the SiC epitaxial layer 12 can be reduced.

 イオン注入領域13およびJTE領域14は、p型終端構造を構成する。SiCエピタキシャル層12の厚み方向一方側の表面近傍部のうち、イオン注入領域13に囲まれた領域を、ショットキ領域18という。 The ion implantation region 13 and the JTE region 14 constitute a p-type termination structure. A region surrounded by the ion implantation region 13 in the vicinity of the surface on one side in the thickness direction of the SiC epitaxial layer 12 is referred to as a Schottky region 18.

 ショットキ電極15は、SiCエピタキシャル層12の厚み方向一方側の表面上、より詳細にはショットキ領域18の表面上およびイオン注入領域13の一部の表面上に設けられている。ショットキ電極15の材料としては、チタン(Ti)、タングステン(W)、モリブデン(Mo)およびクロム(Cr)などが挙げられる。これらの材料から選ばれる1種または2種以上によってショットキ電極15が形成される。 The Schottky electrode 15 is provided on the surface on one side in the thickness direction of the SiC epitaxial layer 12, more specifically, on the surface of the Schottky region 18 and on a part of the surface of the ion implantation region 13. Examples of the material of the Schottky electrode 15 include titanium (Ti), tungsten (W), molybdenum (Mo), and chromium (Cr). The Schottky electrode 15 is formed of one or more selected from these materials.

 配線電極16は、ショットキ電極15の厚み方向一方側の表面上に設けられている。配線電極16の材料としては、Alなどが挙げられる。 The wiring electrode 16 is provided on the surface of one side in the thickness direction of the Schottky electrode 15. Examples of the material of the wiring electrode 16 include Al.

 シリサイド層17は、SiC基板11の厚み方向一方側の表面とは反対側の表面、すなわちSiC基板11の厚み方向他方側の表面上に設けられている。本実施の形態では、SiC基板11の厚み方向他方側の表面が、金属薄膜が形成されるSiC基板の厚み方向の一表面に相当する。以下の説明では、SiC基板の厚み方向他方側の表面を、「SiC基板の裏面」という場合がある。 The silicide layer 17 is provided on the surface opposite to the surface on one side in the thickness direction of the SiC substrate 11, that is, on the surface on the other side in the thickness direction of the SiC substrate 11. In the present embodiment, the surface on the other side in the thickness direction of SiC substrate 11 corresponds to one surface in the thickness direction of the SiC substrate on which the metal thin film is formed. In the following description, the surface on the other side in the thickness direction of the SiC substrate may be referred to as “the back surface of the SiC substrate”.

 シリサイド層17は、コンタクト電極膜とSiCとが反応したものであり、SiC基板11とオーミックコンタクトしている。コンタクト電極膜の材料としては、ニッケル(Ni)、チタン(Ti)、コバルト(Co)、モリブデン(Mo)およびタングステン(W)などが挙げられる。これらの材料から選ばれる1種または2種以上によってコンタクト電極膜が形成される。 The silicide layer 17 is a reaction between the contact electrode film and SiC, and is in ohmic contact with the SiC substrate 11. Examples of the material for the contact electrode film include nickel (Ni), titanium (Ti), cobalt (Co), molybdenum (Mo), and tungsten (W). A contact electrode film is formed of one or more selected from these materials.

 本実施の形態では、SBDである半導体素子1において、SiC基板11の厚み方向他方側の表面に形成されるオーミック電極を例に説明する。本実施の形態では、半導体素子1の一例としてSBDを挙げたが、これに限らず、半導体素子1は、金属-酸化膜-半導体電界効果型トランジスタ(Metal Oxide Semiconductor Field Effect Transistor;略称:MOSFET)であってもよい。 In the present embodiment, an ohmic electrode formed on the surface of the other side in the thickness direction of the SiC substrate 11 in the semiconductor element 1 which is an SBD will be described as an example. In the present embodiment, the SBD has been described as an example of the semiconductor element 1. However, the semiconductor element 1 is not limited thereto, and the semiconductor element 1 is a metal-oxide-semiconductor field-effect transistor (Metal Oxide Semiconductor Field Effect Transistor; abbreviation: MOSFET). It may be.

 次に、図1に示す半導体素子1であるSiCショットキバリアダイオードを備える半導体装置100の製造方法について説明する。本実施の形態の半導体装置の製造方法は、準備工程と、表面加工工程と、裏面加工工程とを備える。 Next, a method for manufacturing the semiconductor device 100 including the SiC Schottky barrier diode that is the semiconductor element 1 shown in FIG. 1 will be described. The method for manufacturing a semiconductor device according to the present embodiment includes a preparation process, a front surface processing process, and a back surface processing process.

 はじめに、準備工程において、SiC基板11などの半導体装置100の製造に必要な材料および装置を準備する。本実施の形態では、SiC基板11として、n型の導電性を有するSiC基板11、具体的には、厚み方向一方側の表面の面方位が<0001>シリコン面から4°または8°オフした4H型のポリタイプのn型低抵抗SiC基板11を準備する。SiC基板11などの半導体装置100の製造に必要な材料および装置を準備すると、表面加工工程に移行する。 First, in the preparation step, materials and devices necessary for manufacturing the semiconductor device 100 such as the SiC substrate 11 are prepared. In the present embodiment, as SiC substrate 11, SiC substrate 11 having n-type conductivity, specifically, the surface orientation of the surface on one side in the thickness direction is off by 4 ° or 8 ° from the <0001> silicon surface. A 4H type polytype n-type low resistance SiC substrate 11 is prepared. When materials and apparatuses necessary for manufacturing the semiconductor device 100 such as the SiC substrate 11 are prepared, the process proceeds to a surface processing step.

 表面加工工程では、まず、SiC基板11の厚み方向一方側の表面上に、SiCエピタキシャル層12を成長させる。これによって、SiC基体10が得られる。SiCエピタキシャル層12は、n型不純物のドーピング濃度が、5×1015個cm-3~5×1016個cm-3になるように形成される。SiCエピタキシャル層12は、膜厚が、5μm~15μmになるように形成される。SiCエピタキシャル層12を成長させた後は、SiCエピタキシャル層12の厚み方向一方側の表面上に、犠牲酸化によって、酸化膜を形成する。 In the surface processing step, first, the SiC epitaxial layer 12 is grown on the surface of one side in the thickness direction of the SiC substrate 11. Thereby, the SiC substrate 10 is obtained. The SiC epitaxial layer 12 is formed so that the doping concentration of the n-type impurity is 5 × 10 15 cm −3 to 5 × 10 16 cm −3 . The SiC epitaxial layer 12 is formed so as to have a film thickness of 5 μm to 15 μm. After the SiC epitaxial layer 12 is grown, an oxide film is formed on the surface on one side in the thickness direction of the SiC epitaxial layer 12 by sacrificial oxidation.

 次に、p型終端構造を形成する処理を行う。具体的には、まず、SiCエピタキシャル層12の厚み方向一方側の表面上に形成した酸化膜上に、イオン注入のためのマスク(以下「イオン注入マスク」という)を形成する。このイオン注入マスクの厚み方向一方側から、p型不純物、たとえばアルミニウムをイオン注入することによって、p型不純物をSiCエピタキシャル層12の予め定める領域に選択的にイオン注入し、イオン注入領域13を形成する。 Next, a process for forming a p-type termination structure is performed. Specifically, first, a mask for ion implantation (hereinafter referred to as “ion implantation mask”) is formed on the oxide film formed on the surface of one side in the thickness direction of SiC epitaxial layer 12. A p-type impurity, for example, aluminum is ion-implanted from one side in the thickness direction of the ion implantation mask to selectively ion-implant the p-type impurity into a predetermined region of the SiC epitaxial layer 12 to form an ion implantation region 13. To do.

 イオン注入領域13は、たとえば、注入量が1×1017cm-3~1×1018cm-3となり、注入深さが0.5μm~1.0μmとなるように、室温たとえば25℃で、注入角度を0°として、40keV~700keVのエネルギーでp型不純物イオン、たとえばアルミニウムイオンを注入することによって形成される。 The ion implantation region 13 has, for example, an implantation amount of 1 × 10 17 cm −3 to 1 × 10 18 cm −3 and an implantation depth of 0.5 μm to 1.0 μm at room temperature, for example, 25 ° C. It is formed by implanting p-type impurity ions such as aluminum ions at an energy of 40 keV to 700 keV with an implantation angle of 0 °.

 次に、イオン注入マスクを除去し、酸化膜上に、JTE領域14を形成するためのJTE用マスクを形成する。JTE用マスクの厚み方向一方側から、p型不純物、たとえばアルミニウムをイオン注入することによって、p型不純物をSiCエピタキシャル層12の予め定める領域に選択的にイオン注入し、JTE領域14を形成する。 Next, the ion implantation mask is removed, and a JTE mask for forming the JTE region 14 is formed on the oxide film. A p-type impurity, for example, aluminum is ion-implanted from one side in the thickness direction of the JTE mask to selectively ion-implant the p-type impurity into a predetermined region of the SiC epitaxial layer 12, thereby forming the JTE region 14.

 JTE用領域14は、イオン注入領域13と同様に、たとえば、注入量が1×1017cm-3~1×1018cm-3となり、注入深さが0.5μm~1.0μmとなるように、室温たとえば25℃で、注入角度を0°として、40keV~700keVのエネルギーでp型不純物イオン、たとえばアルミニウムイオンを注入することによって形成される。 Similar to the ion implantation region 13, the JTE region 14 has, for example, an implantation amount of 1 × 10 17 cm −3 to 1 × 10 18 cm −3 and an implantation depth of 0.5 μm to 1.0 μm. Further, it is formed by implanting p-type impurity ions such as aluminum ions at an energy of 40 keV to 700 keV at a room temperature of 25 ° C. and an implantation angle of 0 °.

 JTE用マスクおよび酸化膜を除去した後、注入したアルミニウムイオンなどのp型不純物イオンを活性化させるために、熱処理を行う。具体的には、アルゴン雰囲気中で、1500℃~2000℃の温度で、1分~30分間熱処理を行う。この熱処理工程によって、注入されたイオンが活性化されて、p型終端構造が形成される。 After removing the JTE mask and the oxide film, heat treatment is performed in order to activate p-type impurity ions such as implanted aluminum ions. Specifically, heat treatment is performed in an argon atmosphere at a temperature of 1500 ° C. to 2000 ° C. for 1 minute to 30 minutes. By this heat treatment step, the implanted ions are activated and a p-type termination structure is formed.

 次に、イオン注入領域13に囲まれたショットキ領域18に、ショットキ電極15を、その周縁部がイオン注入領域13にはみ出すように形成する。ショットキ電極15の材料としては、チタン(Ti)、タングステン(W)、モリブデン(Mo)およびクロム(Cr)などが挙げられる。これらの材料から選ばれる1種または2種以上によってショットキ電極15が形成される。次に、ショットキ電極15の厚み方向一方側の表面上に、配線電極16を形成する。配線電極16の材料としては、Alなどが挙げられる。 Next, the Schottky electrode 15 is formed in the Schottky region 18 surrounded by the ion implantation region 13 so that the peripheral portion protrudes from the ion implantation region 13. Examples of the material of the Schottky electrode 15 include titanium (Ti), tungsten (W), molybdenum (Mo), and chromium (Cr). The Schottky electrode 15 is formed of one or more selected from these materials. Next, the wiring electrode 16 is formed on the surface on one side in the thickness direction of the Schottky electrode 15. Examples of the material of the wiring electrode 16 include Al.

 以上のようにして、表面加工工程において、SiC基板11の表面、すなわちSiC基板11の厚み方向一方側の表面に、図1に示すイオン注入領域13およびJTE領域14を含むSiCエピタキシャル層12と、ショットキ電極15と、配線電極16とを含むデバイス部を形成する。後述する図3~図5では、デバイス部を、参照符号「20」を付して、「デバイス部20」として示している。 As described above, in the surface processing step, the SiC epitaxial layer 12 including the ion implantation region 13 and the JTE region 14 shown in FIG. 1 on the surface of the SiC substrate 11, that is, the surface on one side in the thickness direction of the SiC substrate 11, A device portion including the Schottky electrode 15 and the wiring electrode 16 is formed. In FIG. 3 to FIG. 5 to be described later, the device portion is indicated as “device portion 20” with reference numeral “20”.

 以上のようにしてSiC基板11の表面にデバイス部を形成すると、裏面加工工程に移行する。本実施の形態では、裏面加工工程は、シリサイド層形成工程である。シリサイド層形成工程では、SiC基板11の裏面、すなわちSiC基板11の厚み方向他方側の表面に、オーミック電極であるシリサイド層17を形成する。シリサイド層形成工程は、具体的には、以下のようにして行われる。 When the device part is formed on the surface of the SiC substrate 11 as described above, the process proceeds to the back surface processing step. In the present embodiment, the back surface processing step is a silicide layer forming step. In the silicide layer forming step, a silicide layer 17 that is an ohmic electrode is formed on the back surface of the SiC substrate 11, that is, the surface on the other side in the thickness direction of the SiC substrate 11. Specifically, the silicide layer forming step is performed as follows.

 図2は、本発明の第1の実施の形態の半導体装置の製造方法におけるシリサイド層形成工程の手順を示すフローチャートである。図2に示すように、シリサイド層形成工程は、ステップa1のナノ薄膜形成工程と、ステップa2の電極形成工程とを備える。前述のようにしてデバイス部を形成すると、図2に示すフローチャートの処理が開始され、ステップa1のナノ薄膜形成工程に移行する。ナノ薄膜形成工程は、ステップa11の塗布段階と、ステップa12の焼結段階とを備える。 FIG. 2 is a flowchart showing a procedure of a silicide layer forming step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 2, the silicide layer forming step includes a nano thin film forming step in step a1 and an electrode forming step in step a2. When the device portion is formed as described above, the processing of the flowchart shown in FIG. 2 is started, and the process proceeds to the nano thin film forming step of step a1. The nano thin film forming step includes a coating step of step a11 and a sintering step of step a12.

 図3~図5は、シリサイド層形成工程を説明するための図である。図3~図5では、前述の図1に示すイオン注入領域13およびJTE領域14を含むSiCエピタキシャル層12、ショットキ電極15、ならびに配線電極16をまとめて、デバイス部20として示している。 3 to 5 are diagrams for explaining the silicide layer forming step. 3 to 5, the SiC epitaxial layer 12, the Schottky electrode 15, and the wiring electrode 16 including the ion implantation region 13 and the JTE region 14 shown in FIG.

 図3は、ナノ粒子薄膜22を形成した状態を示す断面図である。図2のステップa1のナノ薄膜形成工程では、図3に示すように、ナノ粒子薄膜22を形成する。具体的には、まず、ステップa11の塗布段階において、SiC基板11の厚み方向の一表面である厚み方向他方側の表面に、金属ナノ粒子21を含む溶媒(以下「ナノ粒子塗布液」という場合がある)を塗布する。ナノ粒子塗布液は、たとえばスピンコートによって塗布される。本実施の形態では、金属ナノ粒子21として、ニッケルナノ粒子を用いる。本実施の形態では、金属ナノ粒子21の粒径は、1nm以上100nm以下である。ナノ粒子塗布液を塗布すると、図2のステップa12の焼結段階に移行する。 FIG. 3 is a cross-sectional view showing a state in which the nanoparticle thin film 22 has been formed. In the nano thin film forming step of step a1 in FIG. 2, the nano particle thin film 22 is formed as shown in FIG. Specifically, first, in the coating step of step a11, a solvent containing metal nanoparticles 21 (hereinafter referred to as “nanoparticle coating liquid”) is formed on the surface on the other side in the thickness direction, which is one surface in the thickness direction of the SiC substrate 11. Apply). The nanoparticle coating liquid is applied by spin coating, for example. In the present embodiment, nickel nanoparticles are used as the metal nanoparticles 21. In the present embodiment, the metal nanoparticles 21 have a particle size of 1 nm to 100 nm. When the nanoparticle coating liquid is applied, the process proceeds to the sintering step of step a12 in FIG.

 ステップa12の焼結段階では、塗布したナノ粒子塗布液を100℃~300℃程度の温度で熱処理することによって、ナノ粒子塗布液中の金属ナノ粒子21を焼結させる。すなわち、塗布した金属ナノ粒子21を、溶媒とともに100℃~300℃程度の温度で熱処理することによって、焼結させる。これによって、金属ナノ粒子21から成る金属薄膜であるナノ粒子薄膜22を形成する。ナノ粒子薄膜22は、コンタクト電極となるコンタクト電極膜である。本実施の形態では、焼結後のナノ粒子薄膜22の膜厚は、10nm以上500nm以下である。 In the sintering step of step a12, the applied nanoparticle coating solution is heat-treated at a temperature of about 100 ° C. to 300 ° C. to sinter the metal nanoparticles 21 in the nanoparticle coating solution. That is, the coated metal nanoparticles 21 are sintered by heat treatment with a solvent at a temperature of about 100 ° C. to 300 ° C. Thus, a nanoparticle thin film 22 that is a metal thin film made of the metal nanoparticles 21 is formed. The nanoparticle thin film 22 is a contact electrode film serving as a contact electrode. In this Embodiment, the film thickness of the nanoparticle thin film 22 after sintering is 10 nm or more and 500 nm or less.

 以上のようにして、金属ナノ粒子21によって、金属薄膜であるナノ粒子薄膜22を形成する。これによって、たとえば蒸着などの他の方法によって金属薄膜を形成する場合に比べて、金属薄膜の反射率を低くすることができる。ナノ粒子薄膜22を形成すると、図2のステップa2の電極形成工程に移行する。 As described above, the nanoparticle thin film 22, which is a metal thin film, is formed from the metal nanoparticles 21. Thereby, the reflectance of a metal thin film can be made low compared with the case where a metal thin film is formed by other methods, such as vapor deposition, for example. When the nanoparticle thin film 22 is formed, the process proceeds to the electrode formation process of step a2 in FIG.

 図4は、ナノ粒子薄膜22にレーザ光を照射する様子を示す断面図である。図5は、シリサイド層17の形成が終了した段階の状態を示す断面図である。以上のようにしてナノ粒子薄膜22を形成した後、図2のステップa2の電極形成工程を行う。電極形成工程では、まず、図4に示すように、ナノ粒子薄膜22に、オーミックコンタクトの形成に必要なエネルギー密度でレーザ光を照射することによって、レーザ光によるアニール処理(以下「レーザアニール処理」という場合がある)を行う。 FIG. 4 is a cross-sectional view showing a state in which the nanoparticle thin film 22 is irradiated with laser light. FIG. 5 is a cross-sectional view showing a state in which the formation of the silicide layer 17 has been completed. After the nanoparticle thin film 22 is formed as described above, the electrode formation step of step a2 in FIG. 2 is performed. In the electrode forming step, first, as shown in FIG. 4, the nanoparticle thin film 22 is irradiated with a laser beam at an energy density necessary for forming an ohmic contact, whereby an annealing process using a laser beam (hereinafter referred to as “laser annealing process”). Sometimes).

 ナノ粒子薄膜22に照射するレーザ光は、ナノ粒子薄膜22が吸収する波長のものであればよい。本実施の形態のようにナノ粒子薄膜22が、ニッケル(Ni)ナノ粒子によるNi薄膜である場合には、レーザ光として、たとえば、以下の(A)~(G)のいずれか1種または2種以上を用いることができる。 The laser beam applied to the nanoparticle thin film 22 only needs to have a wavelength that is absorbed by the nanoparticle thin film 22. When the nanoparticle thin film 22 is a Ni thin film made of nickel (Ni) nanoparticles as in the present embodiment, for example, any one or two of the following (A) to (G) are used as the laser light: More than seeds can be used.

 (A)YAGレーザ素子の波長が1064nmであるレーザ光。
 (B)YLFレーザ素子のレーザ光。
 (C)YVOレーザ素子のレーザ光のうち、(a)波長が1064nmである基本波、(b)波長が532nmである2倍波、(c)波長が355nmである3倍波、(d)波長が266nmである4倍波。
 (D)ArFエキシマレーザ素子の波長が193nmであるレーザ光。
 (E)KrFエキシマレーザ素子の波長が248nmであるレーザ光。
 (F)XeClエキシマレーザ素子の波長が308nmであるレーザ光。
 (G)XeFエキシマレーザ素子の波長が351nmであるレーザ光。
(A) Laser light whose wavelength of the YAG laser element is 1064 nm.
(B) Laser light from a YLF laser element.
(C) Of the laser light from the YVO 4 laser element, (a) a fundamental wave with a wavelength of 1064 nm, (b) a second harmonic with a wavelength of 532 nm, (c) a third harmonic with a wavelength of 355 nm, (d ) Quadruple wave with a wavelength of 266 nm.
(D) Laser light whose wavelength of the ArF excimer laser element is 193 nm.
(E) A laser beam having a wavelength of 248 nm of a KrF excimer laser element.
(F) A laser beam having a XeCl excimer laser element with a wavelength of 308 nm.
(G) A laser beam whose wavelength of the XeF excimer laser element is 351 nm.

 レーザ光としては、前記(A)~(G)以外の各種半導体レーザ素子のレーザ光を用いることもできる。これらのレーザ光の中でも、400nm以下の波長のレーザ光を用いることが望ましい。この理由について、以下に説明する。 As the laser light, laser light of various semiconductor laser elements other than the above (A) to (G) can be used. Among these laser beams, it is desirable to use a laser beam having a wavelength of 400 nm or less. The reason for this will be described below.

 たとえば、ナノ粒子薄膜22に、後述する図9に示すピンホール42などの膜欠陥がある場合、またはナノ粒子薄膜22の膜厚が所望の膜厚よりも薄くなってしまうようなプロセスエラーが発生した場合、照射されたレーザ光は、ナノ粒子薄膜22で吸収されず、SiC基板11に侵入する。このとき、照射されたレーザ光の波長が、SiC基板11を構成する炭化珪素に吸収されない波長であると、照射されたレーザ光は、SiC基板11を透過する。 For example, when the nanoparticle thin film 22 has a film defect such as a pinhole 42 shown in FIG. 9 to be described later, or a process error that causes the nanoparticle thin film 22 to be thinner than a desired film thickness occurs. In this case, the irradiated laser light is not absorbed by the nanoparticle thin film 22 and enters the SiC substrate 11. At this time, if the wavelength of the irradiated laser light is a wavelength that is not absorbed by silicon carbide constituting the SiC substrate 11, the irradiated laser light passes through the SiC substrate 11.

 SiC基板11を透過したレーザ光は、SiC基板11のレーザ光が照射されない面であるレーザ光非照射面、具体的にはSiC基板11の厚み方向一方側の表面に到達する。レーザ光非照射面に到達したレーザ光は、レーザ光非照射面に形成されているショットキ電極15および配線電極16に吸収される。これによって、デバイス部20が破壊されてしまう。デバイス部20の破壊を避けるために、レーザ光としては、炭化珪素に吸収される波長のレーザ光を用いることが望ましく、具体的には、前述のように400nm以下の波長のレーザ光を用いることが望ましい。 The laser beam that has passed through the SiC substrate 11 reaches the non-irradiated surface of the SiC substrate 11 that is not irradiated with the laser beam, specifically, the surface on one side in the thickness direction of the SiC substrate 11. The laser light reaching the laser light non-irradiated surface is absorbed by the Schottky electrode 15 and the wiring electrode 16 formed on the laser light non-irradiated surface. As a result, the device unit 20 is destroyed. In order to avoid destruction of the device unit 20, it is desirable to use a laser beam having a wavelength absorbed by silicon carbide as the laser beam. Specifically, as described above, a laser beam having a wavelength of 400 nm or less is used. Is desirable.

 また、レーザ光の照射時には、ニッケル薄膜などのナノ粒子薄膜22でレーザ光が吸収されることによって発生した熱が、TiおよびAlなどが配置されたデバイス部20に伝わって、デバイス部20が高温になってしまうことがある。デバイス部20が高温になってしまうと、Alの融解およびショットキ界面の劣化などが発生してしまう。 Further, at the time of laser light irradiation, heat generated by the laser light being absorbed by the nanoparticle thin film 22 such as a nickel thin film is transmitted to the device unit 20 in which Ti, Al, and the like are arranged, and the device unit 20 is heated to a high temperature. It may become. When the device unit 20 becomes high temperature, melting of Al, deterioration of the Schottky interface, and the like occur.

 デバイス部20への熱伝導を防ぐためには、たとえば1ns~1000ns程度と短いパルスで、たとえば1kHz~1000kHz程度と低い繰り返し周波数で、レーザ光を照射することが有効である。具体的には、パルス幅が1ns~1000nsであり、繰り返し周波数が1kHz~1000kHzであるパルスレーザ光をスキャンさせて照射することが好ましい。 In order to prevent heat conduction to the device unit 20, it is effective to irradiate the laser beam with a pulse as short as about 1 ns to 1000 ns, for example, with a repetition frequency as low as about 1 kHz to 1000 kHz. Specifically, it is preferable to scan and irradiate pulsed laser light having a pulse width of 1 ns to 1000 ns and a repetition frequency of 1 kHz to 1000 kHz.

 ナノ粒子薄膜22を構成する金属、本実施の形態ではニッケル(Ni)が自然酸化されることを防ぐために、ナノ粒子薄膜22を形成した後は、速やかにレーザアニール処理を行うことが好ましい。レーザアニール処理におけるレーザ光の照射は、電極となるナノ粒子薄膜22の酸化を防ぐために、アルゴンまたは窒素などの不活性ガス雰囲気で行うことが好ましい。 In order to prevent spontaneous oxidation of the metal constituting the nanoparticle thin film 22, in this embodiment, nickel (Ni), it is preferable to perform laser annealing immediately after the nanoparticle thin film 22 is formed. The laser beam irradiation in the laser annealing treatment is preferably performed in an inert gas atmosphere such as argon or nitrogen in order to prevent oxidation of the nanoparticle thin film 22 serving as an electrode.

 レーザアニール処理を行うことによって、ナノ粒子薄膜22を構成する金属とSiCとの反応層、本実施の形態ではNiとSiCとの反応層として、シリサイド層17が形成される。これによって、反応層であるシリサイド層17から成るオーミック電極と、SiC層であるSiC基板11との間で、低抵抗のオーミックコンタクトが得られる。このようにしてレーザ光を照射してオーミック電極を形成する工程は、電極形成工程に相当する。 By performing the laser annealing treatment, the silicide layer 17 is formed as a reaction layer of metal and SiC constituting the nanoparticle thin film 22, in this embodiment as a reaction layer of Ni and SiC. Thereby, a low-resistance ohmic contact is obtained between the ohmic electrode formed of the silicide layer 17 as the reaction layer and the SiC substrate 11 as the SiC layer. Thus, the process of irradiating a laser beam and forming an ohmic electrode is equivalent to an electrode formation process.

 以上のように本実施の形態によれば、ナノ薄膜形成工程において、SiC基板11の厚み方向の他方側の表面上に、金属ナノ粒子21によって、金属薄膜であるナノ粒子薄膜22が形成される。このナノ薄膜形成工程で形成された金属薄膜であるナノ粒子薄膜22に、電極形成工程においてレーザ光が照射されることによって、オーミック電極が形成される。 As described above, according to the present embodiment, nanoparticle thin film 22 that is a metal thin film is formed by metal nanoparticles 21 on the surface of the other side in the thickness direction of SiC substrate 11 in the nanothin film formation step. . An ohmic electrode is formed by irradiating the nanoparticle thin film 22 which is a metal thin film formed in the nano thin film forming process with laser light in the electrode forming process.

 金属ナノ粒子21は、粒径を制御することができる。金属ナノ粒子21の粒径を制御することによって、金属薄膜であるナノ粒子薄膜22に凹凸を形成することができるので、金属薄膜の反射率を低下させることができる。また金属ナノ粒子21で金属薄膜を形成することによって、表面プラズモンを共鳴的に励起することができる。このように表面プラズモンが励起可能な状況では、照射されたレーザ光のエネルギーが表面プラズモンの励起によって奪われるので、金属薄膜の反射率が低下する。したがって、前述のように金属ナノ粒子21によって、金属薄膜としてナノ粒子薄膜22を形成することによって、金属薄膜の反射率を低下させることができる。 The metal nanoparticles 21 can control the particle size. By controlling the particle size of the metal nanoparticles 21, irregularities can be formed in the nanoparticle thin film 22 which is a metal thin film, and thus the reflectance of the metal thin film can be reduced. Further, by forming a metal thin film with the metal nanoparticles 21, surface plasmons can be excited resonantly. In such a situation where surface plasmons can be excited, the energy of the irradiated laser light is deprived by the excitation of the surface plasmons, so that the reflectance of the metal thin film is lowered. Therefore, the reflectance of a metal thin film can be reduced by forming the nanoparticle thin film 22 as a metal thin film with the metal nanoparticles 21 as described above.

 このように本実施の形態では、従来技術とは異なり、SiC基板11に研磨加工を施すことなく、金属薄膜の反射率を低下させることができる。このようにして反射率が低下された金属薄膜であるナノ粒子薄膜22に、電極形成工程でレーザ光を照射するので、照射されたレーザ光のうち、金属薄膜中に侵入して吸収されて熱エネルギーに変わる割合を大きくすることができる。これによって、低抵抗のオーミック電極の形成に必要なレーザ光のエネルギー密度を低減することができる。 Thus, in the present embodiment, unlike the conventional technique, the reflectance of the metal thin film can be reduced without polishing the SiC substrate 11. Since the nanoparticle thin film 22, which is a metal thin film having a reduced reflectance in this way, is irradiated with laser light in the electrode forming step, the laser light enters the metal thin film and is absorbed and absorbed. The rate of change to energy can be increased. As a result, the energy density of laser light necessary for forming a low-resistance ohmic electrode can be reduced.

 すなわち、本実施の形態によれば、金属ナノ粒子21によって金属薄膜であるナノ粒子薄膜22を形成することによって、低抵抗のオーミック電極の形成に必要なレーザ光のエネルギー密度を、スパッタ、蒸着などの他の方法で金属薄膜を形成する場合に比べて低減することができる。これによって、レーザ光の照射に要する処理時間を短縮することができる。 That is, according to the present embodiment, by forming the nanoparticle thin film 22 that is a metal thin film from the metal nanoparticles 21, the energy density of the laser light necessary for the formation of the low-resistance ohmic electrode can be increased by sputtering, vapor deposition, or the like. It can reduce compared with the case where a metal thin film is formed by other methods. Thereby, the processing time required for laser beam irradiation can be shortened.

 また本実施の形態では、SiC基板11には研磨加工が施されないので、本実施の形態の方法によって形成されたオーミック電極は、SiC基板11との界面に加工歪層を有さず、SiC基板11の反りが増加することがない。換言すれば、研磨加工によるSiC基板11への加工歪層の発生を防いで、SiC基板11の反りの増加を防ぐことができる。つまり、本実施の形態では、SiC基板11の反りを増加させることなく、金属薄膜の表面の反射率を低下させて、低抵抗のオーミック電極の形成に必要なレーザ光のエネルギー密度を小さくすることができる。 In this embodiment, since the SiC substrate 11 is not polished, the ohmic electrode formed by the method of this embodiment does not have a processing strain layer at the interface with the SiC substrate 11, and the SiC substrate 11 warpage does not increase. In other words, it is possible to prevent an occurrence of a processing strain layer on the SiC substrate 11 due to the polishing process and to prevent an increase in warpage of the SiC substrate 11. That is, in the present embodiment, the energy density of the laser light necessary for forming the low-resistance ohmic electrode is reduced by reducing the reflectivity of the surface of the metal thin film without increasing the warp of the SiC substrate 11. Can do.

 具体的には、SiC基板11として、円板状のウエハを用いて、ウエハの厚みをtμmとするとき、ウエハの直径が3インチの場合には、SiC基板11の反りを、100×(200/t)μm以下にすることができる。またウエハの直径が4インチの場合には、SiC基板11の反りを、250×(200/t)μm以下にすることができる。 Specifically, when a disc-shaped wafer is used as the SiC substrate 11 and the wafer thickness is t μm, and the wafer diameter is 3 inches, the warp of the SiC substrate 11 is 100 × (200 / T) Can be 2 μm or less. When the wafer diameter is 4 inches, the warp of the SiC substrate 11 can be reduced to 250 × (200 / t) 2 μm or less.

 このようにSiC基板11の反りの増加が抑えられることによって、SiC基板11の反りによる半導体装置100の信頼性の低下を防ぐことができる。また前述のようにSiC基板11に加工歪層が形成されないようにすることによって、加工歪層による悪影響を抑えて、半導体装置100の信頼性が損なわれることを防ぐことができる。 Thus, by suppressing the increase in the warp of the SiC substrate 11, it is possible to prevent a decrease in the reliability of the semiconductor device 100 due to the warp of the SiC substrate 11. Further, by preventing the processing strain layer from being formed on the SiC substrate 11 as described above, the adverse effect of the processing strain layer can be suppressed and the reliability of the semiconductor device 100 can be prevented from being impaired.

 したがって、本実施の形態では、半導体装置100の信頼性を損なうことなく、可及的に小さいエネルギー密度のレーザ光の照射によって、低抵抗のオーミック電極を形成することができる。 Therefore, in this embodiment, a low-resistance ohmic electrode can be formed by irradiating laser light with as low energy density as possible without impairing the reliability of the semiconductor device 100.

 以上に述べた本実施の形態では、ナノ粒子薄膜22を構成する金属ナノ粒子21の材料として、ニッケル(Ni)を用いているが、これに限定されず、チタン(Ti)、コバルト(Co)、モリブデン(Mo)、タングステン(W)などを用いてもよい。これらの材料を用いても、Niを用いる場合と同様の効果を得ることができる。 In the present embodiment described above, nickel (Ni) is used as the material of the metal nanoparticles 21 constituting the nanoparticle thin film 22. However, the present invention is not limited to this, and titanium (Ti), cobalt (Co). Molybdenum (Mo), tungsten (W), or the like may be used. Even if these materials are used, the same effect as the case of using Ni can be obtained.

 すなわち、金属ナノ粒子21の材料は、ニッケル(Ni)、チタン(Ti)、コバルト(Co)、モリブデン(Mo)およびタングステン(W)から選ばれる1種または2種以上を含むことが好ましい。このような材料を用いることによって、他の材料を用いる場合に比べて、より低抵抗のオーミック電極として、シリサイド層17を形成することができる。 That is, the material of the metal nanoparticles 21 preferably contains one or more selected from nickel (Ni), titanium (Ti), cobalt (Co), molybdenum (Mo), and tungsten (W). By using such a material, the silicide layer 17 can be formed as an ohmic electrode having a lower resistance than in the case of using another material.

 本実施の形態では、金属ナノ粒子21の粒径は、1nm以上100nm以下である。金属ナノ粒子21の粒径は、これに限定されないが、本実施の形態のように1nm以上100nm以下であることが好ましい。金属ナノ粒子21の粒径が1nm未満であると、金属薄膜であるナノ粒子薄膜22に形成される凹凸が小さいので、金属薄膜の反射率を低下させる効果が充分に得られないおそれがある。金属ナノ粒子21の粒径が100nmを超えると、焼結後のナノ粒子薄膜22が均質になりにくく、レーザ光の照射後に得られるシリサイド層17も均質になりにくいので、均質なオーミック電極が得られないおそれがある。したがって、金属ナノ粒子21の粒径は、1nm以上100nm以下であることが好ましい。 In the present embodiment, the metal nanoparticles 21 have a particle size of 1 nm to 100 nm. Although the particle diameter of the metal nanoparticle 21 is not limited to this, it is preferable that it is 1 nm or more and 100 nm or less like this Embodiment. If the particle size of the metal nanoparticles 21 is less than 1 nm, the unevenness formed on the nanoparticle thin film 22 that is a metal thin film is small, and thus the effect of reducing the reflectance of the metal thin film may not be sufficiently obtained. When the particle diameter of the metal nanoparticles 21 exceeds 100 nm, the sintered nanoparticle thin film 22 is difficult to be homogeneous, and the silicide layer 17 obtained after the laser light irradiation is also difficult to be uniform, so that a homogeneous ohmic electrode is obtained. There is a risk of not being able to. Therefore, the particle size of the metal nanoparticles 21 is preferably 1 nm or more and 100 nm or less.

 金属ナノ粒子21の粒径は、照射するレーザ光の波長をλとし、その波長λでの金属ナノ粒子21の屈折率をnとしたとき、λ/4nであることが特に好ましい。金属ナノ粒子21の粒径をλ/4nとすることによって、形成されるナノ粒子薄膜22の反射率を充分に抑制することができる。 The particle diameter of the metal nanoparticles 21 is particularly preferably λ / 4n, where λ is the wavelength of the laser beam to be irradiated and n is the refractive index of the metal nanoparticles 21 at the wavelength λ. By setting the particle diameter of the metal nanoparticles 21 to λ / 4n, the reflectance of the formed nanoparticle thin film 22 can be sufficiently suppressed.

 たとえば、金属ナノ粒子21としてニッケル(Ni)ナノ粒子を用いて、波長λが355nmのレーザ光をNiナノ粒子に照射する場合、このレーザ光の波長355nmに対するNiの屈折率nは1.63であり、λ/4n=355nm/(4×1.63)=54.44…nmである。したがって、Niナノ粒子の粒径は、54.4nmにするとよい。 For example, when nickel (Ni) nanoparticles are used as the metal nanoparticles 21 and the Ni nanoparticles are irradiated with laser light having a wavelength λ of 355 nm, the refractive index n of Ni with respect to the wavelength 355 nm of the laser light is 1.63. Yes, λ / 4n = 355 nm / (4 × 1.63) = 54.44. Therefore, the particle size of the Ni nanoparticles is preferably 54.4 nm.

 またナノ粒子薄膜22の膜厚、具体的には、塗布した金属ナノ粒子21の焼結後のナノ粒子薄膜22の膜厚は、本実施の形態では、10nm以上500nm以下である。ナノ粒子薄膜22の膜厚は、これに限定されないが、本実施の形態のように10nm以上500nm以下であることが好ましい。 The film thickness of the nanoparticle thin film 22, specifically, the film thickness of the nanoparticle thin film 22 after sintering of the applied metal nanoparticles 21 is 10 nm or more and 500 nm or less in the present embodiment. Although the film thickness of the nanoparticle thin film 22 is not limited to this, it is preferable that it is 10 nm or more and 500 nm or less like this Embodiment.

 ナノ粒子薄膜22の膜厚が10nm未満であると、レーザ光の照射後に得られるシリサイド層17が均質になりにくく、均質なオーミック電極が得られないおそれがある。ナノ粒子薄膜22の膜厚が500nmを超えると、照射されたレーザ光が、ナノ粒子薄膜22とSiC基板11との界面まで到達できないおそれがある。照射されたレーザ光が、ナノ粒子薄膜22とSiC基板11との界面まで到達できないと、ナノ粒子薄膜22を構成する金属と、SiC基板11を構成するSiCとの反応が進行せず、シリサイド層17が形成されず、低抵抗のオーミック電極が得られないおそれがある。したがって、ナノ粒子薄膜22の膜厚は、10nm以上500nm以下であることが好ましい。 If the film thickness of the nanoparticle thin film 22 is less than 10 nm, the silicide layer 17 obtained after the laser light irradiation is difficult to be uniform, and a uniform ohmic electrode may not be obtained. If the film thickness of the nanoparticle thin film 22 exceeds 500 nm, the irradiated laser light may not reach the interface between the nanoparticle thin film 22 and the SiC substrate 11. If the irradiated laser light cannot reach the interface between the nanoparticle thin film 22 and the SiC substrate 11, the reaction between the metal constituting the nanoparticle thin film 22 and SiC constituting the SiC substrate 11 does not proceed, and the silicide layer 17 may not be formed, and a low-resistance ohmic electrode may not be obtained. Therefore, the film thickness of the nanoparticle thin film 22 is preferably 10 nm or more and 500 nm or less.

 また本実施の形態では、ナノ粒子薄膜22は、図2のステップa11の塗布段階で、SiC基板11の厚み方向他方側の表面上に、金属ナノ粒子21を含む溶媒を塗布し、塗布した金属ナノ粒子21を焼結段階で焼結することによって形成される。このようにすることによって、金属ナノ粒子21による金属薄膜であるナノ粒子薄膜22を容易に形成することができる。 In the present embodiment, the nanoparticle thin film 22 is formed by applying a solvent containing the metal nanoparticles 21 on the surface of the other side in the thickness direction of the SiC substrate 11 at the application stage of step a11 in FIG. It is formed by sintering the nanoparticles 21 in the sintering step. By doing in this way, the nanoparticle thin film 22 which is a metal thin film by the metal nanoparticle 21 can be formed easily.

 <第2の実施の形態>
 次に、本発明の第2の実施の形態の半導体装置の製造方法について説明する。本実施の形態の半導体装置の製造方法によって製造される半導体装置の構成は、SiC基板11の厚みが異なること以外は、前述の図1に示す第1の実施の形態の半導体装置100と同一であるので、対応する部分には同一の参照符を付して、図示および説明を省略する。
<Second Embodiment>
Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described. The configuration of the semiconductor device manufactured by the manufacturing method of the semiconductor device of the present embodiment is the same as that of the semiconductor device 100 of the first embodiment shown in FIG. 1 described above except that the thickness of the SiC substrate 11 is different. Accordingly, corresponding parts are denoted by the same reference numerals, and illustration and description thereof are omitted.

 図1に示す半導体装置100では、半導体素子1の動作時にキャリアがSiC基板11を通過して、図1の紙面に向かって縦方向、具体的にはSiC基板11の厚み方向に走行する。したがって、電流経路であるSiC基板11の厚みを薄くすることによって、半導体素子1の抵抗を低減することができる。本実施の形態では、半導体素子1の抵抗を低減するために、SiC基板11の厚みを薄くする場合の半導体装置の製造方法について説明する。本実施の形態においても、半導体素子1は、SiCショットキバリアダイオード(SBD)である。 In the semiconductor device 100 shown in FIG. 1, when the semiconductor element 1 operates, the carrier passes through the SiC substrate 11 and travels in the vertical direction toward the paper surface of FIG. 1, specifically, in the thickness direction of the SiC substrate 11. Therefore, the resistance of the semiconductor element 1 can be reduced by reducing the thickness of the SiC substrate 11 serving as a current path. In the present embodiment, a method for manufacturing a semiconductor device when the thickness of SiC substrate 11 is reduced in order to reduce the resistance of semiconductor element 1 will be described. Also in the present embodiment, the semiconductor element 1 is a SiC Schottky barrier diode (SBD).

 本実施の形態の半導体装置の製造方法は、裏面加工工程の前までは、第1の実施の形態と同じである。具体的には、はじめに、準備工程において、SiC基板11などの半導体装置100の製造に必要な材料および装置を準備する。SiC基板11としては、n型のSiC基板11を準備する。SiC基板11などの半導体装置100の製造に必要な材料および装置を準備すると、表面加工工程に移行する。 The manufacturing method of the semiconductor device of the present embodiment is the same as that of the first embodiment until the back surface processing step. Specifically, first, in the preparation step, materials and devices necessary for manufacturing the semiconductor device 100 such as the SiC substrate 11 are prepared. As the SiC substrate 11, an n-type SiC substrate 11 is prepared. When materials and apparatuses necessary for manufacturing the semiconductor device 100 such as the SiC substrate 11 are prepared, the process proceeds to a surface processing step.

 表面加工工程では、まず、SiC基板11の表面上に、SiCエピタキシャル層12を成長させる。SiCエピタキシャル層12におけるn型不純物のドーピング濃度は、たとえば5×1015個cm-3~5×1016個cm-3である。SiCエピタキシャル層12の膜厚は、たとえば5μm~15μmである。SiCエピタキシャル層12の厚み方向一方側の表面上に、犠牲酸化によって、酸化膜を形成する。 In the surface processing step, first, the SiC epitaxial layer 12 is grown on the surface of the SiC substrate 11. The doping concentration of the n-type impurity in SiC epitaxial layer 12 is, for example, 5 × 10 15 cm −3 to 5 × 10 16 cm −3 . The film thickness of SiC epitaxial layer 12 is, for example, 5 μm to 15 μm. An oxide film is formed on the surface of one side in the thickness direction of SiC epitaxial layer 12 by sacrificial oxidation.

 次に、p型終端構造を形成する処理を行う。具体的には、まず、SiCエピタキシャル層12の厚み方向一方側の表面上に形成した酸化膜上に、イオン注入マスクを形成する。このイオン注入マスクの厚み方向一方側から、p型不純物、たとえばアルミニウムをイオン注入することによって、p型不純物をSiCエピタキシャル層12の予め定める領域に選択的にイオン注入し、イオン注入領域13を形成する。イオン注入領域13は、たとえば、注入量が1×1016cm-3~1×1018cm-3となり、注入深さが0.5μm~1.0μmとなるように、室温たとえば25℃で、注入角度を0°として、40keV~700keVのエネルギーでp型不純物イオン、たとえばアルミニウムイオンを注入することによって形成される。 Next, a process for forming a p-type termination structure is performed. Specifically, first, an ion implantation mask is formed on the oxide film formed on the surface on one side in the thickness direction of SiC epitaxial layer 12. A p-type impurity, for example, aluminum is ion-implanted from one side in the thickness direction of the ion implantation mask to selectively ion-implant the p-type impurity into a predetermined region of the SiC epitaxial layer 12 to form an ion implantation region 13. To do. The ion implantation region 13 has, for example, an implantation amount of 1 × 10 16 cm −3 to 1 × 10 18 cm −3 and an implantation depth of 0.5 μm to 1.0 μm at room temperature, for example, 25 ° C. It is formed by implanting p-type impurity ions such as aluminum ions at an energy of 40 keV to 700 keV with an implantation angle of 0 °.

 次に、イオン注入マスクを除去し、第1の実施の形態と同様にしてJTE領域14を形成し、JTE領域14の形成に用いたJTE用マスクと酸化膜とを除去する。その後、注入したアルミニウムイオンなどのp型不純物イオンを活性化させるために、たとえばアルゴン雰囲気中で、1500℃~2000℃の温度で、1分~30分間熱処理を行う。この熱処理工程によって、注入されたイオンが活性化されて、p型終端構造が形成される。 Next, the ion implantation mask is removed, the JTE region 14 is formed in the same manner as in the first embodiment, and the JTE mask and the oxide film used for forming the JTE region 14 are removed. Thereafter, in order to activate p-type impurity ions such as implanted aluminum ions, heat treatment is performed at a temperature of 1500 ° C. to 2000 ° C. for 1 minute to 30 minutes, for example, in an argon atmosphere. By this heat treatment step, the implanted ions are activated and a p-type termination structure is formed.

 次に、イオン注入領域13に囲まれたショットキ領域18に、ショットキ電極15を、その周縁部がイオン注入領域13にはみ出すように形成する。ショットキ電極15の材料としては、チタン(Ti)、タングステン(W)、モリブデン(Mo)およびクロム(Cr)などが挙げられる。次に、ショットキ電極15の厚み方向一方側の表面上に、配線電極16を形成する。配線電極16の材料としては、Alなどが挙げられる。以上のようにしてSiC基板11の表面にデバイス部を形成すると、裏面加工工程に移行する。 Next, the Schottky electrode 15 is formed in the Schottky region 18 surrounded by the ion implantation region 13 so that the peripheral portion protrudes from the ion implantation region 13. Examples of the material of the Schottky electrode 15 include titanium (Ti), tungsten (W), molybdenum (Mo), and chromium (Cr). Next, the wiring electrode 16 is formed on the surface of the Schottky electrode 15 on one side in the thickness direction. Examples of the material of the wiring electrode 16 include Al. When the device portion is formed on the surface of SiC substrate 11 as described above, the process proceeds to the back surface processing step.

 図6は、本発明の第2の実施の形態の半導体装置の製造方法における裏面加工工程の手順を示すフローチャートである。本実施の形態では、裏面加工工程は、シリサイド層形成工程の前、具体的にはステップa1のナノ薄膜形成工程の前に、ステップb1の薄板化工程を備える。すなわち、裏面加工工程は、ステップb1の薄板化工程と、ステップa1のナノ薄膜形成工程と、ステップa2の電極形成工程とを備える。ステップa1のナノ薄膜形成工程およびステップa2の電極形成工程は、シリサイド層形成工程を構成する。 FIG. 6 is a flowchart showing the procedure of the back surface processing step in the method for manufacturing a semiconductor device according to the second embodiment of the present invention. In the present embodiment, the back surface processing step includes the thinning step of step b1 before the silicide layer forming step, specifically, before the nano thin film forming step of step a1. That is, the back surface processing process includes a thinning process in step b1, a nano thin film forming process in step a1, and an electrode forming process in step a2. The nano thin film forming process in step a1 and the electrode forming process in step a2 constitute a silicide layer forming process.

 ステップb1の薄板化工程では、SiC基板11を薄板化する。具体的には、SiC基板11の裏面、すなわち厚み方向他方側の表面を研削することによって、SiC基板11の厚み(以下「板厚」という場合がある)を薄くする。たとえば、板厚が400μmのSiC基板11を用いて半導体装置100を作製する場合、SiC基板11の裏面全体を研削することによって、SiC基板11を、板厚が200μm以下になるように薄板化する。 In the thinning process of step b1, the SiC substrate 11 is thinned. Specifically, by grinding the back surface of the SiC substrate 11, that is, the surface on the other side in the thickness direction, the thickness of the SiC substrate 11 (hereinafter sometimes referred to as “plate thickness”) is reduced. For example, when manufacturing semiconductor device 100 using SiC substrate 11 having a plate thickness of 400 μm, SiC substrate 11 is thinned so that the plate thickness becomes 200 μm or less by grinding the entire back surface of SiC substrate 11. .

 この薄板化工程における研削によって、SiC基板11の裏面には、加工歪層が形成される。研削後のSiC基板11に存在する加工歪層を可能な限り少なくするために、仕上げ研削では、SiC基板11の裏面を、JIS B 0601に規定される算術平均粗さRaが10nm以下になるように研削することが好ましい。具体的には、SiC基板11の裏面を、平均砥粒径が20μm以下である1000番以上の目の細かい砥石で研削することによって、SiC基板11の裏面の算術平均粗さRaを10nm以下にすることが好ましい。このように目の細かい砥石で加工表面が平坦になるように研削を行うことによって、加工歪層が形成される深さを浅くすることができるので、SiC基板11の反りを抑制することができる。 A processing strain layer is formed on the back surface of the SiC substrate 11 by grinding in the thinning process. In order to reduce the working strain layer present on the ground SiC substrate 11 as much as possible, in the finish grinding, the back surface of the SiC substrate 11 has an arithmetic average roughness Ra specified in JIS B 0601 of 10 nm or less. It is preferable to grind. Specifically, the arithmetic average roughness Ra of the back surface of the SiC substrate 11 is reduced to 10 nm or less by grinding the back surface of the SiC substrate 11 with a fine grindstone of number 1000 or more having an average abrasive grain size of 20 μm or less. It is preferable to do. By grinding so that the processing surface is flattened with a fine grindstone in this way, the depth at which the processing strain layer is formed can be reduced, so that the warp of the SiC substrate 11 can be suppressed. .

 このように本実施の形態では、ステップa1のナノ薄膜形成工程の前に、ステップb1の薄板化工程を設けて、電流経路であるSiC基板11の厚みを薄くしている。具体的には、SiC基板11を、板厚が200μm以下になるように薄板化している。これによって、半導体素子1の抵抗を低減することができる。 Thus, in the present embodiment, before the nano thin film forming process of step a1, the thinning process of step b1 is provided to reduce the thickness of the SiC substrate 11 serving as a current path. Specifically, the SiC substrate 11 is thinned so that the plate thickness is 200 μm or less. Thereby, the resistance of the semiconductor element 1 can be reduced.

 次に、ステップa2の電極形成工程において、SiC基板11の裏面に、第1の実施の形態と同様にして、オーミック電極であるシリサイド層17を形成する。具体的には、まず、SiC基板11の裏面、すなわち厚み方向他方側の表面に、粒径が1nm以上100nm以下であるニッケルナノ粒子などの金属ナノ粒子21を含む溶媒を塗布、たとえばスピンコートする。 Next, in the electrode formation process of step a2, a silicide layer 17 that is an ohmic electrode is formed on the back surface of the SiC substrate 11 in the same manner as in the first embodiment. Specifically, first, a solvent containing metal nanoparticles 21 such as nickel nanoparticles having a particle size of 1 nm to 100 nm is applied to the back surface of the SiC substrate 11, that is, the surface on the other side in the thickness direction, for example, spin coating. .

 次に、塗布したニッケルナノ粒子などの金属ナノ粒子21を、100℃~300℃程度の温度の熱処理によって焼結させて、金属ナノ粒子21によるナノ粒子薄膜22を形成する。 Next, the coated metal nanoparticles 21 such as nickel nanoparticles are sintered by a heat treatment at a temperature of about 100 ° C. to 300 ° C. to form a nanoparticle thin film 22 made of the metal nanoparticles 21.

 ここで、金属ナノ粒子で形成したナノ粒子薄膜22の厚みが大きいと、ナノ粒子薄膜22にレーザ光を照射してシリサイド化することによって形成される合金層であるシリサイド層17の膜厚も厚くなり、この合金層に生じる応力が増大してしまう。したがって、薄板化したSiC基板11に厚いナノ粒子薄膜22を形成すると、SiC基板11が大きく反ってしまう。最悪の場合、薄板化して強度が低下したSiC基板11が、応力に耐えられず、割れてしまう。 Here, when the thickness of the nanoparticle thin film 22 formed of metal nanoparticles is large, the thickness of the silicide layer 17 which is an alloy layer formed by irradiating the nanoparticle thin film 22 with a laser beam to be silicided is also thick. As a result, the stress generated in the alloy layer increases. Accordingly, when the thick nanoparticle thin film 22 is formed on the thinned SiC substrate 11, the SiC substrate 11 is greatly warped. In the worst case, the SiC substrate 11 that has been thinned and reduced in strength cannot withstand the stress and cracks.

 実際に、100μmまで薄板化した3インチのSiC基板11に、ニッケルナノ粒子によって厚みが300nmのナノ粒子薄膜22を形成してレーザ光を照射すると、合金層であるシリサイド層17の厚みが大きくなり、大きな応力が発生し、それによってSiC基板11が割れてしまった。膜の応力は、その厚みに比例するので、合金層の応力は、成膜するナノ粒子薄膜22の厚みに比例する。 Actually, when the nanoparticle thin film 22 having a thickness of 300 nm is formed by nickel nanoparticles on the 3 inch SiC substrate 11 thinned to 100 μm and irradiated with laser light, the thickness of the silicide layer 17 which is an alloy layer is increased. A large stress was generated, which caused the SiC substrate 11 to crack. Since the stress of the film is proportional to the thickness thereof, the stress of the alloy layer is proportional to the thickness of the nanoparticle thin film 22 to be formed.

 図7は、荷重と応力との関係を説明するための図である。前述のSiC基板11の反りおよび割れについて検討する。理解を容易にするために、図7に示すように、SiC基板11として,円板状のウエハを想定し、ウエハの中心に荷重Pがかかったものとして考え、このときのウエハの反りと、ウエハにかかる最大応力とを計算する。ウエハにかかる最大応力σmaxは、以下の式(1)によって求められる。また、ウエハの反りwmaxは、以下の式(2)および式(3)によって求められる。 FIG. 7 is a diagram for explaining the relationship between load and stress. The warping and cracking of the SiC substrate 11 will be examined. In order to facilitate understanding, as shown in FIG. 7, a disk-shaped wafer is assumed as the SiC substrate 11 and a load P is applied to the center of the wafer. Calculate the maximum stress on the wafer. The maximum stress σ max applied to the wafer is obtained by the following equation (1). Further, the warpage w max of the wafer is obtained by the following equations (2) and (3).

Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001

Figure JPOXMLDOC01-appb-M000002
Figure JPOXMLDOC01-appb-M000002

Figure JPOXMLDOC01-appb-M000003
Figure JPOXMLDOC01-appb-M000003

 式(1)~式(3)において、tはウエハの厚みを表し、νはポアソン比を表す。また式(2)および式(3)において、Dはウエハの単位面積当たりの剛性を表し、式(3)において、Eは縦弾性係数を表す。 In Expressions (1) to (3), t represents the thickness of the wafer, and ν represents the Poisson's ratio. In Expressions (2) and (3), D represents the rigidity per unit area of the wafer, and in Expression (3), E represents the longitudinal elastic modulus.

 図8は、SiC基板11に割れが生じるときのSiC基板11の厚みとNi膜の厚みとの関係を示すグラフである。図8において、横軸はSiC基板11の厚み[μm]を表し、縦軸はニッケルナノ粒子で形成されたナノ粒子薄膜22であるNi膜の厚み[nm]を表す。 FIG. 8 is a graph showing the relationship between the thickness of the SiC substrate 11 and the thickness of the Ni film when a crack occurs in the SiC substrate 11. In FIG. 8, the horizontal axis represents the thickness [μm] of the SiC substrate 11, and the vertical axis represents the thickness [nm] of the Ni film that is the nanoparticle thin film 22 formed of nickel nanoparticles.

 SiC基板11の反りは、SiC基板11の厚みの2乗に反比例し、また膜応力、およびナノ粒子薄膜22の厚みに比例する。実際のSiC基板11の反りとナノ粒子薄膜22の厚みとから、SiC基板11に生じる応力を計算する。SiC基板11が割れてしまうときのナノ粒子薄膜22の厚みを、各厚みのSiC基板11に対して計算すると、図8に示すようになる。すなわち、ナノ粒子薄膜22の厚みをy、SiC基板11の厚みをxとしたとき、SiC基板11が割れるときのSiC基板11の厚みとナノ粒子薄膜22の厚みとの関係は、以下の式(4)を満たす二次関数の曲線で表される。
   y=0.0347x-0.8212x+21.286  …(4)
The warp of the SiC substrate 11 is inversely proportional to the square of the thickness of the SiC substrate 11, and is proportional to the film stress and the thickness of the nanoparticle thin film 22. The stress generated in the SiC substrate 11 is calculated from the actual warpage of the SiC substrate 11 and the thickness of the nanoparticle thin film 22. When the thickness of the nanoparticle thin film 22 when the SiC substrate 11 breaks is calculated for the SiC substrate 11 of each thickness, the thickness is as shown in FIG. That is, when the thickness of the nanoparticle thin film 22 is y and the thickness of the SiC substrate 11 is x, the relationship between the thickness of the SiC substrate 11 and the thickness of the nanoparticle thin film 22 when the SiC substrate 11 is broken is expressed by the following formula ( It is represented by a curve of a quadratic function that satisfies 4).
y = 0.0347x 2 -0.8212x + 21.286 (4)

 ナノ粒子薄膜22は、薄板化されたSiC基板11に対しては、式(4)で示される厚みyの値よりも薄くなくてはならない。すなわち、ナノ粒子薄膜22の厚みyは、SiC基板11の厚みxに対して、以下の式(5)を満足する必要がある。
   y≦0.0347x-0.8212x+21.286  …(5)
The nanoparticle thin film 22 must be thinner than the value of the thickness y represented by the equation (4) with respect to the thinned SiC substrate 11. That is, the thickness y of the nanoparticle thin film 22 needs to satisfy the following formula (5) with respect to the thickness x of the SiC substrate 11.
y ≦ 0.0347x 2 −0.8212x + 21.286 (5)

 式(5)を満足するようにナノ粒子薄膜22の厚みyを選択することによって、SiC基板11の割れ、およびSiC基板11の反りを抑制することができる。 By selecting the thickness y of the nanoparticle thin film 22 so as to satisfy the formula (5), cracking of the SiC substrate 11 and warping of the SiC substrate 11 can be suppressed.

 これによって、SiC基板11の反りを増加させることなく、レーザ光が照射される金属薄膜であるナノ粒子薄膜22の表面の反射率を低くすることができる。したがって、本実施の形態においても、SiC基板11の反りを増加させることなく、金属薄膜の表面の反射率を低下させて、低抵抗のオーミック電極の形成に必要なレーザ光のエネルギー密度を小さくすることができる。 Thereby, the reflectance of the surface of the nanoparticle thin film 22 which is a metal thin film irradiated with laser light can be lowered without increasing the warp of the SiC substrate 11. Therefore, also in the present embodiment, the energy density of the laser beam necessary for forming the low-resistance ohmic electrode is reduced by reducing the reflectivity of the surface of the metal thin film without increasing the warp of the SiC substrate 11. be able to.

 具体的には、SiC基板11として、円板状のウエハを用いて、ウエハの厚みをtμmとするとき、ウエハの直径が3インチの場合には、SiC基板11の反りを、100×(200/t)μm以下にすることができる。またウエハの直径が4インチの場合には、SiC基板11の反りを、250×(200/t)μm以下にすることができる。 Specifically, when a disc-shaped wafer is used as the SiC substrate 11 and the wafer thickness is t μm, and the wafer diameter is 3 inches, the warp of the SiC substrate 11 is 100 × (200 / T) Can be 2 μm or less. When the wafer diameter is 4 inches, the warp of the SiC substrate 11 can be reduced to 250 × (200 / t) 2 μm or less.

 金属ナノ粒子21による金属薄膜であるナノ粒子薄膜22を形成した後は、前述の第1の実施の形態と同様にして、ナノ粒子薄膜22にレーザ光を照射することによって、オーミック電極を形成する。 After forming the nanoparticle thin film 22 that is a metal thin film by the metal nanoparticles 21, the ohmic electrode is formed by irradiating the nanoparticle thin film 22 with laser light in the same manner as in the first embodiment. .

 以上のように本実施の形態によれば、ナノ薄膜形成工程の前に薄板化工程を設けて、電流経路であるSiC基板11を薄板化、具体的には、板厚が200μm以下になるように薄板化することによって、半導体素子1の抵抗を低減している。SiC基板11の薄板化にあたっては、SiC基板11の裏面、すなわち厚み方向他方側の表面を研削している。 As described above, according to the present embodiment, the thin plate forming step is provided before the nano thin film forming step to thin the SiC substrate 11 that is the current path, specifically, the plate thickness is 200 μm or less. The resistance of the semiconductor element 1 is reduced by reducing the thickness. In reducing the thickness of the SiC substrate 11, the back surface of the SiC substrate 11, that is, the surface on the other side in the thickness direction is ground.

 本実施の形態では、前述の第1の実施の形態と同様に、SiC基板11の裏面に形成する金属薄膜を、金属ナノ粒子21によってナノ粒子薄膜22として形成するので、金属薄膜に凹凸を形成するためにSiC基板11の裏面を研削する必要はない。したがって、SiC基板11の裏面を研削するときには、前述のように目の細かい砥石で加工表面が平坦になるように研削を行うことができる。これによって、加工歪層が形成される深さを浅くすることができるので、SiC基板11の反りを抑制することができる。 In the present embodiment, as in the first embodiment described above, the metal thin film formed on the back surface of the SiC substrate 11 is formed as the nanoparticle thin film 22 by the metal nanoparticles 21, so that irregularities are formed in the metal thin film. Therefore, it is not necessary to grind the back surface of the SiC substrate 11. Therefore, when the back surface of SiC substrate 11 is ground, it can be ground so that the processing surface becomes flat with a fine grindstone as described above. As a result, the depth at which the work strain layer is formed can be reduced, so that the warp of SiC substrate 11 can be suppressed.

 また本実施の形態では、前述の第1の実施の形態と同様に、金属ナノ粒子21によって金属薄膜としてナノ粒子薄膜22を形成することによって、レーザ光が照射される金属薄膜の表面の反射率を低下させることができる。これによって、低抵抗のオーミック電極の形成に必要なレーザ光のエネルギー密度を、スパッタ、蒸着などで金属膜を形成する場合に比べて低減することができるので、レーザ光の照射による処理時間を短縮することができる。 Further, in the present embodiment, as in the first embodiment described above, by forming the nanoparticle thin film 22 as a metal thin film by the metal nanoparticles 21, the reflectance of the surface of the metal thin film irradiated with the laser light is formed. Can be reduced. As a result, the energy density of the laser beam required to form a low-resistance ohmic electrode can be reduced compared to the case where a metal film is formed by sputtering, vapor deposition, etc., so the processing time by laser beam irradiation is shortened. can do.

 したがって、本実施の形態では、半導体装置100の信頼性を損なうことなく、可及的に小さいエネルギー密度のレーザ光の照射によって低抵抗のオーミック電極を形成することができるとともに、半導体素子1の抵抗を低減することができる。 Therefore, in this embodiment, a low-resistance ohmic electrode can be formed by irradiating laser light with as low energy density as possible without impairing the reliability of the semiconductor device 100, and the resistance of the semiconductor element 1 Can be reduced.

 本実施の形態では、薄板化工程では、SiC基板11の裏面を、算術平均粗さRaが10nm以下になるように研削している。研削後のSiC基板11の裏面の算術平均粗さRaが10nmを超えると、SiC基板11の裏面から深い位置まで加工歪層が形成されるおそれがあり、SiC基板11に過大な反りが発生するおそれがある。したがって、SiC基板11の裏面を研削するときには、本実施の形態のように算術平均粗さRaが10nm以下になるように研削することが好ましい。 In the present embodiment, in the thinning step, the back surface of the SiC substrate 11 is ground so that the arithmetic average roughness Ra is 10 nm or less. If the arithmetic mean roughness Ra of the back surface of the SiC substrate 11 after grinding exceeds 10 nm, a processed strain layer may be formed from the back surface of the SiC substrate 11 to a deep position, and the SiC substrate 11 is excessively warped. There is a fear. Therefore, when grinding the back surface of SiC substrate 11, it is preferable to grind so that arithmetic mean roughness Ra is 10 nm or less as in the present embodiment.

 SiC基板11の裏面を、算術平均粗さRaが10nm以下になるように研削することによって、研削加工後の加工表面であるSiC基板11の裏面に形成される加工歪層の深さを、可及的に浅くすることができるので、SiC基板11の反りを、より確実に抑制することができる。したがって、より信頼性の高い半導体装置100を得ることができる。 By grinding the back surface of the SiC substrate 11 so that the arithmetic average roughness Ra is 10 nm or less, the depth of the processing strain layer formed on the back surface of the SiC substrate 11 that is the processed surface after grinding is allowed. Since it can be made as shallow as possible, warping of SiC substrate 11 can be more reliably suppressed. Therefore, the semiconductor device 100 with higher reliability can be obtained.

 このようにSiC基板11の裏面を算術平均粗さRaが10nm以下になるように研削する方法として、本実施の形態では、SiC基板11の裏面を、平均砥粒径が20μm以下である砥石で研削している。砥石の平均砥粒径が20μmを超えると、研削後のSiC基板11の裏面の算術平均粗さRaを10nm以下にすることが困難になる。したがって、砥石の平均砥粒径は、20μm以下であることが好ましい。平均砥粒径が20μm以下である砥石で研削することによって、SiC基板11の裏面の算術平均粗さRaを、容易に10nm以下にすることができる。 In this embodiment, as a method for grinding the back surface of SiC substrate 11 so that the arithmetic average roughness Ra is 10 nm or less, in this embodiment, the back surface of SiC substrate 11 is a grindstone having an average abrasive grain size of 20 μm or less. Grinding. When the average abrasive grain size of the grindstone exceeds 20 μm, it becomes difficult to make the arithmetic average roughness Ra of the back surface of the SiC substrate 11 after grinding 10 nm or less. Therefore, the average abrasive grain size of the grindstone is preferably 20 μm or less. By grinding with a grindstone having an average abrasive grain size of 20 μm or less, the arithmetic average roughness Ra of the back surface of the SiC substrate 11 can be easily reduced to 10 nm or less.

 <第3の実施の形態>
 前述の第2の実施の形態では、薄板化したSiC基板11について、図1に示すような半導体装置の製造方法について説明した。前述のように、金属ナノ粒子21によって形成されるナノ粒子薄膜22が厚いと、レーザ光を照射した後に形成される合金層の厚みが大きくなり、合金層の応力が大きくなる。これによって、SiC基板11の反りが増大する。また、SiC基板11として円板状のウエハを用いた場合、ウエハの割れが発生することがある。
<Third Embodiment>
In the above-described second embodiment, the method of manufacturing the semiconductor device as shown in FIG. 1 has been described for the thinned SiC substrate 11. As described above, when the nanoparticle thin film 22 formed by the metal nanoparticles 21 is thick, the thickness of the alloy layer formed after the laser light irradiation is increased, and the stress of the alloy layer is increased. Thereby, the curvature of SiC substrate 11 increases. In addition, when a disc-shaped wafer is used as the SiC substrate 11, the wafer may be cracked.

 他方、ナノ粒子薄膜22が薄くなると、金属薄膜として、均一なナノ粒子薄膜22を形成することが難しくなる。また、形成したナノ粒子薄膜22に、ピンホールが形成されやすくなる。したがって、レーザ光を照射した後に得られるシリサイド層17が均質になりにくく、均質なオーミック電極が得られないおそれがあり、コンタクト抵抗の増加、および半導体素子1の信頼性の低下が生じてしまう。 On the other hand, when the nanoparticle thin film 22 becomes thin, it becomes difficult to form a uniform nanoparticle thin film 22 as a metal thin film. In addition, pinholes are easily formed in the formed nanoparticle thin film 22. Therefore, the silicide layer 17 obtained after the laser beam irradiation is difficult to be uniform, and there is a possibility that a uniform ohmic electrode cannot be obtained, resulting in an increase in contact resistance and a decrease in the reliability of the semiconductor element 1.

 ここで、金属ナノ粒子の粒径について述べる。ナノ粒子薄膜22は、それを構成する金属ナノ粒子の粒径が大きいほど、凹凸が大きくなり、レーザ光に対する反射率が小さくなる。しかし、金属ナノ粒子の粒径が大きいと、薄い金属薄膜を形成するときに、金属薄膜として、均一なナノ粒子薄膜22を形成することが難しくなる。 Here, the particle size of the metal nanoparticles will be described. As the particle size of the metal nanoparticles constituting the nanoparticle thin film 22 increases, the unevenness increases and the reflectance with respect to the laser beam decreases. However, when the particle size of the metal nanoparticles is large, it is difficult to form a uniform nanoparticle thin film 22 as a metal thin film when forming a thin metal thin film.

 図9は、ピンホール42が形成されたナノ粒子薄膜22を示す断面図である。図9では、薄板化されたSiC基板を、参照符号「41」で示している。前述のように金属ナノ粒子の粒径が大きいと、均一なナノ粒子薄膜22を形成することが難しくなるだけでなく、図9に示すように、形成されたナノ粒子薄膜22にピンホール42が形成されやすくなる。したがって、レーザ光を照射した後に得られるシリサイド層17が均質になりにくく、均質なオーミック電極が得られないおそれがあり、コンタクト抵抗の増加、および半導体素子1の信頼性の低下が生じてしまう。 FIG. 9 is a cross-sectional view showing the nanoparticle thin film 22 in which the pinholes 42 are formed. In FIG. 9, the thinned SiC substrate is indicated by a reference sign “41”. As described above, when the particle size of the metal nanoparticles is large, not only is it difficult to form a uniform nanoparticle thin film 22, but also pinholes 42 are formed in the formed nanoparticle thin film 22, as shown in FIG. It becomes easier to form. Therefore, the silicide layer 17 obtained after the laser light irradiation is difficult to be uniform, and there is a possibility that a uniform ohmic electrode cannot be obtained, resulting in an increase in contact resistance and a decrease in the reliability of the semiconductor element 1.

 他方、金属ナノ粒子21の粒径が小さいと、薄く均一なナノ粒子薄膜22を形成しやすい。したがって、薄く均一な合金層を形成しやすく、安定して低コンタクト抵抗が得られ、高い素子信頼性を得ることができる。しかし、ナノ粒子薄膜22の凹凸が小さくなり、レーザ光に対する反射率が大きくなるので、低コンタクト抵抗を得るために必要なレーザ光のエネルギーが大きくなってしまう。したがって、スループットおよび生産性が低下してしまう。 On the other hand, when the particle size of the metal nanoparticles 21 is small, it is easy to form a thin and uniform nanoparticle thin film 22. Therefore, it is easy to form a thin and uniform alloy layer, a stable low contact resistance can be obtained, and a high element reliability can be obtained. However, since the unevenness of the nanoparticle thin film 22 is reduced and the reflectance with respect to the laser beam is increased, the energy of the laser beam required to obtain a low contact resistance is increased. Therefore, throughput and productivity are reduced.

 そこで、本実施の形態では、薄板化したSiC基板41にナノ粒子薄膜22を形成して、レーザ光を照射し、オーミック電極を形成するときに、以下のようにしている。これによって、後述するように、SiC基板41の反りの増大、およびSiC基板41の割れがなく、均一で安定した低コンタクト抵抗を有する高い信頼性を有する半導体素子1を備える半導体装置100を高い生産性で得ることができる。 Therefore, in the present embodiment, the nanoparticle thin film 22 is formed on the thinned SiC substrate 41 and irradiated with laser light to form the ohmic electrode as follows. As a result, as will be described later, the production of the semiconductor device 100 including the highly reliable semiconductor element 1 having a uniform and stable low contact resistance without increasing the warp of the SiC substrate 41 and cracking of the SiC substrate 41. Can be obtained by sex.

 ナノ粒子薄膜22を形成する工程以外は、前述の第2の実施の形態と同一であるので、ナノ粒子薄膜22を形成する工程に重点をおいて説明する。 Since the steps other than the step of forming the nanoparticle thin film 22 are the same as those in the second embodiment described above, the description will be given with emphasis on the step of forming the nanoparticle thin film 22.

 はじめに、準備工程において、SiC基板11、具体的にはn型のSiC基板11を準備する。次に表面加工工程において、SiC基板11の表面上に、SiCエピタキシャル層12を成長させる。SiCエピタキシャル層12におけるn型不純物のドーピング濃度は、たとえば5×1015個cm-3~5×1016個cm-3である。SiCエピタキシャル層12の膜厚は、たとえば5μm~15μmである。SiCエピタキシャル層12の厚み方向一方側の表面上に、犠牲酸化によって、酸化膜を形成する。 First, in the preparation step, an SiC substrate 11, specifically, an n-type SiC substrate 11 is prepared. Next, in the surface processing step, SiC epitaxial layer 12 is grown on the surface of SiC substrate 11. The doping concentration of the n-type impurity in SiC epitaxial layer 12 is, for example, 5 × 10 15 cm −3 to 5 × 10 16 cm −3 . The film thickness of SiC epitaxial layer 12 is, for example, 5 μm to 15 μm. An oxide film is formed on the surface of one side in the thickness direction of SiC epitaxial layer 12 by sacrificial oxidation.

 次に、p型終端構造を形成する処理を行う。具体的には、まず、SiCエピタキシャル層12の厚み方向一方側の表面上に形成した酸化膜上に、イオン注入マスクを形成する。 Next, a process for forming a p-type termination structure is performed. Specifically, first, an ion implantation mask is formed on the oxide film formed on the surface on one side in the thickness direction of SiC epitaxial layer 12.

 このイオン注入マスクの厚み方向一方側から、p型不純物、たとえばアルミニウムをイオン注入することによって、p型不純物をSiCエピタキシャル層12の予め定める領域に選択的にイオン注入し、イオン注入領域13を形成する。イオン注入領域13は、たとえば、注入量が1×1016cm-3~1×1018cm-3となり、注入深さが0.5μm~1.0μmとなるように、室温たとえば25℃で、注入角度を0°として、40keV~700keVのエネルギーでp型不純物イオン、たとえばアルミニウムイオンを注入することによって形成される。 A p-type impurity, for example, aluminum is ion-implanted from one side in the thickness direction of the ion implantation mask to selectively ion-implant the p-type impurity into a predetermined region of the SiC epitaxial layer 12 to form an ion implantation region 13. To do. The ion implantation region 13 has, for example, an implantation amount of 1 × 10 16 cm −3 to 1 × 10 18 cm −3 and an implantation depth of 0.5 μm to 1.0 μm at room temperature, for example, 25 ° C. It is formed by implanting p-type impurity ions such as aluminum ions at an energy of 40 keV to 700 keV with an implantation angle of 0 °.

 次に、イオン注入マスクを除去し、第1の実施の形態と同様にしてJTE領域14を形成し、JTE領域14の形成に用いたJTE用マスクと酸化膜とを除去する。その後、注入したアルミニウムイオンなどのp型不純物イオンを活性化させるために、たとえばアルゴン雰囲気中で、1500℃~2000℃の温度で、1分~30分間熱処理を行う。この熱処理工程によって、注入されたイオンが活性化されて、p型終端構造が形成される。 Next, the ion implantation mask is removed, the JTE region 14 is formed in the same manner as in the first embodiment, and the JTE mask and the oxide film used for forming the JTE region 14 are removed. Thereafter, in order to activate p-type impurity ions such as implanted aluminum ions, heat treatment is performed at a temperature of 1500 ° C. to 2000 ° C. for 1 minute to 30 minutes, for example, in an argon atmosphere. By this heat treatment step, the implanted ions are activated and a p-type termination structure is formed.

 次に、イオン注入領域13に囲まれたショットキ領域18に、ショットキ電極15を、その周縁部がイオン注入領域13にはみ出すように形成する。ショットキ電極15の材料としては、チタン(Ti)、タングステン(W)、モリブデン(Mo)およびクロム(Cr)などが挙げられる。次に、ショットキ電極15の厚み方向一方側の表面上に、配線電極16を形成する。配線電極16の材料としては、Alなどが挙げられる。 Next, the Schottky electrode 15 is formed in the Schottky region 18 surrounded by the ion implantation region 13 so that the peripheral portion protrudes from the ion implantation region 13. Examples of the material of the Schottky electrode 15 include titanium (Ti), tungsten (W), molybdenum (Mo), and chromium (Cr). Next, the wiring electrode 16 is formed on the surface on one side in the thickness direction of the Schottky electrode 15. Examples of the material of the wiring electrode 16 include Al.

 次に、裏面加工工程の薄板化工程において、SiC基板11の裏面、すなわち厚み方向他方側の表面を研削することによって、SiC基板11の厚みを薄くする。たとえば、板厚が400μmのSiC基板11を用いて半導体装置100を作製する場合、SiC基板11の裏面全体を研削することによって、SiC基板11を、板厚が200μm以下になるように薄板化する。この際に形成される加工歪層の深さを浅くしてSiC基板11の反りを抑制するために、SiC基板11の裏面を平均砥粒径が20μm以下である1000番以上の目の細かい砥石で研削し、SiC基板11の裏面の算術平均粗さRaを10nm以下になるように研削する。 Next, in the thinning step of the back surface processing step, the back surface of the SiC substrate 11, that is, the surface on the other side in the thickness direction is ground to reduce the thickness of the SiC substrate 11. For example, when manufacturing semiconductor device 100 using SiC substrate 11 having a plate thickness of 400 μm, SiC substrate 11 is thinned so that the plate thickness becomes 200 μm or less by grinding the entire back surface of SiC substrate 11. . In order to suppress the warp of the SiC substrate 11 by reducing the depth of the processed strain layer formed at this time, the fine grinding stone of 1000th or more having an average abrasive grain size of 20 μm or less on the back surface of the SiC substrate 11. Then, the arithmetic average roughness Ra of the back surface of the SiC substrate 11 is ground to 10 nm or less.

 次に、ナノ薄膜形成工程において、SiC基板11の裏面にナノ粒子薄膜22を形成する。ナノ粒子薄膜22は、金属ナノ粒子の粒径が大きいほど、凹凸が大きくなり、レーザ光に対する反射率が小さくなる。しかし、金属ナノ粒子21の粒径が過度に大きいと、均一なナノ粒子薄膜22を形成することが難しく、また、形成したナノ粒子薄膜22にピンホール42が形成されやすくなる。 Next, in the nano thin film forming step, the nano particle thin film 22 is formed on the back surface of the SiC substrate 11. In the nanoparticle thin film 22, the larger the metal nanoparticles have a larger particle size, the larger the unevenness and the lower the reflectance with respect to the laser beam. However, when the particle size of the metal nanoparticles 21 is excessively large, it is difficult to form a uniform nanoparticle thin film 22, and pinholes 42 are easily formed in the formed nanoparticle thin film 22.

 他方、金属ナノ粒子21の粒径が小さいと、薄く均一なナノ粒子薄膜22を形成しやすい。しかし、金属ナノ粒子21の粒径が小さいと、ナノ粒子薄膜22の凹凸が小さくなり、レーザ光に対する反射率が大きくなる。本実施の形態では、反射率が小さいナノ粒子薄膜22を均一に形成するために、金属ナノ粒子21として、粒径分布のピークを2つ以上有する金属ナノ粒子を用いる。 On the other hand, when the particle size of the metal nanoparticles 21 is small, it is easy to form a thin and uniform nanoparticle thin film 22. However, when the particle diameter of the metal nanoparticles 21 is small, the unevenness of the nanoparticle thin film 22 is reduced, and the reflectance with respect to the laser light is increased. In the present embodiment, in order to uniformly form the nanoparticle thin film 22 having a low reflectance, metal nanoparticles having two or more particle size distribution peaks are used as the metal nanoparticles 21.

 図10は、本発明の第3の実施の形態で用いられる金属ナノ粒子21を模式的に示す断面図である。本実施の形態では、金属ナノ粒子21として、粒径が1nm以上50nm以下である比較的小さい金属ナノ粒子(以下「小粒径ナノ粒子」という場合がある)52と、粒径が50nmを超えて100nm以下である比較的大きい金属ナノ粒子(以下「大粒径ナノ粒子」という場合がある)51とを含む金属ナノ粒子21を用いる。すなわち、金属ナノ粒子21としては、粒径分布のピークを2つ以上有し、粒径分布のピークのうち、少なくとも1つは、1nm以上50nm未満の粒径の範囲内に存在し、かつ他の少なくとも1つは、50nm以上100nm未満の粒径の範囲内に存在する金属ナノ粒子21を用いる。 FIG. 10 is a cross-sectional view schematically showing the metal nanoparticles 21 used in the third embodiment of the present invention. In the present embodiment, as the metal nanoparticles 21, a relatively small metal nanoparticle (hereinafter sometimes referred to as “small particle nanoparticle”) 52 having a particle size of 1 nm or more and 50 nm or less, and a particle size exceeding 50 nm. Metal nanoparticles 21 including relatively large metal nanoparticles (hereinafter sometimes referred to as “large particle size nanoparticles”) 51 of 100 nm or less are used. That is, the metal nanoparticle 21 has two or more particle size distribution peaks, and at least one of the particle size distribution peaks exists within a particle size range of 1 nm or more and less than 50 nm, and others. At least one of the above uses metal nanoparticles 21 present in a particle size range of 50 nm or more and less than 100 nm.

 このような金属ナノ粒子21を塗布した後、前述の実施の形態と同様に焼結させる。本実施の形態では、金属ナノ粒子21は、大粒径ナノ粒子51と小粒径ナノ粒子52とを含むので、図10に示すように、大粒径ナノ粒子51によって、比較的大きい凹凸をナノ粒子薄膜22に形成することができる。これによって、ナノ粒子薄膜22の反射率を小さくすることができる。また小粒径ナノ粒子52によって、ピンホール42を閉塞することができるので、均一なナノ粒子薄膜22を形成することができる。 After such metal nanoparticles 21 are applied, sintering is performed in the same manner as in the above-described embodiment. In the present embodiment, the metal nanoparticles 21 include the large particle size nanoparticles 51 and the small particle size nanoparticles 52. Therefore, as shown in FIG. The nanoparticle thin film 22 can be formed. Thereby, the reflectance of the nanoparticle thin film 22 can be reduced. Moreover, since the pinhole 42 can be obstruct | occluded by the small particle size nanoparticle 52, the uniform nanoparticle thin film 22 can be formed.

 以上のようにして金属ナノ粒子21によって、金属薄膜としてナノ粒子薄膜22を形成する。その後は、前述の実施の形態と同様にして、ナノ粒子薄膜22にレーザ光を照射することによって、オーミック電極を形成する。 The nanoparticle thin film 22 is formed as a metal thin film by the metal nanoparticles 21 as described above. Thereafter, the ohmic electrode is formed by irradiating the nanoparticle thin film 22 with laser light in the same manner as in the above-described embodiment.

 本実施の形態によれば、粒径分布のピークを2つ以上有し、粒径分布のピークのうち、少なくとも1つは、1nm以上50nm未満の粒径の範囲内に存在し、かつ他の少なくとも1つは、50nm以上100nm未満の粒径の範囲内に存在する金属ナノ粒子21が用いられる。これによって、レーザ光が照射される金属薄膜であるナノ粒子薄膜22の表面の反射率を低くすることができ、かつピンホール42の無い均一なナノ粒子薄膜22を形成することができる。したがって、SiC基板41の反りを増加させることなく、金属薄膜であるナノ粒子薄膜22の表面の反射率を低下させて、低抵抗のオーミック電極の形成に必要なレーザ光のエネルギー密度を小さくすることができる。また、レーザ光を照射した後に得られるシリサイド層17も均一になるので、均一で安定した低コンタクト抵抗を有し、高い信頼性を有する半導体素子1を備える半導体装置を、高い生産性で得ることができる。 According to the present embodiment, there are two or more particle size distribution peaks, and at least one of the particle size distribution peaks is present within a particle size range of 1 nm or more and less than 50 nm, and other At least one of the metal nanoparticles 21 present in a particle size range of 50 nm or more and less than 100 nm is used. Thereby, the reflectance of the surface of the nanoparticle thin film 22 which is a metal thin film irradiated with laser light can be lowered, and the uniform nanoparticle thin film 22 without the pinhole 42 can be formed. Therefore, without increasing the warp of the SiC substrate 41, the reflectivity of the surface of the nanoparticle thin film 22 which is a metal thin film is reduced, and the energy density of the laser light necessary for forming the low resistance ohmic electrode is reduced. Can do. Further, since the silicide layer 17 obtained after the laser light irradiation is uniform, a semiconductor device including the semiconductor element 1 having a uniform and stable low contact resistance and high reliability can be obtained with high productivity. Can do.

 <第4の実施の形態>
 図11は、本発明の第4の実施の形態の半導体装置の製造方法における裏面加工工程の手順を示すフローチャートである。本実施の形態の半導体装置の製造方法は、図11に示す裏面加工工程を備えること以外は、前述の第2の実施の形態と同様であるので、同様の工程については説明を省略する。
<Fourth embodiment>
FIG. 11 is a flowchart showing the procedure of the back surface processing step in the semiconductor device manufacturing method according to the fourth embodiment of the present invention. Since the manufacturing method of the semiconductor device of this embodiment is the same as that of the second embodiment described above except that it includes the back surface processing step shown in FIG. 11, the description of the same steps is omitted.

 本実施の形態における裏面加工工程は、ステップb1の薄板化工程とステップa1のナノ薄膜形成工程との間にステップc1の成膜工程を備えること以外は、前述の図6に示す第2の実施の形態における裏面加工工程と同一である。すなわち、本実施の形態における裏面加工工程は、ステップb1の薄板化工程と、ステップc1の成膜工程と、ステップa1のナノ薄膜形成工程と、ステップa2の電極形成工程とを備える。ステップa1のナノ薄膜形成工程と、ステップa2の電極形成工程とは、シリサイド層形成工程を構成する。 The back surface processing step in the present embodiment is the second embodiment shown in FIG. 6 described above except that the film forming step of step c1 is provided between the thinning step of step b1 and the nano thin film forming step of step a1. This is the same as the back surface processing step in the embodiment. That is, the back surface processing step in the present embodiment includes a thinning step in step b1, a film forming step in step c1, a nano thin film forming step in step a1, and an electrode forming step in step a2. The nano thin film forming process in step a1 and the electrode forming process in step a2 constitute a silicide layer forming process.

 図12は、本発明の第4の実施の形態においてシリサイド層形成工程が終了した段階の状態を示す断面図である。本実施の形態では、ステップa1のナノ薄膜形成工程でナノ粒子薄膜22を形成する前に、ステップc1の成膜工程において、図12に示すように、スパッタまたは蒸着によって、ナノ粒子薄膜22の下地となる下地金属薄膜61を形成する。その後は、第2の実施の形態と同様にして、ステップa1のナノ薄膜形成工程においてナノ粒子薄膜22を形成した後、ステップa2の電極形成工程でシリサイド層17を形成する。 FIG. 12 is a cross-sectional view showing a state at the stage where the silicide layer forming step is completed in the fourth embodiment of the present invention. In the present embodiment, before forming the nanoparticle thin film 22 in the nano thin film forming process in step a1, in the film forming process in step c1, the base of the nanoparticle thin film 22 is formed by sputtering or vapor deposition as shown in FIG. A base metal thin film 61 is formed. Thereafter, in the same manner as in the second embodiment, after forming the nanoparticle thin film 22 in the nano thin film forming process in step a1, the silicide layer 17 is formed in the electrode forming process in step a2.

 スパッタまたは蒸着によって成膜することによって、ピンホールの無い均一な下地金属薄膜61を形成しやすい。この下地金属薄膜61の表面上に、表面の反射率を低くすることができるナノ粒子薄膜22を形成することによって、均一で反射率の低い金属薄膜を形成することができる。また、レーザ光を照射した後に得られるシリサイド層17も均一になる。 By forming the film by sputtering or vapor deposition, it is easy to form a uniform base metal thin film 61 without a pinhole. By forming the nanoparticle thin film 22 capable of reducing the surface reflectance on the surface of the underlying metal thin film 61, a uniform and low reflectance metal thin film can be formed. In addition, the silicide layer 17 obtained after the laser light irradiation is made uniform.

 下地金属薄膜61の材料としては、ニッケル(Ni)、チタン(Ti)、コバルト(Co)、モリブデン(Mo)、タングステン(W)などから選ばれる1種または2種以上を用いることができる。 As the material of the base metal thin film 61, one or more selected from nickel (Ni), titanium (Ti), cobalt (Co), molybdenum (Mo), tungsten (W) and the like can be used.

 下地金属薄膜61は応力が大きいので、下地金属薄膜61の厚みが過度に大きくなると、SiC基板11の反りが大きくなり、最悪の場合には、SiC基板11が割れてしまう。これを防ぐために、下地金属薄膜61の厚みは、1nm以上50nm以下にすることが望ましい。 Since the base metal thin film 61 has a large stress, if the thickness of the base metal thin film 61 is excessively large, the warp of the SiC substrate 11 is increased, and in the worst case, the SiC substrate 11 is cracked. In order to prevent this, it is desirable that the thickness of the base metal thin film 61 be 1 nm or more and 50 nm or less.

 下地金属薄膜61上に形成するナノ粒子薄膜21の材料としては、ニッケル(Ni)、チタン(Ti)、コバルト(Co)、モリブデン(Mo)、タングステン(W)などから選ばれる1種または2種以上を用いることができる。ナノ粒子薄膜22の材料は、下地金属薄膜61の材料と同じであってもよいし、異なっていてもよい。 The material of the nanoparticle thin film 21 formed on the base metal thin film 61 is one or two selected from nickel (Ni), titanium (Ti), cobalt (Co), molybdenum (Mo), tungsten (W), and the like. The above can be used. The material of the nanoparticle thin film 22 may be the same as or different from the material of the base metal thin film 61.

 また、前述のように、ナノ粒子薄膜22の膜厚が厚いと、レーザ光の照射後に形成される炭化珪素との合金層の厚みも大きくなり、この膜の応力が大きくなり、SiC基板41の反りが大きくなり、最悪の場合にはSiC基板41が割れてしまう。したがって、下地金属薄膜61とナノ粒子薄膜22と炭化珪素とが反応して形成される合金層の応力で、SiC基板11の割れが生じない厚みにしなければならない。 In addition, as described above, when the nanoparticle thin film 22 is thick, the thickness of the alloy layer with silicon carbide formed after the laser light irradiation increases, and the stress of the film increases, and the SiC substrate 41 Warpage becomes large, and in the worst case, the SiC substrate 41 is broken. Therefore, the thickness of the SiC substrate 11 must not be cracked by the stress of the alloy layer formed by the reaction between the base metal thin film 61, the nanoparticle thin film 22, and silicon carbide.

 たとえば、下地金属薄膜61の材料としてニッケルを用い、ナノ粒子薄膜22の材料にもニッケルを用いた場合、下地金属薄膜61とナノ粒子薄膜22との合計の厚みは、SiC基板11の厚みに対して、前述の式(4)に示す値以下にならなければならない。 For example, when nickel is used as the material of the base metal thin film 61 and nickel is also used as the material of the nanoparticle thin film 22, the total thickness of the base metal thin film 61 and the nanoparticle thin film 22 is smaller than the thickness of the SiC substrate 11. Therefore, it must be less than or equal to the value shown in equation (4) above.

 また、金属ナノ粒子の粒径は、1nm~100nmが好ましい。特に、前述の第3の実施の形態のように、粒径分布のピークを2つ以上有し、粒径分布のピークのうち、少なくとも1つは、1nm以上50nm未満の粒径の範囲内に存在し、かつ他の少なくとも1つは、50nm以上100nm未満の粒径の範囲内に存在する金属ナノ粒子21を用いることが好ましい。 The particle size of the metal nanoparticles is preferably 1 nm to 100 nm. In particular, as in the third embodiment described above, there are two or more particle size distribution peaks, and at least one of the particle size distribution peaks is within the range of the particle size of 1 nm or more and less than 50 nm. It is preferable to use metal nanoparticles 21 that exist and at least one of the other particles exists within a range of a particle size of 50 nm or more and less than 100 nm.

 以上のようにして、スパッタまたは蒸着で形成した下地金属薄膜61の表面上に、金属ナノ粒子によって金属薄膜としてナノ粒子薄膜22を形成することによって、蒸着などの他の方法によって金属薄膜を形成する場合に比べて、金属薄膜の反射率を低くすることができる。また、均一に炭化珪素との合金層を形成することができるので、均一で安定した低コンタクト抵抗、および高い信頼性を有する半導体素子を備える半導体装置を、高い生産性で得ることができる。 As described above, by forming the nanoparticle thin film 22 as a metal thin film with metal nanoparticles on the surface of the base metal thin film 61 formed by sputtering or vapor deposition, a metal thin film is formed by another method such as vapor deposition. Compared with the case, the reflectance of a metal thin film can be made low. In addition, since an alloy layer with silicon carbide can be formed uniformly, a semiconductor device including a semiconductor element having a uniform and stable low contact resistance and high reliability can be obtained with high productivity.

 特に、前述の第3の実施の形態のように、粒径分布のピークを2つ以上有し、粒径分布のピークのうち、少なくとも1つは、1nm以上50nm未満の粒径の範囲内に存在し、かつ他の少なくとも1つは、50nm以上100nm未満の粒径の範囲内に存在する金属ナノ粒子21を用いることによって、より均一なナノ粒子薄膜22を形成することができる。 In particular, as in the above-described third embodiment, there are two or more particle size distribution peaks, and at least one of the particle size distribution peaks is within the range of the particle size of 1 nm or more and less than 50 nm. A more uniform nanoparticle thin film 22 can be formed by using the metal nanoparticles 21 that are present and at least one of them exists in a particle size range of 50 nm or more and less than 100 nm.

 下地金属薄膜61の膜厚は、1nm以上50nm以下であることが好ましい。またナノ粒子薄膜22の膜厚と下地金属薄膜61の膜厚との合計をz(nm)とし、SiC基板41の板厚をx(μm)としたとき、以下の式(6)を満足することが好ましい。
  z≦(0.0347x-0.8212x+21.286) …(6)
The film thickness of the base metal thin film 61 is preferably 1 nm or more and 50 nm or less. Further, when the total thickness of the nanoparticle thin film 22 and the base metal thin film 61 is z (nm) and the thickness of the SiC substrate 41 is x (μm), the following formula (6) is satisfied. It is preferable.
z ≦ (0.0347x 2 −0.8212x + 21.286) (6)

 これによって、SiC基板41の割れ、およびSiC基板41の反りを抑制することができるので、SiC基板41の反りを増加させることなく、レーザ光が照射される金属薄膜であるナノ粒子薄膜22の表面の反射率を低くすることができる。したがって、本実施の形態においても、SiC基板41の反りを増加させることなく、金属薄膜であるナノ粒子薄膜22の表面の反射率を低下させて、低抵抗のオーミック電極の形成に必要なレーザ光のエネルギー密度を小さくすることができる。 As a result, cracking of the SiC substrate 41 and warping of the SiC substrate 41 can be suppressed, so that the surface of the nanoparticle thin film 22 that is a metal thin film irradiated with laser light without increasing the warping of the SiC substrate 41. The reflectance can be lowered. Therefore, also in this embodiment, without increasing the warp of the SiC substrate 41, the reflectance of the surface of the nanoparticle thin film 22 which is a metal thin film is reduced, and the laser light necessary for forming a low-resistance ohmic electrode The energy density can be reduced.

 以上に述べた各実施の形態では、半導体素子1として、SiCを用いたSBDを挙げたが、半導体素子1は、これに限定されず、たとえばMOSFETであってもよい。半導体素子1がMOSFETである場合でも、本実施の形態と同様の方法によって、低抵抗のオーミック電極を形成することができる。 In each of the embodiments described above, the SBD using SiC is exemplified as the semiconductor element 1, but the semiconductor element 1 is not limited to this, and may be, for example, a MOSFET. Even when the semiconductor element 1 is a MOSFET, a low-resistance ohmic electrode can be formed by the same method as in the present embodiment.

 また以上に述べた各実施の形態では、オーミック電極形成工程に用いる金属薄膜としては、ニッケル(Ni)膜を成膜した場合を例に挙げて説明したが、金属薄膜は、Ni膜に限らない。SiCとシリサイド化する金属膜であれば、金属薄膜として使用可能であり、本実施の形態と同様に実施可能である。SiCとシリサイド化する金属としては、たとえば、チタン(Ti)、コバルト(Co)、モリブデン(Mo)およびタングステン(W)が挙げられる。 Further, in each of the embodiments described above, the case where a nickel (Ni) film is formed as an example of the metal thin film used in the ohmic electrode formation process has been described, but the metal thin film is not limited to the Ni film. . Any metal film that can be silicided with SiC can be used as a metal thin film, and can be implemented in the same manner as the present embodiment. Examples of the metal that forms a silicide with SiC include titanium (Ti), cobalt (Co), molybdenum (Mo), and tungsten (W).

 本発明は、その発明の範囲内において、前述の各実施の形態を自由に組み合わせることが可能であり、また各実施の形態の任意の構成要素を適宜、変形または省略することが可能である。 The present invention can freely combine the above-described embodiments within the scope of the invention, and can arbitrarily modify or omit any component of each embodiment.

 この発明は詳細に説明されたが、上記した説明は、すべての局面において、例示であって、この発明がそれに限定されるものではない。例示されていない無数の変形例が、この発明の範囲から外れることなく想定され得るものと解される。 Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It is understood that countless variations that are not illustrated can be envisaged without departing from the scope of the present invention.

 1 窒化物半導体素子、10 SiC基体、11,41 SiC基板、12 SiCエピタキシャル層、13 イオン注入領域、14 JTE領域、15 ショットキ電極、16 配線電極、17 シリサイド層、18 ショットキ領域、20 デバイス部、21 金属ナノ粒子、22 ナノ粒子薄膜、51 大粒径ナノ粒子、52 小粒径ナノ粒子、61 下地金属薄膜、100 半導体装置。 1 nitride semiconductor element, 10 SiC substrate, 11, 41 SiC substrate, 12 SiC epitaxial layer, 13 ion implantation region, 14 JTE region, 15 Schottky electrode, 16 wiring electrode, 17 silicide layer, 18 Schottky region, 20 device part, 21 metal nanoparticles, 22 nanoparticle thin film, 51 large particle size nanoparticle, 52 small particle size nanoparticle, 61 base metal thin film, 100 semiconductor device.

Claims (12)

 炭化珪素基板(11,41)の厚み方向の一表面上に、金属ナノ粒子(21)によって、金属薄膜であるナノ粒子薄膜(22)を形成するナノ薄膜形成工程と、
 前記ナノ薄膜形成工程で形成された前記ナノ粒子薄膜(22)にレーザ光を照射することによってオーミック電極を形成する電極形成工程とを備えることを特徴とする半導体装置の製造方法。
A nano thin film forming step of forming a nano particle thin film (22), which is a metal thin film, with metal nanoparticles (21) on one surface in the thickness direction of the silicon carbide substrate (11, 41);
A method of manufacturing a semiconductor device comprising: an electrode forming step of forming an ohmic electrode by irradiating the nanoparticle thin film (22) formed in the nano thin film forming step with laser light.
 前記金属ナノ粒子(21)の粒径は、1nm以上100nm以下であることを特徴とする請求項1に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein a particle diameter of the metal nanoparticles (21) is not less than 1 nm and not more than 100 nm.  前記ナノ粒子薄膜(22)の膜厚は、10nm以上500nm以下であることを特徴とする請求項1または2に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 1, wherein the film thickness of the nanoparticle thin film (22) is not less than 10 nm and not more than 500 nm.  前記ナノ薄膜形成工程の前に、
 前記炭化珪素基板(11,41)を、板厚が200μm以下になるように薄板化する薄板化工程を備えることを特徴とする請求項1に記載の半導体装置の製造方法。
Before the nano thin film forming step,
The method for manufacturing a semiconductor device according to claim 1, further comprising a thinning step of thinning the silicon carbide substrate (11, 41) so that the plate thickness becomes 200 μm or less.
 前記薄板化工程では、前記炭化珪素基板(11,41)の厚み方向の一表面を、算術平均粗さRaが10nm以下になるように研削することによって、前記炭化珪素基板(11,41)を薄板化し、
 前記ナノ薄膜形成工程では、前記炭化珪素基板(11,41)の厚み方向の一表面であって前記薄板化工程で研削された表面上に、前記ナノ粒子薄膜(22)を形成することを特徴とする請求項4に記載の半導体装置の製造方法。
In the thinning step, the silicon carbide substrate (11, 41) is ground by grinding one surface in the thickness direction of the silicon carbide substrate (11, 41) so that the arithmetic average roughness Ra is 10 nm or less. Thinned,
In the nano thin film forming step, the nano particle thin film (22) is formed on one surface in the thickness direction of the silicon carbide substrate (11, 41) and ground in the thinning step. A method for manufacturing a semiconductor device according to claim 4.
 前記薄板化工程では、
 前記炭化珪素基板(11,41)の厚み方向の一表面を、平均砥粒径が20μm以下である砥石で研削することによって、前記算術平均粗さRaが10nm以下になるように研削することを特徴とする請求項5に記載の半導体装置の製造方法。
In the thinning step,
Grinding one surface in the thickness direction of the silicon carbide substrate (11, 41) with a grindstone having an average abrasive grain size of 20 μm or less so that the arithmetic average roughness Ra is 10 nm or less. The method of manufacturing a semiconductor device according to claim 5, wherein:
 前記ナノ粒子薄膜(22)の膜厚をy(nm)とし、前記炭化珪素基板(11,41)の板厚をx(μm)としたとき、以下の関係式:
   y≦(0.0347x-0.8212x+21.286)
を満足することを特徴とする請求項4~6のいずれか1つに記載の半導体装置の製造方法。
When the thickness of the nanoparticle thin film (22) is y (nm) and the thickness of the silicon carbide substrate (11, 41) is x (μm), the following relational expression:
y ≦ (0.0347x 2 -0.8212x + 21.286)
The method of manufacturing a semiconductor device according to claim 4, wherein:
 前記金属ナノ粒子(21)の材料は、ニッケル(Ni)、チタン(Ti)、コバルト(Co)、モリブデン(Mo)およびタングステン(W)から選ばれる1種または2種以上を含むことを特徴とする請求項1または4に記載の半導体装置の製造方法。 The material of the metal nanoparticles (21) includes one or more selected from nickel (Ni), titanium (Ti), cobalt (Co), molybdenum (Mo) and tungsten (W). A method of manufacturing a semiconductor device according to claim 1 or 4.  前記ナノ薄膜形成工程は、
 前記炭化珪素基板(11,41)の厚み方向の一表面上に、前記金属ナノ粒子(21)を含む溶媒を塗布する塗布段階と、
 前記塗布段階で塗布された前記金属ナノ粒子(21)を焼結させることによって、前記ナノ粒子薄膜(22)を形成する焼結段階とを備えることを特徴とする請求項1または4に記載の半導体装置の製造方法。
The nano thin film forming step includes:
An application step of applying a solvent containing the metal nanoparticles (21) on one surface in the thickness direction of the silicon carbide substrate (11, 41);
The sintering step of forming the nanoparticle thin film (22) by sintering the metal nanoparticles (21) applied in the application step, according to claim 1 or 4. A method for manufacturing a semiconductor device.
 前記金属ナノ粒子(21)は、粒径分布のピークを2つ以上有し、前記粒径分布のピークのうち、少なくとも1つは、1nm以上50nm未満の粒径の範囲内に存在し、かつ他の少なくとも1つは、50nm以上100nm未満の粒径の範囲内に存在することを特徴とする請求項1または4に記載の半導体装置の製造方法。 The metal nanoparticle (21) has two or more particle size distribution peaks, and at least one of the particle size distribution peaks is present in a particle size range of 1 nm or more and less than 50 nm, and 5. The method of manufacturing a semiconductor device according to claim 1, wherein at least one of the other particles exists in a particle diameter range of 50 nm or more and less than 100 nm.  前記ナノ薄膜形成工程の前に、前記炭化珪素基板(41)の厚み方向の一表面に、前記ナノ粒子薄膜(22)の下地となる金属薄膜である下地金属薄膜(61)を、スパッタまたは蒸着によって成膜する成膜工程を備え、
 前記ナノ薄膜形成工程では、前記成膜工程で成膜された前記下地金属薄膜(61)の厚み方向の一表面上に、前記ナノ粒子薄膜(22)を形成することを特徴とする請求項1または4に記載の半導体装置の製造方法。
Prior to the nano thin film forming step, a base metal thin film (61), which is a metal thin film serving as a base of the nano particle thin film (22), is sputtered or deposited on one surface in the thickness direction of the silicon carbide substrate (41). Comprising a film forming step of forming a film by
The nanoparticle thin film (22) is formed on one surface in the thickness direction of the base metal thin film (61) formed in the film forming step in the nano thin film forming step. Or a method of manufacturing a semiconductor device according to 4;
 前記下地金属薄膜(61)の膜厚は、1nm以上50nm以下であり、
 前記ナノ粒子薄膜(22)の膜厚と前記下地金属薄膜(61)の膜厚との合計をz(nm)とし、前記炭化珪素基板(41)の板厚をx(μm)としたとき、以下の関係式:
   z≦(0.0347x-0.8212x+21.286)
を満足することを特徴とする請求項11に記載の半導体装置の製造方法。
The film thickness of the base metal thin film (61) is 1 nm or more and 50 nm or less,
When the total thickness of the nanoparticle thin film (22) and the base metal thin film (61) is z (nm) and the thickness of the silicon carbide substrate (41) is x (μm), The following relation:
z ≦ (0.0347x 2 -0.8212x + 21.286)
The method of manufacturing a semiconductor device according to claim 11, wherein:
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