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WO2013018595A1 - Display device and method for powering same - Google Patents

Display device and method for powering same Download PDF

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Publication number
WO2013018595A1
WO2013018595A1 PCT/JP2012/068757 JP2012068757W WO2013018595A1 WO 2013018595 A1 WO2013018595 A1 WO 2013018595A1 JP 2012068757 W JP2012068757 W JP 2012068757W WO 2013018595 A1 WO2013018595 A1 WO 2013018595A1
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WO
WIPO (PCT)
Prior art keywords
period
scanning
video signal
clock signal
source
Prior art date
Application number
PCT/JP2012/068757
Other languages
French (fr)
Japanese (ja)
Inventor
山本　薫
誠二 金子
小川　康行
耕平 田中
誠一 内田
泰 高丸
森　重恭
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to CN201280048662.5A priority Critical patent/CN103843056B/en
Priority to JP2013526831A priority patent/JP6076253B2/en
Publication of WO2013018595A1 publication Critical patent/WO2013018595A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present invention relates to a display device and a driving method thereof, and more particularly, to a display device in which a display unit and a video signal line driving circuit are integrally formed and a driving method thereof.
  • a source driver for driving a source line (video signal line) of a liquid crystal display device is mounted as an IC (Integrated Circuit) chip on the periphery of a substrate constituting the liquid crystal panel.
  • IC Integrated Circuit
  • a liquid crystal display device provided with this monolithic source driver (hereinafter referred to as a “source driver monolithic liquid crystal display device”) is disclosed in, for example, Patent Document 1.
  • a-Si TFT a thin film transistor (hereinafter referred to as “a-Si TFT”) using amorphous silicon (a-Si) as a semiconductor layer has been conventionally employed as a driving element.
  • Patent Document 2 discloses a driving method of a display device in which a rest period T2 in which all gate lines are in a non-scanning state is provided after a scanning period T1 in which gate lines are scanned.
  • this idle period T2 no clock signal or the like is given to the gate driver.
  • the driving frequency of the gate line as a whole becomes about 30 Hz. For this reason, power consumption can be reduced.
  • an object of the present invention is to provide a display device in which a display unit and a video signal line driving circuit are integrally formed and a driving method thereof, with reduced power consumption.
  • a first aspect of the present invention is a display device, A plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and a display unit for displaying an image;
  • a video signal line driving circuit formed integrally with the display unit for driving the plurality of video signal lines;
  • a display control circuit for providing the video signal line driving circuit with a clock signal that periodically repeats an on level and an off level, and one or more predetermined number of video signals corresponding to an image to be displayed on the display unit;
  • the video signal line driving circuit includes: A shift register that sequentially turns on a plurality of output signals based on the clock signal; A plurality of sampling blocks each provided with the plurality of output signals, Each sampling block applies the predetermined number of video signals to the predetermined number of video signal lines based on the output signal received by the sampling block, The frequency of the clock signal in the idle period is lower than the frequency of the clock signal in the scanning period.
  • An amplitude of the clock signal in the pause period is smaller than an amplitude of the clock signal in the scanning period.
  • the pause period is longer than the scanning period.
  • each sampling block the output signal received by the sampling block is supplied to a control terminal, one of the predetermined number of video signals is supplied to a first conduction terminal, and one of the plurality of video signal lines It has one or more switching elements to which the second conduction terminal is connected.
  • Each sampling block has a plurality of the switching elements.
  • a sixth aspect of the present invention is the fifth aspect of the present invention,
  • the display unit displays a color image based on a plurality of primary colors;
  • the predetermined number of video signals respectively corresponding to the plurality of primary colors;
  • the number of the plurality of switching elements in each sampling block is the same number as the plurality of primary colors,
  • the display control circuit supplies the predetermined number of video signals different from each other to the first conduction terminals of the plurality of switching elements in each sampling block.
  • the display unit displays a color image based on a plurality of primary colors;
  • the number of the plurality of switching elements in each sampling block is an integer multiple of the plurality of primary colors;
  • the display control circuit has the predetermined number of images on the first conduction terminal of the switching element in which the second conduction terminal is connected to the video signal lines adjacent to each other among the plurality of switching elements in each sampling block. Video signals corresponding to different primary colors of the signals are respectively provided.
  • the video signal line driving circuit includes: A first video signal line driving circuit located on one side with respect to the display unit; And a second video signal line driving circuit positioned on the other side of the display unit.
  • the video signal line driver circuit is realized using a thin film transistor in which a semiconductor layer is formed of an oxide semiconductor.
  • the video signal line driving circuit is realized by using a thin film transistor in which a semiconductor layer is formed of amorphous silicon.
  • An eleventh aspect of the present invention includes a plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, a display unit for displaying an image, and an on level and an off level. And a display control circuit that outputs a predetermined number of video signals corresponding to an image to be displayed on the display unit, and a display control circuit that is formed integrally with the display unit, and that is based on the clock signal.
  • Video signal line driving circuit including a shift register for sequentially turning on the output signals of the plurality of output signals, and a plurality of sampling blocks to which the plurality of output signals are respectively applied, and scanning signal lines for driving the plurality of scanning signal lines
  • a driving method of a display device comprising a driving circuit, A scanning period in which the plurality of scanning signal lines are sequentially selected and a pause period in which all of the plurality of scanning signal lines are in a non-selected state alternate with a frame period that includes the scanning period and the pause period as a cycle.
  • a twelfth aspect of the present invention is the eleventh aspect of the present invention, An amplitude of the clock signal in the pause period is smaller than an amplitude of the clock signal in the scanning period.
  • a thirteenth aspect of the present invention is the eleventh aspect of the present invention,
  • the pause period is longer than the scanning period.
  • one frame period includes the scanning period and the pause period.
  • the frequency of the clock signal during this idle period is lower than the frequency of the clock signal during the scanning period. For this reason, the drive frequency of the selection circuit in the entire one frame period is reduced. Thereby, power consumption is reduced.
  • the display portion and the video signal line driving circuit are integrally formed, the frame area is reduced and the cost of the video signal line driving circuit is reduced.
  • the amplitude of the clock signal in the pause period is smaller than the amplitude of the clock signal in the scanning period. For this reason, further reduction in power consumption can be achieved.
  • the pause period becomes longer than the scanning period. For this reason, further reduction in power consumption can be achieved.
  • a sampling block can be realized by one or more switching elements.
  • a video signal is given to the switching element in the sampling block to which the output signal is given at the timing when the output signal of the shift register becomes high level based on the clock signal. For this reason, the influence of the noise etc. which a video signal line receives in an idle period is reduced. Thereby, the fall of display quality can be suppressed.
  • the frequency of the clock signal in the idle period is lower than that in the scanning period, the load applied to the switching element is reduced. Therefore, the threshold fluctuation in the switching element is reduced, so that a decrease in reliability of the switching element can be suppressed.
  • sequential driving can be performed in which video signals are simultaneously applied to a plurality of source lines.
  • the same effect as in the fifth aspect can be achieved.
  • a display device that displays an image based on a plurality of primary colors
  • video signals for an integral multiple of pixels composed of a plurality of primary colors are written at a time.
  • a sufficient pause period can be secured, or a video signal writing time can be secured sufficiently.
  • the number of sampling blocks can be reduced, the number of shift register stages can be reduced.
  • the number of stages of the video signal line driving circuit is halved. This doubles the layout pitch in the direction in which the scanning signal lines extend. Thereby, for example, high definition of the display unit can be achieved.
  • a video signal line driving circuit is realized using a thin film transistor in which a semiconductor layer is formed of an oxide semiconductor. Since the leakage current of the thin film transistor is sufficiently small, the frequency of the clock signal during the idle period can be further reduced. For this reason, further reduction in power consumption can be achieved. In addition, since the on-state current of the thin film transistor in which the semiconductor layer is formed using an oxide semiconductor is sufficiently large, the size of the thin film transistor can be sufficiently reduced. Thereby, further narrowing of the frame can be achieved.
  • a video signal line driving circuit is realized using a thin film transistor in which a semiconductor layer is formed of amorphous silicon. For this reason, further cost reduction can be achieved.
  • FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a first embodiment of the present invention. It is a block diagram for demonstrating the structure of the source driver in the said 1st Embodiment. It is a block diagram which shows the structure of the shift register in the said 1st Embodiment. It is a signal waveform diagram for demonstrating operation
  • the gate terminal of the thin film transistor corresponds to the control terminal
  • the drain terminal corresponds to the first conduction terminal
  • the source terminal corresponds to the second conduction terminal.
  • FIG. 1 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to a first embodiment of the present invention.
  • the liquid crystal display device includes a power source 100, a DC / DC converter 110, a display control circuit 200, a source driver (video signal line driving circuit) 300, a gate driver (scanning signal line driving circuit) 400, a common electrode driving circuit 500, and a display unit. 600.
  • the source driver 300 is formed on the liquid crystal display panel 700 including the display portion 600 using amorphous silicon, polycrystalline silicon, microcrystalline silicon, an oxide semiconductor (for example, IGZO), or the like. That is, in the liquid crystal display device according to this embodiment, the source driver 300 and the display unit 600 are formed on the same substrate (an array substrate that is one of the two substrates constituting the liquid crystal display panel). This is a source driver monolithic liquid crystal display device.
  • the gate driver 400 may also be formed over the liquid crystal display panel 700 using amorphous silicon, polycrystalline silicon, microcrystalline silicon, an oxide semiconductor, or the like. Specific implementation examples using these amorphous silicon and IGZO will be described later.
  • the display unit 600 includes n source lines (video signal lines) SL1 to SLn, m gate lines (scanning signal lines) GL1 to GLm, source lines SL1 to SLn, and gate lines GL1 to GLm.
  • M ⁇ n pixel forming portions provided corresponding to the respective intersections are formed.
  • the m ⁇ n pixel forming portions are arranged in a matrix to constitute a pixel array.
  • Each pixel forming portion includes a pixel thin film transistor 80 which is a switching element having a gate terminal connected to a gate line passing through a corresponding intersection and a source terminal connected to a source line passing through the intersection, and the pixel thin film transistor 80
  • a pixel electrode connected to the drain terminal, a common electrode Ec which is a counter electrode provided in common to the plurality of pixel formation portions, and a pixel electrode provided in common to the plurality of pixel formation portions.
  • the liquid crystal layer is sandwiched between the electrode Ec.
  • a pixel capacitor Cp is constituted by a liquid crystal capacitor formed by the pixel electrode and the common electrode Ec.
  • an auxiliary capacitor is provided in parallel with the liquid crystal capacitor in order to reliably hold the voltage in the pixel capacitor Cp.
  • the auxiliary capacitor is not directly related to the present invention, its description and illustration are omitted.
  • the pixel forming portion is configured as a set of three pixel forming portions corresponding to R, G, and B, respectively.
  • One pixel is formed by this one set.
  • the pixel formation portions corresponding to R, G, and B are referred to as “R pixel formation portion”, “G pixel formation portion”, and “B pixel formation portion”, respectively.
  • the power supply 100 supplies a predetermined power supply voltage to the DC / DC converter 110, the display control circuit 200, and the common electrode drive circuit 500.
  • the DC / DC converter 110 generates a predetermined DC voltage for operating the source driver 300 and the gate driver 400 from the power supply voltage and supplies it to the source driver 300 and the gate driver 400.
  • the common electrode drive circuit 500 gives a predetermined potential Vcom to the common electrode Ec.
  • the display control circuit 200 receives an image signal DAT and a timing signal group TG such as a horizontal synchronization signal and a vertical synchronization signal sent from the outside, and receives a video signal Vid and a source start pulse signal for controlling image display on the display unit 600.
  • the SSP, the source clock signal SCK, the gate start pulse signal GSP, and the gate clock signal GCK are output.
  • the high level potential of the source clock signal SCK is Vdd potential
  • the low level potential is Vss potential.
  • the source clock signal SCK is composed of two-phase source clock signals SCK1 and SCK2.
  • the source clock signal SCK1 is referred to as a “first source clock signal”
  • the source clock signal SCK2 is referred to as a “second source clock signal”.
  • the period from the time when each of the first source clock signal SCK1 and the second source clock signal SCK2 changes from the low level potential to the high level potential until the time when the high level potential changes to the low level potential is referred to as the “sampling period”.
  • the first source clock signal SCK1 and the second source clock signal SCK2 are out of phase with each other by one sampling period, and both are at a high level potential (Vdd potential) only for one sampling period among the two sampling periods (however, , Except for a rest period T2 described later).
  • the source driver 300 receives the video signal Vid, the source start pulse signal SSP, and the source clock signal SCK output from the display control circuit 200.
  • the source driver 300 supplies the received video signal Vid to the source lines SL1 to SLn at a predetermined timing.
  • This video signal Vid includes three video signals Vidr, Vidg, and Vidb.
  • the video signal Vidr is referred to as “R video signal”
  • the video signal Vidg is referred to as “G video signal”
  • the video signal Vidb is referred to as “B video signal”.
  • the R video signal Vidr, the G video signal Vidg, and the B video signal Vidb correspond to the R pixel forming unit, the G pixel forming unit, and the B pixel forming unit, respectively.
  • the source driver 300 in this embodiment performs so-called dot sequential driving. A detailed description of this source driver will be described later.
  • the gate driver 400 Based on the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 200, the gate driver 400 supplies the high-level potential scanning signals GS (1) to GS (m) to the gate lines GL1 to GLm, respectively. Is repeated with one frame period as a cycle.
  • a period (one horizontal scanning period) in which a high level potential is applied to each gate line and the gate line is in a selected state is referred to as a “scanning selection period”.
  • a period during which the gate line GLi is in a selected state one horizontal scanning period
  • one frame period includes a scanning period T1 and a pause period T2 provided after the scanning period T1.
  • the gate driver 400 sequentially sets the scanning signals GS (1) to GS (m) to the high level potential based on the gate clock signal GCK.
  • the gate driver 400 sets the m gate lines GL1 to GLm (scanning signals GS (1) to GS (m)) to a low level potential.
  • the video signals are applied to the source lines SL1 to SLn, and the scanning signals GS (1) to GS (m) are applied to the gate lines GL1 to GLm, respectively.
  • An image based on DAT is displayed on the display unit 600.
  • FIG. 2 is a block diagram showing the configuration of the source driver 300 in this embodiment. As shown in FIG. 2, the source driver 300 includes a shift register 310 and a sampling circuit 320.
  • the shift register 310 receives the source start pulse signal SSP and the source clock signal SCK output from the display control circuit 200.
  • the shift register 310 sequentially transfers pulses included in the source start pulse signal SSP from the input end to the output end based on the source start pulse signal SSP and the source clock signal SCK.
  • the selection signals SEL (1) to SEL (k) which are output signals of the shift register 310, sequentially become a high level potential. These selection signals SEL (1) to SEL (k) are applied to the sampling circuit 320.
  • the sampling circuit 320 receives the selection signals SEL (1) to (k) output from the shift register 310 and the video signal Vid output from the display control circuit 200.
  • the sampling circuit 320 supplies the video signal Vid to the source lines SL1 to SLn at the timing when these selection signals SEL (1) to (k) become the high level potential.
  • FIG. 3 is a block diagram showing a configuration of the shift register 310 in the present embodiment.
  • the shift register 310 includes k bistable circuits 30 (1) to 30 (k) and one dummy bistable circuit 30 (k + 1).
  • the k + 1th stage may be referred to as a “dummy stage”.
  • Each bistable circuit is in one of two states (first state and second state) at each time point, and a signal indicating the state (hereinafter referred to as a “state signal”). Output.
  • a bistable circuit if the bistable circuit is in the first state, a high-level (on-level) potential state signal is output from the bistable circuit, and the bistable circuit is in the second state. Then, a state signal having a low level (off level) potential is output from the bistable circuit.
  • This state signal corresponds to the selection signal described above. That is, the state signals of the bistable circuits 30 (1) to 30 (k) correspond to the selection signals SEL (1) to SEL (k), respectively.
  • Each bistable circuit has an input terminal for receiving a clock signal CK1 (hereinafter referred to as “first clock signal”), an input terminal for receiving a clock signal CK2 (hereinafter referred to as “second clock signal”), An input terminal (not shown) for receiving a DC power supply potential Vss (the magnitude of this potential is also referred to as the “Vss potential”), an input terminal for receiving a set signal S, and an input for receiving a reset signal R A terminal and an output terminal for outputting a status signal Z are provided.
  • the shift register 310 is supplied with the two-phase first source clock signal SCK1 and second source clock signal SCK2 as the source clock signal SCK as described above.
  • this invention is not limited to this, It is good also as an aspect using the source clock signal of 3 phases or more.
  • the signals given to the input terminals of each stage (each bistable circuit) of the shift register 310 are as follows. That is, the first source clock signal SCK1 is provided as the first clock signal CK1, and the second source clock signal SCK2 is provided as the second clock signal CK2. In the even-numbered stage, the first source clock signal SCK1 is supplied as the second clock signal CK2, and the second source clock signal SCK2 is supplied as the first clock signal CK1. Further, a low level DC power supply potential Vss is commonly applied to each stage by means not shown.
  • the status signal Z output from the previous stage is given as the set signal S, and the status signal Z outputted from the next stage is given as the reset signal R.
  • the source start pulse signal SSP is given as the set signal S to the first stage (frontmost stage) 30 (1).
  • the source start pulse signal SSP is a signal that becomes a high level potential in the first sampling period in each scanning selection period.
  • a state signal output from the dummy stage 30 (k + 1) is given as a reset signal R to the k-th stage (last stage) 30 (k).
  • the dummy stage 30 (k + 1) is given the state signal Z output from the k-th stage 30 (k) as the set signal S, and its own state signal Z is given as the reset signal R.
  • the period in which the state signal Z of the dummy stage 30 (k + 1) is at the high level potential is shorter than the period in which the state signal Z of the other stage is at the high level potential.
  • the source end pulse signal SEP may be given as the reset signal R to the k-th stage 30 (k).
  • the source end pulse signal SEP is a signal that becomes a high level potential in one sampling period after the end of the k-th scanning selection period.
  • the source start pulse signal SSP as the set signal S is supplied to the first stage 30 (1) of the shift register 310, based on the first source clock signal SCK1 and the second source clock signal SCK2.
  • the pulses included in the source start pulse signal SSP (this pulse is included in the status signal Z output from each stage) are sequentially transferred from the first stage 30 (1) to the kth stage 30 (k).
  • the state signals Z output from the first stage 30 (1) to the kth stage 30 (k) are sequentially set to the high level potential.
  • the state signals Z output from the first stages 30 (1) to 30 (k) are supplied to the sampling circuit 320 as selection signals SEL (1) to SEL (k). As described above, as shown in FIG.
  • a selection signal that sequentially becomes a high level potential is supplied to the sampling circuit 320 for each sampling period.
  • a period during which each selection signal is at a high level potential is referred to as a “sampling selection period”.
  • a period during which the selection signal SEL (j) is at a high level is referred to as a “jth sampling selection period”.
  • FIG. 5 is a circuit diagram showing a configuration of each bistable circuit in the present embodiment.
  • the bistable circuit includes four thin film transistors (switching elements) M1 to M4, a capacitor C1, four input terminals 31 to 34, an input terminal for a low-level DC power supply potential Vss, and An output terminal 39 is used.
  • the input terminal that receives the first clock signal CK1 is denoted by reference numeral 31
  • the input terminal that receives the second clock signal CK2 is denoted by reference numeral 32
  • the input terminal that receives the set signal S is denoted by reference numeral 33.
  • the input terminal that receives the reset signal R is denoted by reference numeral 34.
  • reference numeral 39 is attached to an output terminal for outputting the status signal Z.
  • the bistable circuit of the shift register 310 is not limited to the configuration of the bistable circuit in the present embodiment, and bistable circuits having various configurations can be employed.
  • the gate terminal of the thin film transistor M1, the source terminal of the thin film transistor M3, the drain terminal of the thin film transistor M4, and one end of the capacitor C1 are connected to each other.
  • a connection point (wiring) where these are connected to each other is referred to as a “first node” for convenience.
  • the first node is denoted by reference numeral N1.
  • the gate terminal is connected to the first node N1, the drain terminal is connected to the input terminal 31, and the source terminal is connected to the output terminal 39.
  • the gate terminal is connected to the input terminal 32, the drain terminal is connected to the output terminal 39, and the source terminal is connected to the input terminal for the DC power supply potential Vss.
  • the gate terminal and the drain terminal are connected to the input terminal 33 (that is, diode connection), and the source terminal is connected to the first node N1.
  • the thin film transistor M4 has a gate terminal connected to the input terminal 34, a drain terminal connected to the first node N1, and a source terminal connected to the input terminal for the DC power supply potential Vss.
  • the capacitor C1 has one end connected to the first node N1 and the other end connected to the output terminal 39.
  • the thin film transistor M1 applies the potential of the first clock signal CK to the output terminal 39 when the potential of the first node N1 is at a high level.
  • the thin film transistor M2 changes the potential of the output terminal 39 toward the Vss potential when the potential of the second clock signal CK2 is at a high level.
  • the thin film transistor M3 changes the potential of the first node N1 toward the high level when the potential of the set signal S is at the high level.
  • the thin film transistor M4 changes the potential of the first node N1 toward the Vss potential when the potential of the reset signal R is at a high level.
  • the capacitor C1 functions as an auxiliary capacitor when the first node N1 is bootstrapped.
  • FIG. 6 is a signal waveform diagram for explaining the operation in the scanning period T1 among the operations of the bistable circuit in the present embodiment. Since the operation of other bistable circuits is the same, the description thereof is omitted.
  • this bistable circuit will be described as an odd-numbered stage. In the odd-numbered stages, the first source clock signal SCK1 and the second source clock signal SCK2 correspond to the first clock signal CK1 and the second clock signal CK2, respectively.
  • a period from time t1 to time t2 in FIG. 6 corresponds to a sampling selection period.
  • one sampling period immediately before the sampling selection period is referred to as a “set period”, and one sampling period immediately after the sampling selection period is referred to as a “reset period”.
  • a period other than the selection period, the set period, and the reset period in the scanning period is referred to as a “normal operation period”.
  • the potential of the set signal S changes from low level to high level. Since the thin film transistor M3 is diode-connected as shown in FIG. 5, when the potential of the set signal S goes high, the thin film transistor M3 is turned on and the capacitor C1 is charged (here, precharged). As a result, the potential of the first node N1 changes from the low level to the high level, and the thin film transistor M1 is turned on. However, in the set period, since the potential of the first source clock signal SCK1 (first clock signal CK1) is at a low level, the potential of the state signal Z is maintained at a low level.
  • the set signal S changes from high level to low level.
  • the thin film transistor M3 is turned off.
  • the first node N1 is in a floating state.
  • the potential of the first source clock signal SCK1 changes from the low level to the high level. Since the thin film transistor M1 is in an on state and has a gate capacitance, the potential of the first node N1 increases as the potential of the input terminal 31 increases (the first node N1 is bootstrapped).
  • the capacitor C1 works to promote the potential rise of the first node N1.
  • the gate potential of the thin film transistor M1 becomes sufficiently high, so that the potential of the state signal Z rises to the high level (Vdd potential) of the first source clock signal SCK1.
  • the potential of the first source clock signal SCK1 changes from high level to low level. Since the thin film transistor M1 is in the on state at time t2, the potential of the state signal Z decreases as the potential of the input terminal 31 decreases. As the potential of the state signal Z decreases in this way, the potential of the first node N1 also decreases via the capacitor C1. In the reset period, the reset signal R changes from a low level to a high level. For this reason, the thin film transistor M4 is turned on. As a result, during the reset period, the potential of the first node N1 is reliably lowered to a low level.
  • the second source clock signal SCK2 (second clock signal CK2) changes from the low level to the high level. For this reason, since the thin film transistor M2 is turned on, the potential of the state signal Z is reliably lowered to a low level.
  • the potential of the second source clock signal SCK2 repeats a high level and a low level every horizontal scanning period, so that the thin film transistor M2 is turned on every horizontal scanning period. For this reason, the potential of the state signal Z can be maintained at a low level.
  • each cycle of the first source clock signal SCK1 and the second source clock signal SCK2 in the scanning period T1 (hereinafter referred to as “scanning period cycle”) is represented by a reference tck1.
  • the respective frequencies of the first gate clock signal GCK1 and the second gate clock signal GCK2 in the scanning period T1 (hereinafter referred to as “scanning period frequency”) are denoted by reference numeral fck1.
  • the respective amplitudes of the first source clock signal SCK1 and the second source clock signal SCK2 in the scanning period T1 (hereinafter referred to as “scanning period amplitude”) are represented by reference sign Vck1.
  • FIG. 7 is a circuit diagram for explaining the configuration of the sampling circuit 320 in the present embodiment.
  • the sampling circuit 320 includes k sampling blocks 40 (1) to 40 (k).
  • the display unit 600 is formed with a pixel matrix of m rows ⁇ n columns, and the sampling blocks are provided so as to correspond to the columns of these pixel matrices in a three-to-one correspondence.
  • the source lines SL1 to SLn are grouped into source line groups SG1 to SGk in units of three.
  • the source line set SGj includes three source lines SL3j-2 to SL3j. These source line sets SG1 to SGk correspond to the sampling blocks 40 (1) to 40 (k), respectively.
  • a source line corresponding to R hereinafter referred to as “R source line” in the source line set SGj is represented by reference sign SLrj
  • G source line a source line corresponding to G
  • a source line corresponding to B (hereinafter referred to as a “B source line”) is represented by a symbol SLbj.
  • the G pixel formation portion provided corresponding to is represented by reference symbol gij
  • the B pixel formation portion provided corresponding to the intersection of the B source line SLbj and the gate line GLi is represented by reference symbol bij.
  • each sampling block is composed of three thin film transistors.
  • the three thin film transistors in the sampling block 40 (j) are referred to as “R thin film transistor 41r (j)”, “G thin film transistor 41g (j)”, and “B thin film transistor 41b (j)”, respectively.
  • a selection signal corresponding to the sampling block including the R thin film transistor is given to the gate terminal, an R video signal Vidr is given to the source terminal, and the R thin film transistor is given to the drain terminal.
  • R source lines in a source line set corresponding to the sampling block to be included are connected.
  • a gate terminal receives a selection signal corresponding to the sampling block including the G thin film transistor, a source terminal receives a G video signal Vidg, and a drain terminal receives the G thin film transistor.
  • G source lines in the source line set corresponding to the sampling block to be included are connected.
  • the gate terminal is supplied with a selection signal corresponding to the sampling block including the B thin film transistor, the source terminal is supplied with the B video signal Vidb, and the drain terminal is supplied with the B thin film transistor.
  • a source line for B in the source line set corresponding to the included sampling block is connected.
  • the source driver 300 including such a sampling circuit 320 realizes dot-sequential driving in which the video signal Vid is sequentially supplied to the source line in units of picture elements composed of R / G / B pixels in one horizontal scanning period. This operation will be described in detail later.
  • one frame period is composed of the scanning period T1 and the pause period T2 provided after the scanning period T1.
  • the operation of the liquid crystal display device according to the present embodiment will be described separately for the operation in the scanning period T1 and the operation in the pause period T2.
  • FIG. 8 is a signal waveform diagram for explaining the operation in the scanning period T1 of the liquid crystal display device according to this embodiment.
  • the scanning signals GS (1) to GS (m) are sequentially selected based on the gate clock signal GCK.
  • video signals are sequentially applied to the source line in block units (source group units).
  • FIG. 8 shows various signal waveforms related to driving of the source driver 300 in the first scan selection period. The operation in the scan selection period other than the first scan selection period is the same, and the description thereof is omitted.
  • the source start pulse signal SSP becomes a high level potential in the first sampling period.
  • the selection signals SEL (1) to SEL (k) sequentially become a high level potential.
  • the scanning period cycle tck1 is two sampling periods.
  • the G video signal Vidg has a potential corresponding to the G pixel forming portion gij in the jth sampling period in the i-th scanning selection period.
  • the B video signal Vidb has a potential corresponding to the B pixel formation portion bij in the jth sampling period in the i-th scanning selection period.
  • the polarity of each video signal is inverted every sampling period, the polarities of the video signals applied to the output signal lines adjacent to each other are inverted, and every frame period.
  • the polarity inversion drive is performed by inverting the polarity of each video signal, the present invention is not limited to this.
  • the selection signal SEL (1) is at a high level potential in the first sampling period, the R thin film transistor 41r (1), the G thin film transistor 41g (1), and the B use in the sampling block 40 (1) shown in FIG.
  • the thin film transistor 41b (1) is turned on. For this reason, the R video signal Vidr having a potential corresponding to the R pixel formation portion r11 is given to the R source line SLr1, and the G video signal Vidg having a potential corresponding to the G pixel formation portion g11 is obtained.
  • the B video signal Vidb which is given to the G source line SLg1 and has a potential corresponding to the B pixel formation portion b11, is given to the B source line SLb1.
  • the potentials of the R source line SLr1, the G source line SLg1, and the B source line SLb1 are positive, negative, and negative, respectively, from the potential (Vcom potential) in the preceding pause period T2. Change to positive polarity.
  • the potentials of the R source line SLr1, the G source line SLg1, and the B source line SLb1 are written to the R pixel forming portion r11, the G pixel forming portion g11, and the B pixel forming portion b11, respectively. Since the operation in the second to m sampling periods is the same, the description thereof is omitted.
  • the operation of one scanning selection period is realized by repeating the one sampling period as described above, and the operation of the scanning period T1 is realized by repeating this one scanning selection period.
  • FIG. 9 is a signal waveform diagram for explaining the operation in the pause period T2 of the liquid crystal display device according to the present embodiment.
  • the pause period T2 is longer than the scanning period T1.
  • the present invention is not limited to this, and the pause period T2 may be shorter than the scanning period T1.
  • X horizontal scanning period a period corresponding to the length of the first X scanning selection period (one horizontal scanning period) in the pause period T ⁇ b> 2.
  • the signal waveform is shown.
  • X is, for example, an integer of 2 or more, but the present invention is not limited to this.
  • the operation in the other X horizontal scanning periods is the same, and the description thereof is omitted.
  • the first source clock signal SCK1 and the second source clock signal SCK2 are at a high level potential in one sampling period with a period longer than the scanning period period tck1.
  • pause period cycle each cycle of the first source clock signal SCK1 and the second source clock signal SCK2 in the pause period T2 (hereinafter referred to as “pause period cycle”) is denoted by reference symbol tck2.
  • pause period frequencies the respective frequencies (hereinafter referred to as “pause period frequencies”) of the first source clock signal SCK1 and the second source clock signal SCK2 in the idle period T2 are denoted by a symbol fck2.
  • pause period amplitude the respective amplitudes (hereinafter referred to as “pause period amplitude”) of the first source clock signal SCK1 and the second source clock signal SCK2 in the pause period T2 are represented by reference sign Vck2.
  • the idle period cycle tck2 is longer than the scanning period cycle tck1. That is, the idle period frequency fck2 is lower than the scanning period frequency fck1.
  • the scanning period frequency fck1 is an integral multiple of the idle period frequency fck2.
  • the display control circuit 200 and the like can have a simple configuration.
  • the scanning period frequency fck1 is at least twice the idle period frequency fck2.
  • the idle period frequency fck2 is 1 ⁇ 2 times or less of the scanning period frequency fck1.
  • the power consumption required for driving the source driver 300 can be sufficiently reduced.
  • Such control of the frequency (cycle) of the source clock signal SCK is performed in the display control circuit 200, for example.
  • the idle period amplitude Vck2 and the scanning period amplitude Vck1 are the same.
  • the R video signal Vidr, the G video signal Vidg, and the B video signal Vidb are at the Vcom potential.
  • the potential is not limited to the Vcom potential, and may be another fixed potential.
  • the scanning signals GS (1) to GS (m) do not become a high level potential during the pause period T2, the video signal is written to the R pixel forming portion rij, the G pixel forming portion gij, and the B pixel forming portion bij. Absent.
  • the source start pulse signal SSP becomes a high level potential in the first sampling period in the X horizontal scanning period. Therefore, the selection signals SEL (1) to SEL (k) are sequentially set to the high level potential on the basis of the first source clock signal SCK1 and the second source clock signal SCK2 having the idle period frequency fck2 lower than the scanning period frequency fck1. Become.
  • FIG. 10 is a signal waveform diagram for explaining the operation of the bistable circuit in the present embodiment, in particular, the operation in the idle period T2. Since the operation of other bistable circuits is the same, the description thereof is omitted.
  • one horizontal scanning period in which the set signal S is at a high level potential is referred to as a “set period”, and a period from the end of the set period to the start of the sampling selection period is “selected”.
  • the period from the end of the sampling selection period to the time when the reset signal R changes to the high level potential is called the “waiting period”, and the period during which the reset signal R is at the high level potential Period.
  • a period other than the sampling selection period, the set period, the selection waiting period, the reset waiting period, and the reset period in the suspension period T2 is referred to as a “normal operation period”.
  • the operation in the set period (time points s0 to s1) is the same as the operation in the set period in the scanning period T1, and thus description thereof is omitted.
  • the potential of the set signal S changes from high level to low level, so that the thin film transistor M3 is turned off (see FIG. 5). For this reason, the first node N1 is in a floating state. Further, the first source clock signal SCK1 remains at a low level potential. For this reason, in the selection waiting period, the potential of the first node N1 in the set period is maintained. Note that since the potential of the second source clock signal SCK2 changes to a low level, the thin film transistor M2 is turned off.
  • the potential of the first source clock signal SCK1 changes from the high level to the low level, so that the potential of the first node N1 is influenced by the parasitic capacitance between the gate and the drain of the thin film transistor M1. Descends. This amount of decrease in potential corresponds to the amount of increase in potential due to the above-described boost strap. For this reason, the thin film transistor M1 is not turned off. Therefore, as described above, when the potential of the first source clock signal SCK1 changes from the high level to the low level, the potential of the state signal Z changes to the low level. Further, after that, the potential of the first source clock signal SCK1 is maintained at the low level, so that the potential of the state signal Z is maintained at the low level.
  • the selection signals SEL (1) to SEL (k) are sequentially set to the high level potential in a period longer than the period in the scanning period T1. Therefore, the R thin film transistor, the G thin film transistor, and the B thin film transistor in each of the sampling blocks 40 (1) to 40 (k) are sequentially turned on.
  • the R thin film transistor is turned on, the R video signal Vidr having the Vcom potential is applied to the R source line.
  • the G thin film transistor is turned on, the G video signal Vidg at the Vcom potential is applied to the G source line.
  • the B thin film transistor is turned on, the B video signal Vidb at the Vcom potential is applied to the B source line.
  • the scanning signals GS (1) to GS (m) do not become high level potentials in the idle period T2, and therefore the potentials of these R source line, G source line, and B source line are R respectively. It is not written in the pixel formation portion, the G pixel formation portion, and the B pixel formation portion.
  • the source line is in a floating state. For this reason, the source line is likely to be affected by noise or the like in the pause period T2. Since there is a parasitic capacitance between the source line and the pixel electrode, and the pixel electrode is also in a floating state, noise in the source line also affects the pixel potential due to capacitive coupling. As a result, the display quality may be degraded.
  • the selection signals SEL (1) to SEL (k) are generated by the shift register 310 operating on the first source clock signal SCK1 and the second source clock signal SCK2 in the pause period T2. Sequentially becomes a high level potential.
  • the Vcom potential is applied to the source line in the source line group corresponding to each selection signal at the high level.
  • the influence of noise and the like received by the source lines SL1 to SLm is reduced by the source lines SL1 to SLm being in the floating state in the pause period T2.
  • each thin film transistor in the sampling circuit 320 is kept on during the rest period T2 and each video signal is set to the Vcom potential, it is necessary to continuously apply a high level potential to the gate terminal of the thin film transistor. Since the gate bias stress is applied to the thin film transistor for a long time, the threshold fluctuation in the thin film transistor is increased. As a result, the thin film transistor is lowered.
  • the shift register 310 operates based on the first source clock signal SCK1 and the second source clock signal SCK2 in the pause period T2, so that the selection signal SEL ( 1) to SEL (k) sequentially become high level potentials.
  • the high level potential is applied to the gate terminal of the thin film transistor in the sampling circuit 320 only in one sampling period in each X horizontal scanning period.
  • a-Si or an oxide semiconductor can be used for the semiconductor layer of each thin film transistor in the sampling circuit 320 in the present embodiment.
  • the oxide semiconductor typically, InGaZnO x (hereinafter referred to as “IGZO”), which is an oxide semiconductor mainly containing indium, gallium, zinc, and oxygen, is used. It is not limited. For example, any oxide semiconductor containing at least one of indium, gallium, zinc, copper, silicon, tin, aluminum, calcium, germanium, and lead may be used.
  • FIG. 11 is a graph showing drain current-gate voltage characteristics of a TFT using a-Si TFT and IGZO as a semiconductor layer (hereinafter referred to as “IGZOTFT”).
  • the horizontal axis represents the gate voltage Vg
  • the vertical axis represents the drain current Ids.
  • the leakage current of the IGZOTFT is 1/1000 or less of the leakage current of the a-Si TFT
  • the on-current of the IGZOTFT is about 20 times the on-current of the a-Si TFT.
  • the IGZOTFT has a small leakage current as described above, when the IGZOTFT is used as each thin film transistor in the sampling circuit 320 in the present embodiment, the source driver 300 (sampling circuit 320 is used even when the a-Si TFT is used as this thin film transistor. ) Driving power can be reduced (1/100 or less).
  • the IGZOTFT has a large on-state current as described above, when the IGZOTFT is used, the size of the TFT can be reduced to about 1/20 compared to the case where the a-Si TFT is used.
  • this embodiment can be realized at a lower cost than when an IGZO TFT is used.
  • the pause period T2 is provided after the scanning period T1 within one frame period. Since the idle period frequency fck2 is lower than the scanning period frequency fck1, the driving frequency of the entire source frame of the source driver 300 is reduced. For this reason, the power consumption required for driving the source driver 300 is reduced. Further, since the source driver 300 is monolithically formed, the frame area of the liquid crystal display panel 700 is reduced and the cost of the source driver 300 is reduced.
  • the Vcom potential is applied to the source line in the corresponding source line group at the timing when each selection signal becomes high level in the pause period T2. For this reason, since the source lines SL1 to SLm are in the floating state in the suspension period T2, the influence of noise and the like received by these source lines SL1 to SLm is reduced. Thereby, the fall of display quality can be suppressed.
  • the high level potential is applied to the gate terminal of each thin film transistor in the sampling circuit 320 only in one sampling period in each X horizontal scanning period in the pause period T2, the gate bias stress applied to the thin film transistor is reduced. . As a result, a decrease in driving capability (reliability) of each thin film transistor in the sampling circuit 320 can be suppressed.
  • the pause period T2 is provided longer than the scanning period T1, further power consumption can be achieved.
  • the leakage current of the IGZOTFT is sufficiently small, so that the idle period frequency fck2 can be further reduced. For this reason, power consumption can be reduced.
  • the TFT size can be sufficiently reduced. Thereby, further narrowing of the frame can be achieved. Note that by using the IGZOTFT as each thin film transistor in the bistable circuit, further reduction in power consumption and narrowing of the frame can be achieved.
  • the cost can be further reduced.
  • FIG. 12 is a signal waveform diagram for explaining the operation in the pause period T2 of the liquid crystal display device according to the second embodiment of the present invention. Since the present embodiment is the same as the first embodiment except for the operation during the suspension period, the description of the same portion is omitted.
  • the pause period amplitude Vck2 is smaller than the scanning period amplitude Vck1. Note that, in order to ensure that each thin film transistor in the sampling circuit 320 is turned on in the pause period T2, it is necessary to be higher than the threshold voltage of this thin film transistor. That is, the pause period amplitude Vck in this embodiment is smaller than the scanning period amplitude Vck2 and larger than the threshold voltage of each thin film transistor in the sampling circuit 320.
  • the pause period amplitude Vck2 which is the amplitude of each of the first source clock signal SCK1 and the second source clock signal SCK2 in the pause period T2, is the first source clock signal SCK1 and the second source in the scan period T1. It is smaller than the scanning period amplitude Vck1 that is the amplitude of each of the clock signals SCK2. For this reason, further reduction in power consumption can be achieved.
  • the gate bias stress applied to the R thin film transistor, the G thin film transistor, and the B thin film transistor is further reduced during the suspension period T2, the R thin film transistor, the G thin film transistor, and the B thin film transistor are further improved in reliability. Can be achieved.
  • FIG. 13 is a circuit diagram for explaining the configuration of the sampling circuit 320 according to the third embodiment of the present invention. Since this embodiment is the same as the first embodiment except for the configuration of the sampling circuit 320 and the detailed operation of the liquid crystal display device, the description of the same parts is omitted. In this embodiment, the relationship between the sampling blocks 40 (1) to 40 (k) and the source lines SL1 to SLn is different from that in the first embodiment, and sampling is performed so as to correspond to each column of the pixel matrix on a one-to-one basis. Blocks are provided.
  • the video signal Vid includes 24 video signals Vidr1 to Vidr8, Vidg1 to Vidg8, and Vidb1 to Vidb8.
  • the video signal Vidrx is referred to as “xR video signal”
  • the video signal Vidigx is referred to as “xG video signal”
  • the first to eighth R video signals Vidr1 to Vidr8 correspond to the R pixel forming unit
  • the first to 8G video signals Vidg1 to Vidg8 correspond to the G pixel forming unit
  • the first to 8B video signals Vidb1 to Vidb8 are This corresponds to the B pixel forming portion.
  • the source lines SL1 to SLn are grouped into source line groups SG1 to SGk in units of 24.
  • the source line set SGj is composed of 24 source lines SL24j-23 to SL24j.
  • These source line sets SG1 to SGk correspond to the sampling blocks 40 (1) to 40 (k), respectively.
  • eight source lines corresponding to the same color are provided in each source line group.
  • xG source lines eight G source lines in the source line set SGj
  • xB source lines eight B source lines in the source line set SGj
  • SLbj_x eight B source lines in the source line set SGj
  • an R pixel forming portion provided corresponding to the intersection of the xR source line SLrj_x and the gate line GLi is denoted by rij_x (i to m), and the intersection of the xG source line SLgj_x and the gate line GLi.
  • a G pixel forming portion provided for the xb is represented by reference symbol gij_x
  • a G pixel forming portion provided corresponding to the intersection of the xb source line SLbj_x and the gate line GLi is represented by bij_x.
  • Each sampling block is composed of 24 thin film transistors as shown in FIG.
  • the gate terminal For each xR thin film transistor, the gate terminal is supplied with a selection signal corresponding to the sampling block including the xR thin film transistor, the source terminal is supplied with the xR video signal Vidrx, and the drain terminal is supplied with the second signal.
  • the xR source line in the source line set corresponding to the sampling block including the xR thin film transistor is connected.
  • the gate terminal For each xG thin film transistor, the gate terminal is supplied with a selection signal corresponding to the sampling block including the xG thin film transistor, the source terminal is supplied with the xG video signal Vidgx, and the drain terminal is supplied with the corresponding second signal.
  • the xG source line in the source line set corresponding to the sampling block including the xG thin film transistor is connected.
  • a selection signal corresponding to the sampling block including the xB thin film transistor is given to the gate terminal, the xB video signal Vidbx is given to the source terminal, and the corresponding xth video signal Vidbx is given to the drain terminal.
  • the xB source line in the source line set corresponding to the sampling block including the xB thin film transistor is connected.
  • the source driver 300 including such a sampling circuit 320 realizes block sequential driving in which a video signal Vid is sequentially applied to a source line in block units (source group units) and a plurality of picture elements are simultaneously written in one horizontal scanning period. The This operation will be described in detail later.
  • FIG. 14 is a signal waveform diagram for explaining the operation in the scanning period T1 of the liquid crystal display device according to this embodiment.
  • the description of the common parts with the first embodiment is omitted as appropriate.
  • FIG. 14 shows various signal waveforms related to driving of the source driver 300 in the first scan selection period. The operation in the scan selection period other than the first scan selection period is the same, and the description thereof is omitted.
  • the xG video signal Vidgx has a potential corresponding to the xG pixel forming unit gij_x in the jth sampling period in the i-th scanning selection period.
  • the xB video signal Vidbx has a potential corresponding to the xB pixel formation portion bij_x in the jth sampling period in the i-th scanning selection period.
  • the selection signal SEL (1) becomes a high level potential in the first sampling period
  • the xB thin film transistor 41bx (1) is turned on.
  • the xR video signal Vidrx having a potential corresponding to the R pixel forming portion r11_x is supplied to the xR source line SLr1_x, and the xG video having a potential corresponding to the G pixel forming portion g11_x.
  • the signal Vidx is supplied to the xG source line SLg1_x, and the xB video signal Vidbx having a potential corresponding to the B pixel formation portion b11_x is supplied to the xB source line SLb1_x.
  • the potentials of the xR source line SLr1_x, the xG source line SLg1_x, and the xB source line SLb1_x change from the potential (Vcom potential) in the preceding pause period T2 to a positive polarity or a negative polarity. Change.
  • the potentials of the xR source line SLr1_x, the xG source line SLg1_x, and the xB source line SLb1_x are written to the R pixel formation portion r11_x, the G pixel formation portion g11_x, and the B pixel formation portion b11_x, respectively. Since the operation in the second to m sampling periods is the same, the description thereof is omitted.
  • the operation of one scanning selection period is realized by repeating the one sampling period as described above, and the operation of the scanning period T1 is realized by repeating this one scanning selection period.
  • FIG. 15 is a signal waveform diagram for explaining the operation in the pause period T2 of the liquid crystal display device according to the present embodiment.
  • the xR Vidrx, the xG Viggx, and the xB Vidbx are at the Vcom potential in the suspension period T2. Note that the potential is not limited to the Vcom potential, and may be another fixed potential.
  • the xR thin film transistor is turned on, the xR video signal Vidrx having the Vcom potential is applied to the xR source line.
  • the xG thin film transistor is turned on, the xG video signal Vidgx at the Vcom potential is applied to the xG source line.
  • the xB video signal Vidbx having the Vcom potential is applied to the xB source line.
  • the scanning signals GS (1) to GS (m) do not become a high level potential in the pause period T2, and therefore, the potentials of the xR source line, the xG source line, and the xB source line. Are not written in the R pixel forming portion, the G pixel forming portion, and the B pixel forming portion, respectively.
  • the number of pixel forming portions in which a video signal can be written at a time is increased as compared with the first embodiment. For this reason, it is possible to secure a sufficient rest period T2 by shortening the scanning period T1 compared to the first embodiment, or to provide the scanning period T1 having the same length as that of the first embodiment. As a result, it is possible to secure a sufficient video signal writing time for each pixel formation portion. Further, the number of stages of the shift register 310 can be reduced by reducing the number of sampling blocks.
  • FIG. 16 is a circuit diagram for explaining a configuration of a source driver 300 according to the fourth embodiment of the present invention. Since this embodiment is the same as the first embodiment except for the configuration of the source driver 300, the description of the same portion is omitted.
  • the source driver 300 in the present embodiment is divided into both sides (upper and lower sides in FIG. 16) of the display unit 600.
  • a portion of the source driver 300 that is disposed on the upper side of the display unit 600 is referred to as a “first source driver” and is denoted by reference numeral 300a.
  • a portion of the source driver 300 that is disposed below the display unit 600 is referred to as a “second source driver” and is denoted by reference numeral 300 b.
  • the shift register 310 in the present embodiment is configured separately on both sides of the display unit 600.
  • a portion of the shift register 310 that is disposed on the upper side of the display unit 600 is referred to as a “first shift register” and is denoted by reference numeral 310a.
  • a portion of the shift register 310 disposed below the display unit 600 is referred to as a “second shift register” and is denoted by reference numeral 310 b.
  • the first shift register 310a corresponds to a portion composed of an odd-stage bistable circuit in the shift register 310 in the first embodiment.
  • the second shift register 310b corresponds to a portion made up of an even number of bistable circuits in the shift register in the first embodiment.
  • the sampling circuit 320 in the present embodiment is configured separately on both sides of the display unit 600.
  • a portion of the sampling circuit 320 that is disposed on the upper side of the display unit 600 is referred to as a “first sampling circuit” and is denoted by reference numeral 320a.
  • a portion of the sampling circuit 320 disposed below the display unit 600 is referred to as a “second sampling circuit” and is denoted by reference numeral 320b.
  • the first sampling circuit 320a corresponds to a portion of the sampling circuit 320 in the first embodiment, which is composed of odd-numbered sampling blocks counted from the side where the gate driver 400 is disposed.
  • the second sampling circuit 320b corresponds to a part of the sampling circuit 320 in the first embodiment, which is composed of even-numbered sampling blocks counted from the side where the gate driver 400 is arranged.
  • the first source driver 300a includes a first shift register 310a and a first sampling circuit 320a.
  • the second source driver 300b includes a second shift register 310b and a second sampling circuit 320b.
  • the number of stages of the first source driver 300a and the second source driver 300b respectively disposed on the upper and lower sides of the display unit is approximately the number of stages of the source driver 300 in the first embodiment. Halved. For this reason, the layout pitch in the extending direction of the gate line is doubled. Thereby, for example, it becomes possible to deal with a higher-definition liquid crystal display panel.
  • the present invention is not limited to the configuration of the present embodiment, and for example, as shown in FIG. 17, the first sampling circuit 320a and the second sampling circuit 320b may share the sampling blocks 40 (1) to 40 (k). That is, in this case, the odd-numbered sampling blocks counted from the side on which the gate driver 400 is arranged are arranged on the lower side of the display unit 600 and the R thin film transistor and the B thin film transistor. And a thin film transistor for G. Further, the even-numbered sampling blocks counted from the side where the gate driver 400 is disposed include the G thin film transistor disposed on the upper side of the display unit 600, the R thin film transistor disposed on the lower side of the display unit 600, and B Thin film transistor.
  • the first source driver 300a includes the shift register 310 and the first sampling circuit 320a
  • the second source driver 300a includes the shift register 310 and the second sampling circuit 320b.
  • the number of stages of the shift register 310 arranged on each of the upper side and the lower side of the display unit is the same as the number of stages of the shift register 310 in the first embodiment, but the upper side and the lower side of the display unit.
  • the number of stages of each of the first sampling circuit 320a and the second sampling circuit 320b arranged on the side is about half of the number of stages of the sampling circuit 320 in the first embodiment. For this reason, as in the fourth embodiment, the layout pitch in the direction in which the gate lines extend can be doubled.
  • color image display using the three primary colors RGB is described, but the present invention is not limited to this.
  • color image display may be performed using four primary colors such as RGBY, or five or more primary colors.
  • Monochrome image display may be performed.
  • each set of source lines is composed of 24 source lines, but the present invention is not limited to this.
  • each source line group may be configured by source lines that are multiples of the number of primary colors.
  • the thin film transistors are all assumed to be n-channel type, but the present invention is not limited to this. The present invention can be applied even if the thin film transistor is a p-channel type.
  • the liquid crystal display device has been described as an example, but the present invention is not limited to this.
  • the present invention can also be applied to other display devices such as organic EL (Electro Luminescence) display devices.
  • organic EL Electro Luminescence
  • the above-described embodiments can be variously modified and implemented without departing from the spirit of the present invention.
  • a display device in which a display unit and a video signal line driving circuit are integrally formed with reduced power consumption and a method for controlling the video signal line driving circuit in the display device are provided.
  • the present invention can be applied to a display device in which a display unit and a video signal line driving circuit are integrally formed.

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Abstract

Provided is a display device that reduces power consumption, and has a display unit and an image signal drive circuit integrally formed with one another. A source driver (300) is configured from a shift register (310) and a sampling circuit (320). The sampling circuit (320) is configured from sampling blocks (40(1)-40(k)). Each sampling block is configured from three thin-film transistors. The shift register outputs selection signals (SEL(1)-SEL(k)) on the basis of a source clock signal (SCK2). The selection signals (SEL(1)-SEL(k)) are assigned to the sampling blocks (40(1)-40(k)). A scanning period (T1) is followed by an idle period (T2). During the idle period (T2), the shift register (310) operates on the basis of the source clock signal (SCK) of the idle period frequency (fck2). The idle period frequency (fck2) is lower than the scanning period frequency (fck1).

Description

表示装置およびその駆動方法Display device and driving method thereof
　本発明は、表示装置およびその駆動方法に関し、特に、表示部と映像信号線駆動回路とが一体的に形成された表示装置およびその駆動方法に関する。 The present invention relates to a display device and a driving method thereof, and more particularly, to a display device in which a display unit and a video signal line driving circuit are integrally formed and a driving method thereof.
　従来、液晶表示装置のソースライン（映像信号線）を駆動するためのソースドライバ（映像信号線駆動回路）は、液晶パネルを構成する基板の周辺部にＩＣ（Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ）チップとして搭載されることが多かった。しかし近年、基板上に直接的にソースドライバを形成する試みがなされてきている。このようなソースドライバは「モノリシックソースドライバ」等と呼ばれている。このモノリシックソースドライバを備えた液晶表示装置（以下「ソースドライバモノリシック型の液晶表示装置」という）は、例えば特許文献１に開示されている。このソースドライバモノリシック型の液晶表示装置によれば、狭額縁化および低コスト化を図ることができる。なお、このソースドライバモノリシック型の液晶表示装置では、従来よりアモルファスシリコン（ａ－Ｓｉ）を半導体層に用いた薄膜トランジスタ（以下「ａ－ＳｉＴＦＴ」という）等が駆動素子として採用されている。 Conventionally, a source driver (video signal line drive circuit) for driving a source line (video signal line) of a liquid crystal display device is mounted as an IC (Integrated Circuit) chip on the periphery of a substrate constituting the liquid crystal panel. There were many. In recent years, however, attempts have been made to form source drivers directly on a substrate. Such a source driver is called a “monolithic source driver” or the like. A liquid crystal display device provided with this monolithic source driver (hereinafter referred to as a “source driver monolithic liquid crystal display device”) is disclosed in, for example, Patent Document 1. According to the source driver monolithic type liquid crystal display device, it is possible to reduce the frame and reduce the cost. In the source driver monolithic liquid crystal display device, a thin film transistor (hereinafter referred to as “a-Si TFT”) using amorphous silicon (a-Si) as a semiconductor layer has been conventionally employed as a driving element.
　ところで、特許文献２には、ゲートラインを走査する走査期間Ｔ１の後に、全てのゲートラインを非走査状態にする休止期間Ｔ２を設ける表示装置の駆動方法が開示されている。この休止期間Ｔ２では、ゲートドライバにクロック信号等が与えられない。このため、走査期間Ｔ１においてゲートラインを６０Ｈｚで走査したとしても、例えばこの走査期間Ｔ１の同じ長さの休止期間Ｔ２を設けることにより、全体としてのゲートラインの駆動周波数が３０Ｈｚ程度になる。このため、低消費電力化を図ることができる。 Incidentally, Patent Document 2 discloses a driving method of a display device in which a rest period T2 in which all gate lines are in a non-scanning state is provided after a scanning period T1 in which gate lines are scanned. In this idle period T2, no clock signal or the like is given to the gate driver. For this reason, even if the gate line is scanned at 60 Hz in the scanning period T1, for example, by providing the rest period T2 having the same length as the scanning period T1, the driving frequency of the gate line as a whole becomes about 30 Hz. For this reason, power consumption can be reduced.
日本の特開２００４－７８１７２号公報Japanese Unexamined Patent Publication No. 2004-78172 日本の特開２００１－３１２２５３号公報Japanese Unexamined Patent Publication No. 2001-31253
　従来から、表示装置等の電子機器には低消費電力化が求められている。 Conventionally, low power consumption is required for electronic devices such as display devices.
　そこで、本発明は、消費電力を低減した、表示部と映像信号線駆動回路とが一体的に形成された表示装置およびその駆動方法を提供することを目的とする。 Therefore, an object of the present invention is to provide a display device in which a display unit and a video signal line driving circuit are integrally formed and a driving method thereof, with reduced power consumption.
　本発明の第１の局面は、表示装置であって、
　複数の映像信号線、該複数の映像信号線と交差する複数の走査信号線を含み、画像を表示するための表示部と、
　前記表示部と一体的に形成され、前記複数の映像信号線を駆動するための映像信号線駆動回路と、
　前記映像信号線駆動回路に、オンレベルとオフレベルとを周期的に繰り返すクロック信号、および前記表示部に表示すべき画像に対応する１以上の所定数の映像信号を与える表示制御回路と、
　前記複数の走査信号線が順次選択される走査期間と該複数の走査信号線のいずれもが非選択状態となる休止期間とが、該走査期間と該休止期間とからなるフレーム期間を周期として交互に現れるように、前記複数の走査信号線を駆動するための走査信号線駆動回路とを備え、
　前記映像信号線駆動回路は、
　　前記クロック信号に基づいて複数の出力信号を順次にオンレベルにするシフトレジスタと、
　　前記複数の出力信号がそれぞれ与えられる複数のサンプリングブロックとを含み、
　各サンプリングブロックが、該サンプリングブロックの受け取る前記出力信号に基づいて、前記所定数の映像信号を該所定数の映像信号線に与え、
　前記走査期間における前記クロック信号の周波数よりも、前記休止期間における該クロック信号の周波数が低いことを特徴とする。 A first aspect of the present invention is a display device,
A plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and a display unit for displaying an image;
A video signal line driving circuit formed integrally with the display unit for driving the plurality of video signal lines;
A display control circuit for providing the video signal line driving circuit with a clock signal that periodically repeats an on level and an off level, and one or more predetermined number of video signals corresponding to an image to be displayed on the display unit;
A scanning period in which the plurality of scanning signal lines are sequentially selected and a pause period in which all of the plurality of scanning signal lines are in a non-selected state alternate with a frame period that includes the scanning period and the pause period as a cycle. And a scanning signal line driving circuit for driving the plurality of scanning signal lines,
The video signal line driving circuit includes:
A shift register that sequentially turns on a plurality of output signals based on the clock signal;
A plurality of sampling blocks each provided with the plurality of output signals,
Each sampling block applies the predetermined number of video signals to the predetermined number of video signal lines based on the output signal received by the sampling block,
The frequency of the clock signal in the idle period is lower than the frequency of the clock signal in the scanning period.
　本発明の第２の局面は、本発明の第１の局面において、
　前記休止期間における前記クロック信号の振幅が、前記走査期間における該クロック信号の振幅よりも小さいことを特徴とする。 According to a second aspect of the present invention, in the first aspect of the present invention,
An amplitude of the clock signal in the pause period is smaller than an amplitude of the clock signal in the scanning period.
　本発明の第３の局面は、本発明の第１の局面において、
　前記休止期間が前記走査期間よりも長いことを特徴とする。 According to a third aspect of the present invention, in the first aspect of the present invention,
The pause period is longer than the scanning period.
　本発明の第４の局面は、本発明の第１の局面において、
　各サンプリングブロックは、該サンプリングブロックの受け取る前記出力信号が制御端子に与えられ、前記所定数の映像信号のうちのいずれかが第１導通端子に与えられ、前記複数の映像信号線のうちのいずれかに第２導通端子が接続された１以上のスイッチング素子を有することを特徴とする。 According to a fourth aspect of the present invention, in the first aspect of the present invention,
In each sampling block, the output signal received by the sampling block is supplied to a control terminal, one of the predetermined number of video signals is supplied to a first conduction terminal, and one of the plurality of video signal lines It has one or more switching elements to which the second conduction terminal is connected.
　本発明の第５の局面は、本発明の第４の局面において、
　各サンプリングブロックは前記スイッチング素子を複数有することを特徴とする。 According to a fifth aspect of the present invention, in the fourth aspect of the present invention,
Each sampling block has a plurality of the switching elements.
　本発明の第６の局面は、本発明の第５の局面において、
　前記表示部が複数の原色に基づくカラー画像を表示し、
　前記所定数の映像信号が前記複数の原色にそれぞれ対応し、
　各サンプリングブロックにおける前記複数のスイッチング素子の数が前記複数の原色と同数であり、
　前記表示制御回路が、各サンプリングブロックにおける前記複数のスイッチング素子の前記第１導通端子に互いに異なる前記所定数の映像信号をそれぞれ与えることを特徴とする。 A sixth aspect of the present invention is the fifth aspect of the present invention,
The display unit displays a color image based on a plurality of primary colors;
The predetermined number of video signals respectively corresponding to the plurality of primary colors;
The number of the plurality of switching elements in each sampling block is the same number as the plurality of primary colors,
The display control circuit supplies the predetermined number of video signals different from each other to the first conduction terminals of the plurality of switching elements in each sampling block.
　本発明の第７の局面は、本発明の第５の局面において、
　前記表示部が複数の原色に基づくカラー画像を表示し、
　各サンプリングブロックにおける前記複数のスイッチング素子の数が前記複数の原色の整数倍であり、
　前記表示制御回路が、各サンプリングブロックにおける前記複数のスイッチング素子のうちの、互いに隣接する映像信号線に前記第２導通端子が接続されたスイッチング素子の前記第１導通端子に、前記所定数の映像信号のうちの互いに異なる原色に対応する映像信号をそれぞれ与えることを特徴とする。 According to a seventh aspect of the present invention, in the fifth aspect of the present invention,
The display unit displays a color image based on a plurality of primary colors;
The number of the plurality of switching elements in each sampling block is an integer multiple of the plurality of primary colors;
The display control circuit has the predetermined number of images on the first conduction terminal of the switching element in which the second conduction terminal is connected to the video signal lines adjacent to each other among the plurality of switching elements in each sampling block. Video signals corresponding to different primary colors of the signals are respectively provided.
　本発明の第８の局面は、本発明の第１の局面において、
　前記映像信号線駆動回路は、
　　前記表示部に対して一方に位置する第１映像信号線駆動回路と、
　　前記表示部に対して他方に位置する第２映像信号線駆動回路とにより構成されることを特徴とする。 According to an eighth aspect of the present invention, in the first aspect of the present invention,
The video signal line driving circuit includes:
A first video signal line driving circuit located on one side with respect to the display unit;
And a second video signal line driving circuit positioned on the other side of the display unit.
　本発明の第９の局面は、本発明の第１の局面から第８の局面までのいずれかにおいて、
　前記映像信号線駆動回路が、酸化物半導体により半導体層が形成された薄膜トランジスタを用いて実現されていることを特徴とする。 According to a ninth aspect of the present invention, in any one of the first to eighth aspects of the present invention,
The video signal line driver circuit is realized using a thin film transistor in which a semiconductor layer is formed of an oxide semiconductor.
　本発明の第１０の局面は、本発明の第１の局面から第８の局面までのいずれかにおいて、
　前記映像信号線駆動回路が、アモルファスシリコンにより半導体層が形成された薄膜トランジスタを用いて実現されていることを特徴とする。 According to a tenth aspect of the present invention, in any one of the first to eighth aspects of the present invention,
The video signal line driving circuit is realized by using a thin film transistor in which a semiconductor layer is formed of amorphous silicon.
　本発明の第１１の局面は、複数の映像信号線、該複数の映像信号線と交差する複数の走査信号線を含み、画像を表示するための表示部と、オンレベルとオフレベルとを周期的に繰り返すクロック信号および該表示部に表示すべき画像に対応する１以上の所定数の映像信号を出力する表示制御回路と、該表示部と一体的に形成され、該クロック信号に基づいて複数の出力信号を順次にオンレベルにするシフトレジスタおよび該複数の出力信号がそれぞれ与えられる複数のサンプリングブロックとを含む映像信号線駆動回路と、前記複数の走査信号線を駆動するための走査信号線駆動回路とを備える表示装置の駆動方法であって、
　前記複数の走査信号線が順次選択される走査期間と該複数の走査信号線のいずれもが非選択状態となる休止期間とが、該走査期間と該休止期間とからなるフレーム期間を周期として交互に現れるように前記複数の走査信号線を駆動するステップと、
　各サンプリングブロックの受け取る前記出力信号に基づいて、前記所定数の映像信号を該所定数の映像信号線に与えるステップと、
　前記走査期間における前記クロック信号の周波数よりも、前記休止期間における該クロック信号の周波数を低くするステップとを備えることを特徴とする。 An eleventh aspect of the present invention includes a plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, a display unit for displaying an image, and an on level and an off level. And a display control circuit that outputs a predetermined number of video signals corresponding to an image to be displayed on the display unit, and a display control circuit that is formed integrally with the display unit, and that is based on the clock signal. Video signal line driving circuit including a shift register for sequentially turning on the output signals of the plurality of output signals, and a plurality of sampling blocks to which the plurality of output signals are respectively applied, and scanning signal lines for driving the plurality of scanning signal lines A driving method of a display device comprising a driving circuit,
A scanning period in which the plurality of scanning signal lines are sequentially selected and a pause period in which all of the plurality of scanning signal lines are in a non-selected state alternate with a frame period that includes the scanning period and the pause period as a cycle. Driving the plurality of scanning signal lines to appear in
Applying the predetermined number of video signals to the predetermined number of video signal lines based on the output signal received by each sampling block;
And a step of lowering the frequency of the clock signal in the idle period than the frequency of the clock signal in the scanning period.
　本発明の第１２の局面は、本発明の第１１の局面において、
　前記休止期間における前記クロック信号の振幅が、前記走査期間における該クロック信号の振幅よりも小さいことを特徴とする。 A twelfth aspect of the present invention is the eleventh aspect of the present invention,
An amplitude of the clock signal in the pause period is smaller than an amplitude of the clock signal in the scanning period.
　本発明の第１３の局面は、本発明の第１１の局面において、
　前記休止期間が前記走査期間よりも長いことを特徴とする。 A thirteenth aspect of the present invention is the eleventh aspect of the present invention,
The pause period is longer than the scanning period.
　本発明の第１の局面によれば、表示部と映像信号線駆動回路とが一体的に形成された表示装置において、１フレーム期間が上記走査期間および上記休止期間からなる。この休止期間におけるクロック信号の周波数は、走査期間におけるクロック信号の周波数よりも低くなる。このため、１フレーム期間全体での選択回路の駆動周波数が低減される。これにより、消費電力が低減される。また、表示部と映像信号線駆動回路とが一体的に形成されているので、額縁面積が縮小されると共に、映像信号線駆動回路のコストが低減される。 According to the first aspect of the present invention, in the display device in which the display unit and the video signal line driving circuit are integrally formed, one frame period includes the scanning period and the pause period. The frequency of the clock signal during this idle period is lower than the frequency of the clock signal during the scanning period. For this reason, the drive frequency of the selection circuit in the entire one frame period is reduced. Thereby, power consumption is reduced. In addition, since the display portion and the video signal line driving circuit are integrally formed, the frame area is reduced and the cost of the video signal line driving circuit is reduced.
　本発明の第２の局面によれば、休止期間におけるクロック信号の振幅が、走査期間におけるクロック信号の振幅よりも小さくなる。このため、さらなる低消費電力化を図ることができる。 According to the second aspect of the present invention, the amplitude of the clock signal in the pause period is smaller than the amplitude of the clock signal in the scanning period. For this reason, further reduction in power consumption can be achieved.
　本発明の第３の局面によれば、休止期間が走査期間によりも長くなる。このため、さらなる低消費電力化を図ることができる。 According to the third aspect of the present invention, the pause period becomes longer than the scanning period. For this reason, further reduction in power consumption can be achieved.
　本発明の第４の局面によれば、１以上のスイッチング素子によりサンプリングブロックを実現することができる。ここで、休止期間において、クロック信号に基づいてシフトレジスタの出力信号がハイレベルになるタイミングで、この出力信号が与えられるサンプリングブロック内のスイッチング素子に映像信号が与えられる。このため、休止期間において映像信号線が受けるノイズ等の影響が低減される。これにより、表示品位の低下を抑制することができる。また、休止期間におけるクロック信号の周波数が走査期間におけるものよりも低くなるので、スイッチング素子に掛かる負荷が低減される。したがって、スイッチング素子におけるしきい値変動が低減されるので、当該スイッチング素子の信頼性低下を抑制することができる。 According to the fourth aspect of the present invention, a sampling block can be realized by one or more switching elements. Here, in the idle period, a video signal is given to the switching element in the sampling block to which the output signal is given at the timing when the output signal of the shift register becomes high level based on the clock signal. For this reason, the influence of the noise etc. which a video signal line receives in an idle period is reduced. Thereby, the fall of display quality can be suppressed. Further, since the frequency of the clock signal in the idle period is lower than that in the scanning period, the load applied to the switching element is reduced. Therefore, the threshold fluctuation in the switching element is reduced, so that a decrease in reliability of the switching element can be suppressed.
　本発明の第５の局面によれば、映像信号を同時に複数のソースラインに与える順次駆動を行うことができる。 According to the fifth aspect of the present invention, sequential driving can be performed in which video signals are simultaneously applied to a plurality of source lines.
　本発明の第６の局面によれば、複数原色に基づく画像表示を行う表示装置において、上記第５の発明と同様の効果を奏することができる。 According to the sixth aspect of the present invention, in the display device that displays an image based on a plurality of primary colors, the same effect as in the fifth aspect can be achieved.
　本発明の第７の局面によれば、複数原色に基づく画像表示を行う表示装置において、複数の原色からなる画素の整数倍分の映像信号が一度に書き込まれる。走査期間を短くすることにより十分な休止期間を確保することができるか、または、映像信号の書き込み時間を十分に確保することができる。また、サンプリングブロックの数を削減することができるので、シフトレジスタの段数を削減することができる。 According to the seventh aspect of the present invention, in a display device that displays an image based on a plurality of primary colors, video signals for an integral multiple of pixels composed of a plurality of primary colors are written at a time. By shortening the scanning period, a sufficient pause period can be secured, or a video signal writing time can be secured sufficiently. In addition, since the number of sampling blocks can be reduced, the number of shift register stages can be reduced.
　本発明の第８の局面によれば、映像信号線駆動回路の段数が約半分になる。このため、走査信号線の延びる方向におけるレイアウトピッチが倍に広がる。これにより、例えば表示部の高精細化を図ることができる。 According to the eighth aspect of the present invention, the number of stages of the video signal line driving circuit is halved. This doubles the layout pitch in the direction in which the scanning signal lines extend. Thereby, for example, high definition of the display unit can be achieved.
　本発明の第９の局面によれば、酸化物半導体により半導体層が形成された薄膜トランジスタを用いて映像信号線駆動回路が実現される。この薄膜トランジスタのリーク電流は十分に小さいので、休止期間におけるクロック信号の周波数をさらに低くすることができる。このため、さらなる低消費電力化を図ることができる。また、酸化物半導体により半導体層が形成された薄膜トランジスタのオン電流は十分に大きいので、この薄膜トランジスタのサイズを十分に小さくすることができる。これにより、さらなる狭額縁化を図ることができる。 According to the ninth aspect of the present invention, a video signal line driving circuit is realized using a thin film transistor in which a semiconductor layer is formed of an oxide semiconductor. Since the leakage current of the thin film transistor is sufficiently small, the frequency of the clock signal during the idle period can be further reduced. For this reason, further reduction in power consumption can be achieved. In addition, since the on-state current of the thin film transistor in which the semiconductor layer is formed using an oxide semiconductor is sufficiently large, the size of the thin film transistor can be sufficiently reduced. Thereby, further narrowing of the frame can be achieved.
　本発明の第１０の局面によれば、アモルファスシリコンにより半導体層が形成された薄膜トランジスタを用いて映像信号線駆動回路が実現される。このため、さらなる低コスト化を図ることができる。 According to the tenth aspect of the present invention, a video signal line driving circuit is realized using a thin film transistor in which a semiconductor layer is formed of amorphous silicon. For this reason, further cost reduction can be achieved.
　本発明の第１１の局面から第１３の局面までによれば、表示装置の駆動方法において、本発明の第１の局面から第３の局面までとそれぞれ同様の効果を奏することができる。 According to the eleventh to thirteenth aspects of the present invention, in the method for driving the display device, it is possible to achieve the same effects as the first to third aspects of the present invention.
本発明の第１の実施形態に係る液晶表示装置の全体構成を示すブロック図である。1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a first embodiment of the present invention. 上記第１の実施形態におけるソースドライバの構成を説明するためのブロック図である。It is a block diagram for demonstrating the structure of the source driver in the said 1st Embodiment. 上記第１の実施形態におけるシフトレジスタの構成を示すブロック図である。It is a block diagram which shows the structure of the shift register in the said 1st Embodiment. 上記第１の実施形態におけるシフトレジスタの動作を説明するための信号波形図である。It is a signal waveform diagram for demonstrating operation | movement of the shift register in the said 1st Embodiment. 上記第１の実施形態における双安定回路の構成を示す回路図である。It is a circuit diagram which shows the structure of the bistable circuit in the said 1st Embodiment. 上記第１の実施形態における双安定回路の動作を説明するための信号波形図である。It is a signal waveform diagram for demonstrating operation | movement of the bistable circuit in the said 1st Embodiment. 上記第１の実施形態におけるサンプリング回路の構成を説明するための回路図である。It is a circuit diagram for demonstrating the structure of the sampling circuit in the said 1st Embodiment. 上記第１の実施形態における液晶表示装置の走査期間での動作を説明するための信号波形図である。It is a signal waveform diagram for demonstrating operation | movement in the scanning period of the liquid crystal display device in the said 1st Embodiment. 上記第１の実施形態における液晶表示装置の休止期間での動作を説明するための信号波形図である。It is a signal waveform diagram for demonstrating the operation | movement in the idle period of the liquid crystal display device in the said 1st Embodiment. 上記第１の実施形態における双安定回路の休止期間での動作を説明するための信号波形図である。It is a signal waveform diagram for demonstrating the operation | movement in the idle period of the bistable circuit in the said 1st Embodiment. ａ－ＳｉＴＦＴおよびＩＧＺＯＴＦＴのドレイン電流－ゲート電圧特性を示す図である。It is a figure which shows the drain current-gate voltage characteristic of a-SiTFT and IGZOTFT. 本発明の第２の実施形態における液晶表示装置の休止期間での動作を説明するための信号波形図である。It is a signal waveform diagram for demonstrating operation | movement in the idle period of the liquid crystal display device in the 2nd Embodiment of this invention. 本発明の第３の実施形態におけるサンプリング回路の構成を説明するための回路図である。It is a circuit diagram for demonstrating the structure of the sampling circuit in the 3rd Embodiment of this invention. 上記第３の実施形態における液晶表示装置の走査期間での動作を説明するための信号波形図である。It is a signal waveform diagram for demonstrating operation | movement in the scanning period of the liquid crystal display device in the said 3rd Embodiment. 上記第３の実施形態における液晶表示装置の休止期間での動作を説明するための信号波形図である。It is a signal waveform diagram for demonstrating operation | movement in the idle period of the liquid crystal display device in the said 3rd Embodiment. 本発明の第４の実施形態におけるソースドライバの構成を説明するための回路図である。It is a circuit diagram for demonstrating the structure of the source driver in the 4th Embodiment of this invention. 上記第４の実施形態におけるソースドライバの構成の他の例を説明するための回路図である。It is a circuit diagram for demonstrating the other example of a structure of the source driver in the said 4th Embodiment.
　以下、添付図面を参照しながら、本発明の実施形態について説明する。なお、以下の説明においては、薄膜トランジスタのゲート端子は制御端子に相当し、ドレイン端子は第１導通端子に相当し、ソース端子は第２導通端子に相当する。また、薄膜トランジスタはすべてｎチャネル型であるものとして説明する。 Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the gate terminal of the thin film transistor corresponds to the control terminal, the drain terminal corresponds to the first conduction terminal, and the source terminal corresponds to the second conduction terminal. The description will be made assuming that all thin film transistors are n-channel type.
　＜１．第１の実施形態＞
　＜１．１　全体構成および動作＞
　図１は、本発明の第１の実施形態に係るアクティブマトリクス型の液晶表示装置の全体構成を示すブロック図である。この液晶表示装置は、電源１００とＤＣ／ＤＣコンバータ１１０と表示制御回路２００とソースドライバ（映像信号線駆動回路）３００とゲートドライバ（走査信号線駆動回路）４００と共通電極駆動回路５００と表示部６００とを備えている。 <1. First Embodiment>
<1.1 Overall configuration and operation>
FIG. 1 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to a first embodiment of the present invention. The liquid crystal display device includes a power source 100, a DC / DC converter 110, a display control circuit 200, a source driver (video signal line driving circuit) 300, a gate driver (scanning signal line driving circuit) 400, a common electrode driving circuit 500, and a display unit. 600.
　ソースドライバ３００は、アモルファスシリコン、多結晶シリコン、微結晶シリコン、または酸化物半導体（例えばＩＧＺＯ）等を用いて、表示部６００を含む液晶表示パネル７００上に形成されている。すなわち、本実施形態に係る液晶表示装置は、ソースドライバ３００と表示部６００とが同一基板（液晶表示パネルを構成する２枚の基板のうちの一方の基板であるアレイ基板）上に形成されたソースドライバモノリシック型の液晶表示装置である。なお、ゲートドライバ４００もアモルファスシリコン、多結晶シリコン、微結晶シリコン、または酸化物半導体等を用いて液晶表示パネル７００上に形成されていても良い。これらのアモルファスシリコンおよびＩＧＺＯを用いた具体的な実現例については後述する。 The source driver 300 is formed on the liquid crystal display panel 700 including the display portion 600 using amorphous silicon, polycrystalline silicon, microcrystalline silicon, an oxide semiconductor (for example, IGZO), or the like. That is, in the liquid crystal display device according to this embodiment, the source driver 300 and the display unit 600 are formed on the same substrate (an array substrate that is one of the two substrates constituting the liquid crystal display panel). This is a source driver monolithic liquid crystal display device. Note that the gate driver 400 may also be formed over the liquid crystal display panel 700 using amorphous silicon, polycrystalline silicon, microcrystalline silicon, an oxide semiconductor, or the like. Specific implementation examples using these amorphous silicon and IGZO will be described later.
　表示部６００には、ｎ本のソースライン（映像信号線）ＳＬ１～ＳＬｎと、ｍ本のゲートライン（走査信号線）ＧＬ１～ＧＬｍと、これらのソースラインＳＬ１～ＳＬｎとゲートラインＧＬ１～ＧＬｍとの交差点にそれぞれ対応して設けられたｍ×ｎ個の画素形成部とが形成されている。上記ｍ×ｎ個の画素形成部は、マトリクス状に配置されることにより画素アレイを構成している。各画素形成部は、対応する交差点を通過するゲートラインにゲート端子が接続されると共に当該交差点を通過するソースラインにソース端子が接続されたスイッチング素子である画素薄膜トランジスタ８０と、その画素薄膜トランジスタ８０のドレイン端子に接続された画素電極と、上記複数個の画素形成部に共通的に設けられた対向電極である共通電極Ｅｃと、上記複数個の画素形成部に共通的に設けられ画素電極と共通電極Ｅｃとの間に挟持された液晶層とからなる。そして、画素電極と共通電極Ｅｃとにより形成される液晶容量により、画素容量Ｃｐが構成される。なお通常、画素容量Ｃｐに確実に電圧を保持すべく、液晶容量に並列に補助容量が設けられるが、補助容量は本発明には直接に関係しないのでその説明および図示を省略する。 The display unit 600 includes n source lines (video signal lines) SL1 to SLn, m gate lines (scanning signal lines) GL1 to GLm, source lines SL1 to SLn, and gate lines GL1 to GLm. M × n pixel forming portions provided corresponding to the respective intersections are formed. The m × n pixel forming portions are arranged in a matrix to constitute a pixel array. Each pixel forming portion includes a pixel thin film transistor 80 which is a switching element having a gate terminal connected to a gate line passing through a corresponding intersection and a source terminal connected to a source line passing through the intersection, and the pixel thin film transistor 80 A pixel electrode connected to the drain terminal, a common electrode Ec which is a counter electrode provided in common to the plurality of pixel formation portions, and a pixel electrode provided in common to the plurality of pixel formation portions. The liquid crystal layer is sandwiched between the electrode Ec. A pixel capacitor Cp is constituted by a liquid crystal capacitor formed by the pixel electrode and the common electrode Ec. Normally, an auxiliary capacitor is provided in parallel with the liquid crystal capacitor in order to reliably hold the voltage in the pixel capacitor Cp. However, since the auxiliary capacitor is not directly related to the present invention, its description and illustration are omitted.
　本実施形態に係る液晶表示装置では、ＲＧＢの３原色によるカラー画像表示が行われる。このため、上記画素形成部は、Ｒ、Ｇ、およびＢにそれぞれ対応する３個の画素形成部を１組として構成されている。この１組により１画素が形成される。以下では、Ｒ、Ｇ、およびＢにそれぞれ対応する画素形成部を「Ｒ画素形成部」、「Ｇ画素形成部」、および「Ｂ画素形成部」という。 In the liquid crystal display device according to the present embodiment, color image display using the three primary colors RGB is performed. For this reason, the pixel forming portion is configured as a set of three pixel forming portions corresponding to R, G, and B, respectively. One pixel is formed by this one set. Hereinafter, the pixel formation portions corresponding to R, G, and B are referred to as “R pixel formation portion”, “G pixel formation portion”, and “B pixel formation portion”, respectively.
　電源１００は、ＤＣ／ＤＣコンバータ１１０と表示制御回路２００と共通電極駆動回路５００とに所定の電源電圧を供給する。ＤＣ／ＤＣコンバータ１１０は、ソースドライバ３００およびゲートドライバ４００を動作させるための所定の直流電圧を電源電圧から生成し、それをソースドライバ３００およびゲートドライバ４００に供給する。共通電極駆動回路５００は、共通電極Ｅｃに所定の電位Ｖｃｏｍを与える。 The power supply 100 supplies a predetermined power supply voltage to the DC / DC converter 110, the display control circuit 200, and the common electrode drive circuit 500. The DC / DC converter 110 generates a predetermined DC voltage for operating the source driver 300 and the gate driver 400 from the power supply voltage and supplies it to the source driver 300 and the gate driver 400. The common electrode drive circuit 500 gives a predetermined potential Vcom to the common electrode Ec.
　表示制御回路２００は、外部から送られる画像信号ＤＡＴおよび水平同期信号や垂直同期信号などのタイミング信号群ＴＧを受け取り、映像信号Ｖｉｄと、表示部６００における画像表示を制御するためのソーススタートパルス信号ＳＳＰ、ソースクロック信号ＳＣＫ、ゲートスタートパルス信号ＧＳＰ、およびゲートクロック信号ＧＣＫを出力する。ソースクロック信号ＳＣＫのハイレベル側の電位はＶｄｄ電位、ローレベル側の電位はＶｓｓ電位となっている。 The display control circuit 200 receives an image signal DAT and a timing signal group TG such as a horizontal synchronization signal and a vertical synchronization signal sent from the outside, and receives a video signal Vid and a source start pulse signal for controlling image display on the display unit 600. The SSP, the source clock signal SCK, the gate start pulse signal GSP, and the gate clock signal GCK are output. The high level potential of the source clock signal SCK is Vdd potential, and the low level potential is Vss potential.
　本実施形態では、このソースクロック信号ＳＣＫは２相のソースクロック信号ＳＣＫ１およびＳＣＫ２からなっている。以下では、ソースクロック信号ＳＣＫ１を「第１ソースクロック信号」といい、ソースクロック信号ＳＣＫ２を「第２ソースクロック信号」という。また、第１ソースクロック信号ＳＣＫ１および第２ソースクロック信号ＳＣＫ２のそれぞれがローレベル電位からハイレベル電位に変化する時点から、ハイレベル電位からローレベル電位に変化する時点までの期間を便宜上「サンプリング期間」という。これらの第１ソースクロック信号ＳＣＫ１および第２ソースクロック信号ＳＣＫ２は、互いに１サンプリング期間だけ位相がずれており、いずれも２サンプリング期間中の１サンプリング期間だけハイレベル電位（Ｖｄｄ電位）になる（ただし、後述の休止期間Ｔ２を除く）。 In this embodiment, the source clock signal SCK is composed of two-phase source clock signals SCK1 and SCK2. Hereinafter, the source clock signal SCK1 is referred to as a “first source clock signal”, and the source clock signal SCK2 is referred to as a “second source clock signal”. For convenience, the period from the time when each of the first source clock signal SCK1 and the second source clock signal SCK2 changes from the low level potential to the high level potential until the time when the high level potential changes to the low level potential is referred to as the “sampling period”. " The first source clock signal SCK1 and the second source clock signal SCK2 are out of phase with each other by one sampling period, and both are at a high level potential (Vdd potential) only for one sampling period among the two sampling periods (however, , Except for a rest period T2 described later).
　ソースドライバ３００は、表示制御回路２００から出力される映像信号Ｖｉｄ、ソーススタートパルス信号ＳＳＰ、およびソースクロック信号ＳＣＫを受け取る。このソースドライバ３００は、受け取った映像信号Ｖｉｄを所定のタイミングでソースラインＳＬ１～ＳＬｎに与える。この映像信号Ｖｉｄは、３つの映像信号Ｖｉｄｒ、Ｖｉｄｇ、およびＶｉｄｂからなっている。以下では、映像信号Ｖｉｄｒを「Ｒ用映像信号」といい、映像信号Ｖｉｄｇを「Ｇ用映像信号」といい、映像信号Ｖｉｄｂを「Ｂ用映像信号」という。Ｒ用映像信号Ｖｉｄｒ、Ｇ用映像信号Ｖｉｄｇ、およびＢ用映像信号ＶｉｄｂはそれぞれＲ画素形成部、Ｇ画素形成部、およびＢ画素形成部に対応している。本実施形態におけるソースドライバ３００は、いわゆる点順次駆動を行う。なお、このソースドライバについての詳しい説明は後述する。 The source driver 300 receives the video signal Vid, the source start pulse signal SSP, and the source clock signal SCK output from the display control circuit 200. The source driver 300 supplies the received video signal Vid to the source lines SL1 to SLn at a predetermined timing. This video signal Vid includes three video signals Vidr, Vidg, and Vidb. Hereinafter, the video signal Vidr is referred to as “R video signal”, the video signal Vidg is referred to as “G video signal”, and the video signal Vidb is referred to as “B video signal”. The R video signal Vidr, the G video signal Vidg, and the B video signal Vidb correspond to the R pixel forming unit, the G pixel forming unit, and the B pixel forming unit, respectively. The source driver 300 in this embodiment performs so-called dot sequential driving. A detailed description of this source driver will be described later.
　ゲートドライバ４００は、表示制御回路２００から出力されるゲートスタートパルス信号ＧＳＰおよびゲートクロック信号ＧＣＫに基づいて、ハイレベル電位の走査信号ＧＳ（１）～ＧＳ（ｍ）のゲートラインＧＬ１～ＧＬｍそれぞれへの印加を１フレーム期間を周期として繰り返す。以下では、各ゲートラインにハイレベル電位が与えられることにより、当該ゲートラインが選択状態となっている期間（１水平走査期間）を「走査選択期間」という。さらに、ゲートラインＧＬｉが選択状態となっている期間（１水平走査期間）を「第ｉ走査選択期間」という（ｉ＝１～ｍ）。本実施形態では、１フレーム期間が走査期間Ｔ１と、当該走査期間Ｔ１の後に設けられた休止期間Ｔ２とからなっている。ゲートドライバ４００は、この走査期間Ｔ１では走査信号ＧＳ（１）～ＧＳ（ｍ）をゲートクロック信号ＧＣＫに基づいて順次にハイレベル電位にする。一方休止期間Ｔ２では、ゲートドライバ４００は、ｍ本のゲートラインＧＬ１～ＧＬｍ（走査信号ＧＳ（１）～ＧＳ（ｍ））をローレベル電位にする。 Based on the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 200, the gate driver 400 supplies the high-level potential scanning signals GS (1) to GS (m) to the gate lines GL1 to GLm, respectively. Is repeated with one frame period as a cycle. Hereinafter, a period (one horizontal scanning period) in which a high level potential is applied to each gate line and the gate line is in a selected state is referred to as a “scanning selection period”. Further, a period during which the gate line GLi is in a selected state (one horizontal scanning period) is referred to as an “i-th scanning selection period” (i = 1 to m). In the present embodiment, one frame period includes a scanning period T1 and a pause period T2 provided after the scanning period T1. In the scanning period T1, the gate driver 400 sequentially sets the scanning signals GS (1) to GS (m) to the high level potential based on the gate clock signal GCK. On the other hand, in the suspension period T2, the gate driver 400 sets the m gate lines GL1 to GLm (scanning signals GS (1) to GS (m)) to a low level potential.
　以上のようにして、ソースラインＳＬ１～ＳＬｎに映像信号が印加され、ゲートラインＧＬ１～ＧＬｍに走査信号ＧＳ（１）～ＧＳ（ｍ）がそれぞれ印加されることにより、外部から送られた画像信号ＤＡＴに基づく画像が表示部６００に表示される。 As described above, the video signals are applied to the source lines SL1 to SLn, and the scanning signals GS (1) to GS (m) are applied to the gate lines GL1 to GLm, respectively. An image based on DAT is displayed on the display unit 600.
　＜１．２　ソースドライバの構成および動作＞
　図２は、本実施形態におけるソースドライバ３００の構成を示すブロック図である。図２に示すように、このソースドライバ３００は、シフトレジスタ３１０およびサンプリング回路３２０により構成されている。 <1.2 Source Driver Configuration and Operation>
FIG. 2 is a block diagram showing the configuration of the source driver 300 in this embodiment. As shown in FIG. 2, the source driver 300 includes a shift register 310 and a sampling circuit 320.
　シフトレジスタ３１０は、表示制御回路２００から出力されたソーススタートパルス信号ＳＳＰおよびソースクロック信号ＳＣＫを受け取る。このシフトレジスタ３１０は、これらのソーススタートパルス信号ＳＳＰおよびソースクロック信号ＳＣＫに基づいて、ソーススタートパルス信号ＳＳＰに含まれるパルスを入力端から出力端へと順次転送する。この転送に応じて、このシフトレジスタ３１０の出力信号である選択信号ＳＥＬ（１）～ＳＥＬ（ｋ）が順次にハイレベル電位になる。これらの選択信号ＳＥＬ（１）～ＳＥＬ（ｋ）は、サンプリング回路３２０に与えられる。 The shift register 310 receives the source start pulse signal SSP and the source clock signal SCK output from the display control circuit 200. The shift register 310 sequentially transfers pulses included in the source start pulse signal SSP from the input end to the output end based on the source start pulse signal SSP and the source clock signal SCK. In response to this transfer, the selection signals SEL (1) to SEL (k), which are output signals of the shift register 310, sequentially become a high level potential. These selection signals SEL (1) to SEL (k) are applied to the sampling circuit 320.
　サンプリング回路３２０は、シフトレジスタ３１０から出力された選択信号ＳＥＬ（１）～（ｋ）と、表示制御回路２００から出力された映像信号Ｖｉｄとを受け取る。サンプリング回路３２０は、これらの選択信号ＳＥＬ（１）～（ｋ）がハイレベル電位になるタイミングで、映像信号ＶｉｄをソースラインＳＬ１～ＳＬｎに与える。 The sampling circuit 320 receives the selection signals SEL (1) to (k) output from the shift register 310 and the video signal Vid output from the display control circuit 200. The sampling circuit 320 supplies the video signal Vid to the source lines SL1 to SLn at the timing when these selection signals SEL (1) to (k) become the high level potential.
　＜１．３　シフトレジスタの構成および動作＞
　図３は、本実施形態におけるシフトレジスタ３１０の構成を示すブロック図である。このシフトレジスタ３１０は、ｋ個の双安定回路３０（１）～３０（ｋ）と、１個のダミー用双安定回路３０（ｋ＋１）により構成されている。なお、以下の説明では、ｘ段目（ｘ＝１～ｋ＋１）の双安定回路のことを、単に「ｘ段目」ということがある。また、ｋ＋１段目を「ダミー段」ということがある。各双安定回路は、各時点において２つの状態（第１の状態および第２の状態）のうちのいずれか一方の状態となっていて当該状態を示す信号（以下「状態信号」という。）を出力する。本実施形態では、双安定回路が第１の状態となっていれば、当該双安定回路からはハイレベル（オンレベル）電位の状態信号が出力され、双安定回路が第２の状態となっていれば、当該双安定回路からはローレベル（オフレベル）電位の状態信号が出力される。この状態信号は、上述の選択信号に相当する。すなわち、双安定回路３０（１）～３０（ｋ）の状態信号はそれぞれ、選択信号ＳＥＬ（１）～ＳＥＬ（ｋ）に相当する。 <1.3 Configuration and operation of shift register>
FIG. 3 is a block diagram showing a configuration of the shift register 310 in the present embodiment. The shift register 310 includes k bistable circuits 30 (1) to 30 (k) and one dummy bistable circuit 30 (k + 1). In the following description, the x-stage (x = 1 to k + 1) bistable circuit may be simply referred to as “x-th stage”. The k + 1th stage may be referred to as a “dummy stage”. Each bistable circuit is in one of two states (first state and second state) at each time point, and a signal indicating the state (hereinafter referred to as a “state signal”). Output. In the present embodiment, if the bistable circuit is in the first state, a high-level (on-level) potential state signal is output from the bistable circuit, and the bistable circuit is in the second state. Then, a state signal having a low level (off level) potential is output from the bistable circuit. This state signal corresponds to the selection signal described above. That is, the state signals of the bistable circuits 30 (1) to 30 (k) correspond to the selection signals SEL (1) to SEL (k), respectively.
　各双安定回路には、クロック信号ＣＫ１（以下「第１クロック信号」という）を受け取るための入力端子、クロック信号ＣＫ２（以下「第２クロック信号」という）を受け取るための入力端子、ローレベルの直流電源電位Ｖｓｓ（この電位の大きさのことを上記「Ｖｓｓ電位」ともいう）を受け取るための入力端子（図示しない）、セット信号Ｓを受け取るための入力端子、リセット信号Ｒを受け取るための入力端子、および状態信号Ｚを出力するための出力端子が設けられている。 Each bistable circuit has an input terminal for receiving a clock signal CK1 (hereinafter referred to as “first clock signal”), an input terminal for receiving a clock signal CK2 (hereinafter referred to as “second clock signal”), An input terminal (not shown) for receiving a DC power supply potential Vss (the magnitude of this potential is also referred to as the “Vss potential”), an input terminal for receiving a set signal S, and an input for receiving a reset signal R A terminal and an output terminal for outputting a status signal Z are provided.
　このシフトレジスタ３１０には、ソースクロック信号ＳＣＫとして、上述のように２相の第１ソースクロック信号ＳＣＫ１および第２ソースクロック信号ＳＣＫ２が与えられる。なお、本発明はこれに限定されるものではなく、３相以上のソースクロック信号を用いた態様としても良い。 The shift register 310 is supplied with the two-phase first source clock signal SCK1 and second source clock signal SCK2 as the source clock signal SCK as described above. In addition, this invention is not limited to this, It is good also as an aspect using the source clock signal of 3 phases or more.
　シフトレジスタ３１０の各段（各双安定回路）の入力端子に与えられる信号は次のようになっている。すなわち、第１ソースクロック信号ＳＣＫ１が第１クロック信号ＣＫ１として与えられ、第２ソースクロック信号ＳＣＫ２が第２クロック信号ＣＫ２として与えられる。偶数段目には、第１ソースクロック信号ＳＣＫ１が第２クロック信号ＣＫ２として与えられ、第２ソースクロック信号ＳＣＫ２が第１クロック信号ＣＫ１として与えられる。また、各段には図示しない手段によりローレベルの直流電源電位Ｖｓｓが共通的に与えられる。 The signals given to the input terminals of each stage (each bistable circuit) of the shift register 310 are as follows. That is, the first source clock signal SCK1 is provided as the first clock signal CK1, and the second source clock signal SCK2 is provided as the second clock signal CK2. In the even-numbered stage, the first source clock signal SCK1 is supplied as the second clock signal CK2, and the second source clock signal SCK2 is supplied as the first clock signal CK1. Further, a low level DC power supply potential Vss is commonly applied to each stage by means not shown.
　各段には、前段から出力される状態信号Ｚがセット信号Ｓとして与えられ、次段から出力される状態信号Ｚがリセット信号Ｒとして与えられる。ただし、１段目（最前段）３０（１）には、ソーススタートパルス信号ＳＳＰがセット信号Ｓとして与えられる。このソーススタートパルス信号ＳＳＰは、各走査選択期間のうちの、最初の１サンプリング期間においてハイレベル電位になる信号である。また、ｋ段目（最後段）３０（ｋ）には、ダミー段３０（ｋ＋１）から出力される状態信号がリセット信号Ｒとして与えられる。なお、ダミー段３０（ｋ＋１）には、ｋ段目３０（ｋ）から出力される状態信号Ｚがセット信号Ｓとして与えられ、自身の状態信号Ｚがリセット信号Ｒとして与えられる。このため、ダミー段３０（ｋ＋１）の状態信号Ｚがハイレベル電位になっている期間は、他の段の状態信号Ｚがハイレベル電位になっている期間よりも短い。このようなダミー段３０（ｋ＋１）を設けることに代えて、ｋ段目３０（ｋ）にリセット信号Ｒとして、ソースエンドパルス信号ＳＥＰを与えても良い。このソースエンドパルス信号ＳＥＰは、ｋ段目の走査選択期間終了後の１サンプリング期間においてハイレベル電位になる信号である。 In each stage, the status signal Z output from the previous stage is given as the set signal S, and the status signal Z outputted from the next stage is given as the reset signal R. However, the source start pulse signal SSP is given as the set signal S to the first stage (frontmost stage) 30 (1). The source start pulse signal SSP is a signal that becomes a high level potential in the first sampling period in each scanning selection period. Further, a state signal output from the dummy stage 30 (k + 1) is given as a reset signal R to the k-th stage (last stage) 30 (k). The dummy stage 30 (k + 1) is given the state signal Z output from the k-th stage 30 (k) as the set signal S, and its own state signal Z is given as the reset signal R. For this reason, the period in which the state signal Z of the dummy stage 30 (k + 1) is at the high level potential is shorter than the period in which the state signal Z of the other stage is at the high level potential. Instead of providing such a dummy stage 30 (k + 1), the source end pulse signal SEP may be given as the reset signal R to the k-th stage 30 (k). The source end pulse signal SEP is a signal that becomes a high level potential in one sampling period after the end of the k-th scanning selection period.
　以上のような構成において、シフトレジスタ３１０の１段目３０（１）にセット信号Ｓとしてのソーススタートパルス信号ＳＳＰが与えられると、第１ソースクロック信号ＳＣＫ１および第２ソースクロック信号ＳＣＫ２に基づいて、ソーススタートパルス信号ＳＳＰに含まれるパルス（このパルスは各段から出力される状態信号Ｚに含まれる）が１段目３０（１）からｋ段目３０（ｋ）へと順次に転送される。そして、このパルスの転送に応じて、１段目３０（１）～ｋ段目３０（ｋ）からそれぞれ出力される状態信号Ｚが順次にハイレベル電位となる。これらの１段目３０（１）～３０（ｋ）からそれぞれ出力される状態信号Ｚは、選択信号ＳＥＬ（１）～ＳＥＬ（ｋ）としてサンプリング回路３２０に与えられる。以上により、図４に示すように、１サンプリング期間ずつ順次にハイレベル電位となる選択信号がサンプリング回路３２０に与えられる。以下では、各選択信号がハイレベル電位になる期間を「サンプリング選択期間」という。さらに、選択信号ＳＥＬ（ｊ）がハイレベルになる期間を「第ｊサンプリング選択期間」という。 In the above configuration, when the source start pulse signal SSP as the set signal S is supplied to the first stage 30 (1) of the shift register 310, based on the first source clock signal SCK1 and the second source clock signal SCK2. The pulses included in the source start pulse signal SSP (this pulse is included in the status signal Z output from each stage) are sequentially transferred from the first stage 30 (1) to the kth stage 30 (k). . In response to the transfer of the pulse, the state signals Z output from the first stage 30 (1) to the kth stage 30 (k) are sequentially set to the high level potential. The state signals Z output from the first stages 30 (1) to 30 (k) are supplied to the sampling circuit 320 as selection signals SEL (1) to SEL (k). As described above, as shown in FIG. 4, a selection signal that sequentially becomes a high level potential is supplied to the sampling circuit 320 for each sampling period. Hereinafter, a period during which each selection signal is at a high level potential is referred to as a “sampling selection period”. Furthermore, a period during which the selection signal SEL (j) is at a high level is referred to as a “jth sampling selection period”.
　＜１．４　双安定回路の構成および動作＞
　図５は、本実施形態における各双安定回路の構成を示す回路図である。図５に示すように、この双安定回路は、４個の薄膜トランジスタ（スイッチング素子）Ｍ１～Ｍ４、コンデンサＣ１、４個の入力端子３１～３４、ローレベルの直流電源電位Ｖｓｓ用の入力端子、および出力端子３９により構成されている。ここで、第１クロック信号ＣＫ１を受け取る入力端子には符号３１を付し、第２クロック信号ＣＫ２を受け取る入力端子には符号３２を付し、セット信号Ｓを受け取る入力端子には符号３３を付し、リセット信号Ｒを受け取る入力端子には符号３４を付している。また、状態信号Ｚを出力する出力端子には符号３９を付している。なお、シフトレジスタ３１０の双安定回路としては、本実施形態における双安定回路の構成に限定されるものではなく、種々の構成の双安定回路を採用することができる。 <1.4 Bistable circuit configuration and operation>
FIG. 5 is a circuit diagram showing a configuration of each bistable circuit in the present embodiment. As shown in FIG. 5, the bistable circuit includes four thin film transistors (switching elements) M1 to M4, a capacitor C1, four input terminals 31 to 34, an input terminal for a low-level DC power supply potential Vss, and An output terminal 39 is used. Here, the input terminal that receives the first clock signal CK1 is denoted by reference numeral 31, the input terminal that receives the second clock signal CK2 is denoted by reference numeral 32, and the input terminal that receives the set signal S is denoted by reference numeral 33. The input terminal that receives the reset signal R is denoted by reference numeral 34. Further, reference numeral 39 is attached to an output terminal for outputting the status signal Z. Note that the bistable circuit of the shift register 310 is not limited to the configuration of the bistable circuit in the present embodiment, and bistable circuits having various configurations can be employed.
　次に、この双安定回路内における構成要素間の接続関係について説明する。薄膜トランジスタＭ１のゲート端子、薄膜トランジスタＭ３のソース端子、薄膜トランジスタＭ４のドレイン端子、およびコンデンサＣ１の一端は互いに接続されている。以下では、これらが互いに接続されている接続点（配線）のことを便宜上「第１ノード」という。この第１ノードには符号Ｎ１を付す。 Next, the connection relationship between the components in the bistable circuit will be described. The gate terminal of the thin film transistor M1, the source terminal of the thin film transistor M3, the drain terminal of the thin film transistor M4, and one end of the capacitor C1 are connected to each other. Hereinafter, a connection point (wiring) where these are connected to each other is referred to as a “first node” for convenience. The first node is denoted by reference numeral N1.
　薄膜トランジスタＭ１については、ゲート端子が第１ノードＮ１に接続され、ドレイン端子が入力端子３１に接続され、ソース端子が出力端子３９に接続されている。薄膜トランジスタＭ２については、ゲート端子が入力端子３２に接続され、ドレイン端子が出力端子３９に接続され、ソース端子が直流電源電位Ｖｓｓ用の入力端子に接続されている。薄膜トランジスタＭ３については、ゲート端子およびドレイン端子が入力端子３３に接続され（すなわち、ダイオード接続となっている）、ソース端子が第１ノードＮ１に接続されている。薄膜トランジスタＭ４については、ゲート端子が入力端子３４に接続され、ドレイン端子が第１ノードＮ１に接続され、ソース端子が直流電源電位Ｖｓｓ用の入力端子に接続されている。コンデンサＣ１については、一端が第１ノードＮ１に接続され、他端が出力端子３９に接続されている。 Regarding the thin film transistor M1, the gate terminal is connected to the first node N1, the drain terminal is connected to the input terminal 31, and the source terminal is connected to the output terminal 39. As for the thin film transistor M2, the gate terminal is connected to the input terminal 32, the drain terminal is connected to the output terminal 39, and the source terminal is connected to the input terminal for the DC power supply potential Vss. As for the thin film transistor M3, the gate terminal and the drain terminal are connected to the input terminal 33 (that is, diode connection), and the source terminal is connected to the first node N1. The thin film transistor M4 has a gate terminal connected to the input terminal 34, a drain terminal connected to the first node N1, and a source terminal connected to the input terminal for the DC power supply potential Vss. The capacitor C1 has one end connected to the first node N1 and the other end connected to the output terminal 39.
　次に、この双安定回路における各構成要素の機能について説明する。薄膜トランジスタＭ１は、第１ノードＮ１の電位がハイレベルになっているときに、第１クロック信号ＣＫの電位を出力端子３９に与える。薄膜トランジスタＭ２は、第２クロック信号ＣＫ２の電位がハイレベルになっているときに、出力端子３９の電位をＶｓｓ電位に向けて変化させる。薄膜トランジスタＭ３は、セット信号Ｓの電位がハイレベルになっているときに、第１ノードＮ１の電位をハイレベルに向けて変化させる。薄膜トランジスタＭ４は、リセット信号Ｒの電位がハイレベルになっているときに、第１ノードＮ１の電位をＶｓｓ電位に向けて変化させる。コンデンサＣ１は、第１ノードＮ１がブートストラップされるときの補助容量として機能する。 Next, the function of each component in this bistable circuit will be described. The thin film transistor M1 applies the potential of the first clock signal CK to the output terminal 39 when the potential of the first node N1 is at a high level. The thin film transistor M2 changes the potential of the output terminal 39 toward the Vss potential when the potential of the second clock signal CK2 is at a high level. The thin film transistor M3 changes the potential of the first node N1 toward the high level when the potential of the set signal S is at the high level. The thin film transistor M4 changes the potential of the first node N1 toward the Vss potential when the potential of the reset signal R is at a high level. The capacitor C1 functions as an auxiliary capacitor when the first node N1 is bootstrapped.
　図６は、本実施形態における双安定回路の動作のうち、特に走査期間Ｔ１での動作を説明するための信号波形図である。なお、他の双安定回路の動作も同様であるので、説明を省略する。ここで、この双安定回路は奇数段目であるものとして説明する。奇数段目では、第１ソースクロック信号ＳＣＫ１および第２ソースクロック信号ＳＣＫ２がそれぞれ第１クロック信号ＣＫ１および第２クロック信号ＣＫ２に相当する。図６における時点ｔ１から時点ｔ２までの期間はサンプリング選択期間に相当する。走査期間Ｔ１での動作説明においては、サンプリング選択期間直前の１サンプリング期間のことを「セット期間」といい、サンプリング選択期間直後の１サンプリング期間のことを「リセット期間」という。また、走査期間のうちの、選択期間、セット期間、およびリセット期間以外の期間のことを「通常動作期間」という。 FIG. 6 is a signal waveform diagram for explaining the operation in the scanning period T1 among the operations of the bistable circuit in the present embodiment. Since the operation of other bistable circuits is the same, the description thereof is omitted. Here, this bistable circuit will be described as an odd-numbered stage. In the odd-numbered stages, the first source clock signal SCK1 and the second source clock signal SCK2 correspond to the first clock signal CK1 and the second clock signal CK2, respectively. A period from time t1 to time t2 in FIG. 6 corresponds to a sampling selection period. In the description of the operation in the scanning period T1, one sampling period immediately before the sampling selection period is referred to as a “set period”, and one sampling period immediately after the sampling selection period is referred to as a “reset period”. Further, a period other than the selection period, the set period, and the reset period in the scanning period is referred to as a “normal operation period”.
　セット期間になると（時点ｔ０になると）、セット信号Ｓの電位がローレベルからハイレベルに変化する。薄膜トランジスタＭ３が図５に示すようにダイオード接続となっているので、セット信号Ｓの電位がハイレベルになることによって薄膜トランジスタＭ３がオン状態になり、コンデンサＣ１が充電（ここではプリチャージ）される。これにより、第１ノードＮ１の電位がローレベルからハイレベルに変化し、薄膜トランジスタＭ１がオン状態となる。しかし、セット期間では、第１ソースクロック信号ＳＣＫ１（第１クロック信号ＣＫ１）の電位がローレベルとなっているので、状態信号Ｚの電位はローレベルで維持される。 In the set period (at time t0), the potential of the set signal S changes from low level to high level. Since the thin film transistor M3 is diode-connected as shown in FIG. 5, when the potential of the set signal S goes high, the thin film transistor M3 is turned on and the capacitor C1 is charged (here, precharged). As a result, the potential of the first node N1 changes from the low level to the high level, and the thin film transistor M1 is turned on. However, in the set period, since the potential of the first source clock signal SCK1 (first clock signal CK1) is at a low level, the potential of the state signal Z is maintained at a low level.
　サンプリング選択期間になると（時点ｔ１になると）、セット信号Ｓがハイレベルからローレベルに変化する。これにより、薄膜トランジスタＭ３がオフ状態になる。このとき、第１ノードＮ１はフローティング状態になる。この時点ｔ１では、第１ソースクロック信号ＳＣＫ１の電位がローレベルからハイレベルに変化する。薄膜トランジスタＭ１はオン状態でありゲート容量が存在するので、入力端子３１の電位の上昇に伴って第１ノードＮ１の電位も上昇する（第１ノードＮ１がブートストラップされる）。この際、コンデンサＣ１は第１ノードＮ１の電位上昇を促進するように働く。その結果、薄膜トランジスタＭ１のゲート電位は十分に高いレベルになるので、第１ソースクロック信号ＳＣＫ１のハイレベル（Ｖｄｄ電位）まで状態信号Ｚの電位が上昇する。 In the sampling selection period (at time t1), the set signal S changes from high level to low level. Thereby, the thin film transistor M3 is turned off. At this time, the first node N1 is in a floating state. At this time t1, the potential of the first source clock signal SCK1 changes from the low level to the high level. Since the thin film transistor M1 is in an on state and has a gate capacitance, the potential of the first node N1 increases as the potential of the input terminal 31 increases (the first node N1 is bootstrapped). At this time, the capacitor C1 works to promote the potential rise of the first node N1. As a result, the gate potential of the thin film transistor M1 becomes sufficiently high, so that the potential of the state signal Z rises to the high level (Vdd potential) of the first source clock signal SCK1.
　リセット期間になると（時点ｔ２になると）、第１ソースクロック信号ＳＣＫ１の電位がハイレベルからローレベルに変化する。時点ｔ２には薄膜トランジスタＭ１がオン状態となっているので、入力端子３１の電位の低下と共に状態信号Ｚの電位が低下する。このように状態信号Ｚの電位が低下することによって、コンデンサＣ１を介して第１ノードＮ１の電位も低下する。また、リセット期間には、リセット信号Ｒがローレベルからハイレベルに変化する。このため、薄膜トランジスタＭ４がオン状態になる。その結果、リセット期間には、第１ノードＮ１の電位が確実にローレベルに低下する。さらに、リセット期間には、第２ソースクロック信号ＳＣＫ２（第２クロック信号ＣＫ２）がローレベルからハイレベルに変化する。このため、薄膜トランジスタＭ２がオン状態になるので、状態信号Ｚの電位が確実にローレベルに低下する。 In the reset period (at time t2), the potential of the first source clock signal SCK1 changes from high level to low level. Since the thin film transistor M1 is in the on state at time t2, the potential of the state signal Z decreases as the potential of the input terminal 31 decreases. As the potential of the state signal Z decreases in this way, the potential of the first node N1 also decreases via the capacitor C1. In the reset period, the reset signal R changes from a low level to a high level. For this reason, the thin film transistor M4 is turned on. As a result, during the reset period, the potential of the first node N1 is reliably lowered to a low level. Further, in the reset period, the second source clock signal SCK2 (second clock signal CK2) changes from the low level to the high level. For this reason, since the thin film transistor M2 is turned on, the potential of the state signal Z is reliably lowered to a low level.
　通常動作期間では、第２ソースクロック信号ＳＣＫ２の電位が１水平走査期間毎にハイレベルとローレベルとを繰り返すことにより、薄膜トランジスタＭ２が１水平走査期間毎にオン状態になる。このため、状態信号Ｚの電位をローレベルに維持することができる。 In the normal operation period, the potential of the second source clock signal SCK2 repeats a high level and a low level every horizontal scanning period, so that the thin film transistor M2 is turned on every horizontal scanning period. For this reason, the potential of the state signal Z can be maintained at a low level.
　なお、以下の説明では、走査期間Ｔ１における第１ソースクロック信号ＳＣＫ１および第２ソースクロック信号ＳＣＫ２のそれぞれの周期（以下「走査期間周期」という）を符号ｔｃｋ１で表す。また、走査期間Ｔ１における第１ゲートクロック信号ＧＣＫ１および第２ゲートクロック信号ＧＣＫ２のそれぞれの周波数（以下「走査期間周波数」という）を符号ｆｃｋ１で表す。さらに、走査期間Ｔ１における第１ソースクロック信号ＳＣＫ１および第２ソースクロック信号ＳＣＫ２のそれぞれの振幅（以下「走査期間振幅」という）を符号Ｖｃｋ１で表す。 In the following description, each cycle of the first source clock signal SCK1 and the second source clock signal SCK2 in the scanning period T1 (hereinafter referred to as “scanning period cycle”) is represented by a reference tck1. Further, the respective frequencies of the first gate clock signal GCK1 and the second gate clock signal GCK2 in the scanning period T1 (hereinafter referred to as “scanning period frequency”) are denoted by reference numeral fck1. Further, the respective amplitudes of the first source clock signal SCK1 and the second source clock signal SCK2 in the scanning period T1 (hereinafter referred to as “scanning period amplitude”) are represented by reference sign Vck1.
　＜１．５　サンプリング回路の構成＞
　図７は、本実施形態におけるサンプリング回路３２０の構成を説明するための回路図である。図７に示すように、このサンプリング回路３２０は、ｋ個のサンプリングブロック４０（１）～４０（ｋ）により構成されている。表示部６００には上述のようにｍ行×ｎ列の画素マトリクスが形成されており、これらの画素マトリクスの各列と３対１で対応するように上記サンプリングブロックが設けられている。 <1.5 Configuration of sampling circuit>
FIG. 7 is a circuit diagram for explaining the configuration of the sampling circuit 320 in the present embodiment. As shown in FIG. 7, the sampling circuit 320 includes k sampling blocks 40 (1) to 40 (k). As described above, the display unit 600 is formed with a pixel matrix of m rows × n columns, and the sampling blocks are provided so as to correspond to the columns of these pixel matrices in a three-to-one correspondence.
　サンプリングブロック４０（１）～４０（ｋ）にはそれぞれ選択信号ＳＥＬ（１）～ＳＥＬ（ｋ）が与えられている（対応している）。また、サンプリングブロック４０（１）～４０（ｋ）のそれぞれには互いに異なる３本のソースラインが接続されている。サンプリングブロック４０（ｊ）にはソースラインＳＬ３ｊ－２～ＳＬ３ｊが接続されている（ｊ＝１～ｋ）。各サンプリングブロックには、Ｒ用映像信号Ｖｉｄｒ、Ｇ用映像信号Ｖｉｄｇ、およびＢ用映像信号Ｖｉｄｂが与えられている。 The selection signals SEL (1) to SEL (k) are given (corresponding) to the sampling blocks 40 (1) to 40 (k), respectively. Also, three different source lines are connected to each of the sampling blocks 40 (1) to 40 (k). Source lines SL3j-2 to SL3j are connected to the sampling block 40 (j) (j = 1 to k). Each sampling block is provided with an R video signal Vidr, a G video signal Vidg, and a B video signal Vidb.
　図７に示すように、ソースラインＳＬ１～ＳＬｎは、３本を単位としてソースライン組ＳＧ１～ＳＧｋに組み分けされている。ここで、ソースライン組ＳＧｊは３本のソースラインＳＬ３ｊ－２～ＳＬ３ｊからなっている。これらのソースライン組ＳＧ１～ＳＧｋはそれぞれ、サンプリングブロック４０（１）～４０（ｋ）に対応している。図７において、ソースライン組ＳＧｊ中の、Ｒに対応するソースライン（以下「Ｒ用ソースライン」という）を符号ＳＬｒｊで表し、Ｇに対応するソースライン（以下「Ｇ用ソースライン」という）を符号ＳＬｇｊで表し、Ｂに対応するソースライン（以下「Ｂ用ソースライン」という）を符号ＳＬｂｊで表している。また、Ｒ用ソースラインＳＬｒｊとゲートラインＧＬｉとの交差点に対応して設けられたＲ画素形成部を符号ｒｉｊで表し（ｉ＝１～ｍ）、Ｇ用ソースラインＳＬｇｊとゲートラインＧＬｉとの交差点に対応して設けられたＧ画素形成部を符号ｇｉｊで表し、Ｂ用ソースラインＳＬｂｊとゲートラインＧＬｉとの交差点に対応して設けられてＢ画素形成部を符号ｂｉｊで表している。 As shown in FIG. 7, the source lines SL1 to SLn are grouped into source line groups SG1 to SGk in units of three. Here, the source line set SGj includes three source lines SL3j-2 to SL3j. These source line sets SG1 to SGk correspond to the sampling blocks 40 (1) to 40 (k), respectively. In FIG. 7, a source line corresponding to R (hereinafter referred to as “R source line”) in the source line set SGj is represented by reference sign SLrj, and a source line corresponding to G (hereinafter referred to as “G source line”). A source line corresponding to B (hereinafter referred to as a “B source line”) is represented by a symbol SLbj. Further, an R pixel forming portion provided corresponding to the intersection of the R source line SLrj and the gate line GLi is represented by a symbol rij (i = 1 to m), and the intersection of the G source line SLgj and the gate line GLi. The G pixel formation portion provided corresponding to is represented by reference symbol gij, and the B pixel formation portion provided corresponding to the intersection of the B source line SLbj and the gate line GLi is represented by reference symbol bij.
　図７に示すように、各サンプリングブロックは３つの薄膜トランジスタにより構成されている。以下では、サンプリングブロック４０（ｊ）内の３つの薄膜トランジスタをそれぞれ、「Ｒ用薄膜トランジスタ４１ｒ（ｊ）」、「Ｇ用薄膜トランジスタ４１ｇ（ｊ）」、および「Ｂ用薄膜トランジスタ４１ｂ（ｊ）」という。 As shown in FIG. 7, each sampling block is composed of three thin film transistors. Hereinafter, the three thin film transistors in the sampling block 40 (j) are referred to as “R thin film transistor 41r (j)”, “G thin film transistor 41g (j)”, and “B thin film transistor 41b (j)”, respectively.
　各Ｒ用薄膜トランジスタについては、ゲート端子には当該Ｒ用薄膜トランジスタを含むサンプリングブロックに対応する選択信号が与えられ、ソース端子にはＲ用映像信号Ｖｉｄｒが与えられ、ドレイン端子には当該Ｒ用薄膜トランジスタを含むサンプリングブロックに対応するソースライン組内のＲ用ソースラインが接続されている。各Ｇ用薄膜トランジスタについては、ゲート端子には当該Ｇ用薄膜トランジスタを含むサンプリングブロックに対応する選択信号が与えられ、ソース端子にはＧ用映像信号Ｖｉｄｇが与えられ、ドレイン端子には当該Ｇ用薄膜トランジスタを含むサンプリングブロックに対応するソースライン組内のＧ用ソースラインが接続されている。各Ｂ用薄膜トランジスタについては、ゲート端子には当該Ｂ用薄膜トランジスタを含むサンプリングブロックに対応する選択信号が与えられ、ソース端子にはＢ用映像信号Ｖｉｄｂが与えられ、ドレイン端子には当該Ｂ用薄膜トランジスタを含むサンプリングブロックに対応するソースライン組内のＢ用ソースラインが接続されている。 For each R thin film transistor, a selection signal corresponding to the sampling block including the R thin film transistor is given to the gate terminal, an R video signal Vidr is given to the source terminal, and the R thin film transistor is given to the drain terminal. R source lines in a source line set corresponding to the sampling block to be included are connected. For each G thin film transistor, a gate terminal receives a selection signal corresponding to the sampling block including the G thin film transistor, a source terminal receives a G video signal Vidg, and a drain terminal receives the G thin film transistor. G source lines in the source line set corresponding to the sampling block to be included are connected. For each B thin film transistor, the gate terminal is supplied with a selection signal corresponding to the sampling block including the B thin film transistor, the source terminal is supplied with the B video signal Vidb, and the drain terminal is supplied with the B thin film transistor. A source line for B in the source line set corresponding to the included sampling block is connected.
　このようなサンプリング回路３２０を含むソースドライバ３００により、１水平走査期間において映像信号ＶｉｄをＲ／Ｇ／Ｂの各画素からなる絵素単位で順次にソースラインに与える点順次駆動が実現される。なお、この動作について詳しい説明は後述する。 The source driver 300 including such a sampling circuit 320 realizes dot-sequential driving in which the video signal Vid is sequentially supplied to the source line in units of picture elements composed of R / G / B pixels in one horizontal scanning period. This operation will be described in detail later.
　＜１．６　液晶表示装置の動作＞
　本実施形態では、上述のように１フレーム期間が走査期間Ｔ１と、当該走査期間Ｔ１の後に設けられた休止期間Ｔ２とからなっている。ここで、本実施形態に係る液晶表示装置の動作を、走査期間Ｔ１における動作と休止期間Ｔ２における動作とに分けて説明する。 <1.6 Operation of liquid crystal display device>
In the present embodiment, as described above, one frame period is composed of the scanning period T1 and the pause period T2 provided after the scanning period T1. Here, the operation of the liquid crystal display device according to the present embodiment will be described separately for the operation in the scanning period T1 and the operation in the pause period T2.
　＜１．６．１　走査期間の動作＞
　図８は、本実施形態に係る液晶表示装置の走査期間Ｔ１における動作を説明するための信号波形図である。図８に示すように、走査期間Ｔ１では走査信号ＧＳ（１）～ＧＳ（ｍ）がゲートクロック信号ＧＣＫに基づいて順次に選択状態になる。各選択期間では、ブロック単位（ソース組単位）でソースラインに映像信号が順次に与えられる。図８では、第１走査選択期間における、ソースドライバ３００の駆動に関する各種信号波形を示している。なお、第１走査選択期間以外の走査選択期間での動作についても同様であるので、その説明を省略する。 <Operation of 1.6.1 Scanning Period>
FIG. 8 is a signal waveform diagram for explaining the operation in the scanning period T1 of the liquid crystal display device according to this embodiment. As shown in FIG. 8, in the scanning period T1, the scanning signals GS (1) to GS (m) are sequentially selected based on the gate clock signal GCK. In each selection period, video signals are sequentially applied to the source line in block units (source group units). FIG. 8 shows various signal waveforms related to driving of the source driver 300 in the first scan selection period. The operation in the scan selection period other than the first scan selection period is the same, and the description thereof is omitted.
　第１走査選択期間において、最初の１サンプリング期間でソーススタートパルス信号ＳＳＰがハイレベル電位になる。その後、第１ソースクロック信号ＳＣＫ１および第２ソースクロック信号ＳＣＫ２に基づいて選択信号ＳＥＬ（１）～ＳＥＬ（ｋ）が順次にハイレベル電位になる。図８に示すように、本実施形態では、走査期間周期ｔｃｋ１は２サンプリング期間である。 In the first scanning selection period, the source start pulse signal SSP becomes a high level potential in the first sampling period. Thereafter, based on the first source clock signal SCK1 and the second source clock signal SCK2, the selection signals SEL (1) to SEL (k) sequentially become a high level potential. As shown in FIG. 8, in this embodiment, the scanning period cycle tck1 is two sampling periods.
　Ｒ用映像信号Ｖｉｄｒは、第ｉ走査選択期間中の第ｊサンプリング期間でＲ画素形成部ｒｉｊに対応する電位となっている（ｉ＝１～ｍ、ｊ＝１～ｋ）。Ｇ用映像信号Ｖｉｄｇは、第ｉ走査選択期間中の第ｊサンプリング期間でＧ画素形成部ｇｉｊに対応する電位となっている。Ｂ用映像信号Ｖｉｄｂは、第ｉ走査選択期間中の第ｊサンプリング期間でＢ画素形成部ｂｉｊに対応する電位となっている。なお、本実施形態および後述の各実施形態では、１サンプリング期間毎に各映像信号の極性を反転させ且つ互いに隣接する出力信号線に与えられる映像信号の極性を互いに反転させると共に、フレーム期間毎に各映像信号の極性を反転させることにより極性反転駆動を行っているが、本発明はこれに限定されるものではない。 The video signal Vidr for R has a potential corresponding to the R pixel formation portion rij in the jth sampling period in the i-th scanning selection period (i = 1 to m, j = 1 to k). The G video signal Vidg has a potential corresponding to the G pixel forming portion gij in the jth sampling period in the i-th scanning selection period. The B video signal Vidb has a potential corresponding to the B pixel formation portion bij in the jth sampling period in the i-th scanning selection period. In this embodiment and each of the embodiments described later, the polarity of each video signal is inverted every sampling period, the polarities of the video signals applied to the output signal lines adjacent to each other are inverted, and every frame period. Although the polarity inversion drive is performed by inverting the polarity of each video signal, the present invention is not limited to this.
　第１サンプリング期間では選択信号ＳＥＬ（１）がハイレベル電位になるので、図７に示すサンプリングブロック４０（１）内のＲ用薄膜トランジスタ４１ｒ（１）、Ｇ用薄膜トランジスタ４１ｇ（１）、およびＢ用薄膜トランジスタ４１ｂ（１）がオン状態になる。このため、Ｒ画素形成部ｒ１１に対応する電位になっているＲ用映像信号ＶｉｄｒがＲ用ソースラインＳＬｒ１に与えられ、Ｇ画素形成部ｇ１１に対応する電位になっているＧ用映像信号ＶｉｄｇがＧ用ソースラインＳＬｇ１に与えられ、Ｂ画素形成部ｂ１１に対応する電位になっているＢ用映像信号ＶｉｄｂがＢ用ソースラインＳＬｂ１に与えられる。この第１サンプリング期間では、Ｒ用ソースラインＳＬｒ１、Ｇ用ソースラインＳＬｇ１、およびＢ用ソースラインＳＬｂ１の電位は、先行の休止期間Ｔ２における電位（Ｖｃｏｍ電位）からそれぞれ、正極性、負極性、および正極性に変化する。これらのＲ用ソースラインＳＬｒ１、Ｇ用ソースラインＳＬｇ１、およびＢ用ソースラインＳＬｂ１の電位はそれぞれ、Ｒ画素形成部ｒ１１、Ｇ画素形成部ｇ１１、およびＢ画素形成部ｂ１１に書き込まれる。なお、第２～ｍサンプリング期間での動作も同様であるので、その説明を省略する。 Since the selection signal SEL (1) is at a high level potential in the first sampling period, the R thin film transistor 41r (1), the G thin film transistor 41g (1), and the B use in the sampling block 40 (1) shown in FIG. The thin film transistor 41b (1) is turned on. For this reason, the R video signal Vidr having a potential corresponding to the R pixel formation portion r11 is given to the R source line SLr1, and the G video signal Vidg having a potential corresponding to the G pixel formation portion g11 is obtained. The B video signal Vidb, which is given to the G source line SLg1 and has a potential corresponding to the B pixel formation portion b11, is given to the B source line SLb1. In the first sampling period, the potentials of the R source line SLr1, the G source line SLg1, and the B source line SLb1 are positive, negative, and negative, respectively, from the potential (Vcom potential) in the preceding pause period T2. Change to positive polarity. The potentials of the R source line SLr1, the G source line SLg1, and the B source line SLb1 are written to the R pixel forming portion r11, the G pixel forming portion g11, and the B pixel forming portion b11, respectively. Since the operation in the second to m sampling periods is the same, the description thereof is omitted.
　以上のような１サンプリング期間が繰り返されることにより１走査選択期間の動作が実現され、この１走査選択期間が繰り返されることにより走査期間Ｔ１の動作が実現される。 The operation of one scanning selection period is realized by repeating the one sampling period as described above, and the operation of the scanning period T1 is realized by repeating this one scanning selection period.
　＜１．６．２　休止期間の動作＞
　図９は、本実施形態に係る液晶表示装置の休止期間Ｔ２における動作を説明するための信号波形図である。図９に示すように、休止期間Ｔ２では、ｍ本のゲートラインＧＬ１～ＧＬｍ（走査信号ＧＳ（１）～ＧＳ（ｍ））のいずれもがローレベル電位になっている。実施形態および後述の各実施形態では、休止期間Ｔ２が走査期間Ｔ１よりも長く設けられている。ただし、本発明はこれに限定されるものではなく、休止期間Ｔ２が走査期間Ｔ１よりも短くても良い。図９では、休止期間Ｔ２における最初の、Ｘ回分の１走査選択期間（１水平走査期間）の長さに相当する期間（以下「Ｘ水平走査期間」という）でのソースドライバ３００の駆動に関する各種信号波形を示している。ここで、Ｘは例えば２以上の整数であるが、本発明はこれに限定されるものではない。なお、他のＸ水平走査期間での動作についても同様であるので、その説明を省略する。 <1.6.2 Operation during idle period>
FIG. 9 is a signal waveform diagram for explaining the operation in the pause period T2 of the liquid crystal display device according to the present embodiment. As shown in FIG. 9, in the pause period T2, all of the m gate lines GL1 to GLm (scanning signals GS (1) to GS (m)) are at the low level potential. In the embodiment and each embodiment described later, the pause period T2 is longer than the scanning period T1. However, the present invention is not limited to this, and the pause period T2 may be shorter than the scanning period T1. In FIG. 9, various types of driving of the source driver 300 in a period (hereinafter referred to as “X horizontal scanning period”) corresponding to the length of the first X scanning selection period (one horizontal scanning period) in the pause period T <b> 2. The signal waveform is shown. Here, X is, for example, an integer of 2 or more, but the present invention is not limited to this. The operation in the other X horizontal scanning periods is the same, and the description thereof is omitted.
　図９に示すように、この休止期間Ｔ２では、第１ソースクロック信号ＳＣＫ１および第２ソースクロック信号ＳＣＫ２は走査期間周期ｔｃｋ１よりも長い周期で、１サンプリング期間でハイレベル電位になる。以下では、休止期間Ｔ２における第１ソースクロック信号ＳＣＫ１および第２ソースクロック信号ＳＣＫ２のそれぞれの周期（以下「休止期間周期」という）を符号ｔｃｋ２で表す。また、休止期間Ｔ２における第１ソースクロック信号ＳＣＫ１および第２ソースクロック信号ＳＣＫ２のそれぞれの周波数（以下「休止期間周波数」という）を符号ｆｃｋ２で表す。また、休止期間Ｔ２における第１ソースクロック信号ＳＣＫ１および第２ソースクロック信号ＳＣＫ２のそれぞれの振幅（以下「休止期間振幅」という）を符号Ｖｃｋ２で表す。 As shown in FIG. 9, in the idle period T2, the first source clock signal SCK1 and the second source clock signal SCK2 are at a high level potential in one sampling period with a period longer than the scanning period period tck1. In the following, each cycle of the first source clock signal SCK1 and the second source clock signal SCK2 in the pause period T2 (hereinafter referred to as “pause period cycle”) is denoted by reference symbol tck2. In addition, the respective frequencies (hereinafter referred to as “pause period frequencies”) of the first source clock signal SCK1 and the second source clock signal SCK2 in the idle period T2 are denoted by a symbol fck2. Further, the respective amplitudes (hereinafter referred to as “pause period amplitude”) of the first source clock signal SCK1 and the second source clock signal SCK2 in the pause period T2 are represented by reference sign Vck2.
　上述のように、休止期間周期ｔｃｋ２は走査期間周期ｔｃｋ１よりも長い。すなわち、休止期間周波数ｆｃｋ２は走査期間周波数ｆｃｋ１よりも低い。ここで、走査期間周波数ｆｃｋ１は休止期間周波数ｆｃｋ２の整数倍であることが望ましい。これにより、表示制御回路２００等を簡易な構成とすることができる。また、走査期間周波数ｆｃｋ１は休止期間周波数ｆｃｋ２の２倍以上であることが望ましい。言い換えると、休止期間周波数ｆｃｋ２は走査期間周波数ｆｃｋ１の１／２倍以下であることが望ましい。これにより、ソースドライバ３００の駆動に要する消費電力を十分に低減することができる。このようなソースクロック信号ＳＣＫの周波数（周期）の制御は、例えば表示制御回路２００において行われる。なお、本実施形態では、休止期間振幅Ｖｃｋ２および走査期間振幅Ｖｃｋ１は互いに同じ大きさである。 As described above, the idle period cycle tck2 is longer than the scanning period cycle tck1. That is, the idle period frequency fck2 is lower than the scanning period frequency fck1. Here, it is desirable that the scanning period frequency fck1 is an integral multiple of the idle period frequency fck2. Thereby, the display control circuit 200 and the like can have a simple configuration. Further, it is desirable that the scanning period frequency fck1 is at least twice the idle period frequency fck2. In other words, it is desirable that the idle period frequency fck2 is ½ times or less of the scanning period frequency fck1. Thereby, the power consumption required for driving the source driver 300 can be sufficiently reduced. Such control of the frequency (cycle) of the source clock signal SCK is performed in the display control circuit 200, for example. In the present embodiment, the idle period amplitude Vck2 and the scanning period amplitude Vck1 are the same.
　図９に示すように、休止期間Ｔ２ではＲ用映像信号Ｖｉｄｒ、Ｇ用映像信号Ｖｉｄｇ、およびＢ用映像信号ＶｉｄｂがＶｃｏｍ電位になっている。なお、Ｖｃｏｍ電位に限らず、他の固定電位となっていても良い。また、休止期間Ｔ２では走査信号ＧＳ（１）～ＧＳ（ｍ）はハイレベル電位にならないので、Ｒ画素形成部ｒｉｊ、Ｇ画素形成部ｇｉｊ、およびＢ画素形成部ｂｉｊには映像信号は書き込まれない。 As shown in FIG. 9, in the idle period T2, the R video signal Vidr, the G video signal Vidg, and the B video signal Vidb are at the Vcom potential. Note that the potential is not limited to the Vcom potential, and may be another fixed potential. Further, since the scanning signals GS (1) to GS (m) do not become a high level potential during the pause period T2, the video signal is written to the R pixel forming portion rij, the G pixel forming portion gij, and the B pixel forming portion bij. Absent.
　図９に示すように、Ｘ水平走査期間での最初の１サンプリング期間においてソーススタートパルス信号ＳＳＰがハイレベル電位になる。したがって、走査期間周波数ｆｃｋ１よりも低い休止期間周波数ｆｃｋ２である第１ソースクロック信号ＳＣＫ１および第２ソースクロック信号ＳＣＫ２に基づいて、選択信号ＳＥＬ（１）～ＳＥＬ（ｋ）が順次にハイレベル電位になる。 As shown in FIG. 9, the source start pulse signal SSP becomes a high level potential in the first sampling period in the X horizontal scanning period. Therefore, the selection signals SEL (1) to SEL (k) are sequentially set to the high level potential on the basis of the first source clock signal SCK1 and the second source clock signal SCK2 having the idle period frequency fck2 lower than the scanning period frequency fck1. Become.
　図１０は、本実施形態における双安定回路の動作のうち、特に休止期間Ｔ２での動作を説明するための信号波形図である。なお、他の双安定回路の動作も同様であるので、説明を省略する。休止期間Ｔ２での動作説明においては、セット信号Ｓがハイレベル電位になっている１水平走査期間を「セット期間」といい、セット期間の終了時点からサンプリング選択期間開始時点までの期間を「選択待ち期間」といい、サンプリング選択期間終了時点からリセット信号Ｒがハイレベル電位に変化する時点までの期間を「リセット待ち期間」といい、リセット信号Ｒがハイレベル電位になっている期間を「リセット期間」という。また、休止期間Ｔ２のうちの、サンプリング選択期間、セット期間、選択待ち期間、リセット待ち期間およびリセット期間以外の期間のことを「通常動作期間」という。 FIG. 10 is a signal waveform diagram for explaining the operation of the bistable circuit in the present embodiment, in particular, the operation in the idle period T2. Since the operation of other bistable circuits is the same, the description thereof is omitted. In the description of the operation in the pause period T2, one horizontal scanning period in which the set signal S is at a high level potential is referred to as a “set period”, and a period from the end of the set period to the start of the sampling selection period is “selected”. The period from the end of the sampling selection period to the time when the reset signal R changes to the high level potential is called the “waiting period”, and the period during which the reset signal R is at the high level potential Period. In addition, a period other than the sampling selection period, the set period, the selection waiting period, the reset waiting period, and the reset period in the suspension period T2 is referred to as a “normal operation period”.
　セット期間（時点ｓ０～ｓ１）の動作については、走査期間Ｔ１におけるセット期間での動作と同様であるので説明を省略する。 The operation in the set period (time points s0 to s1) is the same as the operation in the set period in the scanning period T1, and thus description thereof is omitted.
　選択待ち期間になると（時点ｓ１になると）、セット信号Ｓの電位がハイレベルからローレベルに変化するので薄膜トランジスタＭ３がオフ状態になる（図５を参照）。このため、第１ノードＮ１はフローティング状態になる。また、第１ソースクロック信号ＳＣＫ１はローレベル電位のままである。このため、選択待ち期間では、セット期間における第１ノードＮ１の電位が維持される。なお、第２ソースクロック信号ＳＣＫ２の電位がローレベルに変化するので、薄膜トランジスタＭ２がオフ状態になる。 In the selection waiting period (at time s1), the potential of the set signal S changes from high level to low level, so that the thin film transistor M3 is turned off (see FIG. 5). For this reason, the first node N1 is in a floating state. Further, the first source clock signal SCK1 remains at a low level potential. For this reason, in the selection waiting period, the potential of the first node N1 in the set period is maintained. Note that since the potential of the second source clock signal SCK2 changes to a low level, the thin film transistor M2 is turned off.
　サンプリング選択期間（時点ｓ２～ｓ３）の動作については、走査期間Ｔ１におけるセット期間での動作と同様であるので説明を省略する。 Since the operation in the sampling selection period (time points s2 to s3) is the same as the operation in the set period in the scanning period T1, description thereof will be omitted.
　リセット待ち期間になると（時点ｓ３になると）、第１ソースクロック信号ＳＣＫ１の電位がハイレベルからローレベルに変化するので、薄膜トランジスタＭ１のゲート－ドレイン間の寄生容量の影響により第１ノードＮ１の電位が下降する。この電位の下降量は、上述のブーストストラップによる電位の上昇量に相当する。このため、薄膜トランジスタＭ１はオフ状態にはならない。したがって、上述のように第１ソースクロック信号ＳＣＫ１の電位がハイレベルからローレベルに変化することにより、状態信号Ｚの電位がローレベルに変化する。また、その後も、第１ソースクロック信号ＳＣＫ１の電位はローレベルを維持するので、状態信号Ｚの電位はローレベルを維持する。 In the reset waiting period (at time s3), the potential of the first source clock signal SCK1 changes from the high level to the low level, so that the potential of the first node N1 is influenced by the parasitic capacitance between the gate and the drain of the thin film transistor M1. Descends. This amount of decrease in potential corresponds to the amount of increase in potential due to the above-described boost strap. For this reason, the thin film transistor M1 is not turned off. Therefore, as described above, when the potential of the first source clock signal SCK1 changes from the high level to the low level, the potential of the state signal Z changes to the low level. Further, after that, the potential of the first source clock signal SCK1 is maintained at the low level, so that the potential of the state signal Z is maintained at the low level.
　このようにして、本実施形態では、休止期間Ｔ２において、走査期間Ｔ１における周期よりも長い周期で選択信号ＳＥＬ（１）～ＳＥＬ（ｋ）が順次にハイレベル電位になる。このため、サンプリングブロック４０（１）～４０（ｋ）のそれぞれのＲ用薄膜トランジスタ、Ｇ用薄膜トランジスタ、およびＢ用薄膜トランジスタが順次にオン状態になる。Ｒ用薄膜トランジスタがオン状態になると、Ｖｃｏｍ電位になっているＲ用映像信号ＶｉｄｒがＲ用ソースラインに与えられる。Ｇ用薄膜トランジスタがオン状態になると、Ｖｃｏｍ電位になっているＧ用映像信号ＶｉｄｇがＧ用ソースラインに与えられる。Ｂ用薄膜トランジスタがオン状態になると、Ｖｃｏｍ電位になっているＢ用映像信号ＶｉｄｂがＢ用ソースラインに与えられる。なお、上述のように休止期間Ｔ２では走査信号ＧＳ（１）～ＧＳ（ｍ）がハイレベル電位にならないので、これらのＲ用ソースライン、Ｇ用ソースライン、Ｂ用ソースラインの電位はそれぞれＲ画素形成部、Ｇ画素形成部、およびＢ画素形成部に書き込まれない。 Thus, in the present embodiment, in the pause period T2, the selection signals SEL (1) to SEL (k) are sequentially set to the high level potential in a period longer than the period in the scanning period T1. Therefore, the R thin film transistor, the G thin film transistor, and the B thin film transistor in each of the sampling blocks 40 (1) to 40 (k) are sequentially turned on. When the R thin film transistor is turned on, the R video signal Vidr having the Vcom potential is applied to the R source line. When the G thin film transistor is turned on, the G video signal Vidg at the Vcom potential is applied to the G source line. When the B thin film transistor is turned on, the B video signal Vidb at the Vcom potential is applied to the B source line. Note that, as described above, the scanning signals GS (1) to GS (m) do not become high level potentials in the idle period T2, and therefore the potentials of these R source line, G source line, and B source line are R respectively. It is not written in the pixel formation portion, the G pixel formation portion, and the B pixel formation portion.
　＜１．７　考察＞
　上記従来のソースドライバモノリシック型の液晶表示装置において特許文献２に記載の駆動方法を単純に用いる場合、休止期間Ｔ２においてソースラインを所定電位（Ｖｃｏｍ電位）に固定するために、休止期間Ｔ２においてサンプリング回路３２０内の各薄膜トランジスタをオフ状態に維持するか、または、休止期間Ｔ２において当該薄膜トランジスタをオン状態維持すると共に各映像信号をＶｃｏｍ電位にすることが考えられる。 <1.7 Consideration>
When the driving method described in Patent Document 2 is simply used in the above-described conventional source driver monolithic liquid crystal display device, sampling is performed in the rest period T2 in order to fix the source line to a predetermined potential (Vcom potential) in the rest period T2. It is conceivable that each thin film transistor in the circuit 320 is kept in an off state, or that the thin film transistor is kept in an on state and the video signal is set to a Vcom potential in the pause period T2.
　しかし、休止期間Ｔ２においてサンプリング回路３２０内の各薄膜トランジスタをオフ状態に維持すると、ソースラインがフローティング状態になる。このため、休止期間Ｔ２においてソースラインがノイズ等の影響を受けやすくなってしまう。ソースラインと画素電極との間には寄生容量があり、画素電極もフローティング状態なので、ソースラインのノイズは容量カップリングにより画素電位へも影響する。その結果、表示品位の低下を招くおそれがある。これに対して、本実施形態では、休止期間Ｔ２において、第１ソースクロック信号ＳＣＫ１および第２ソースクロック信号ＳＣＫ２にシフトレジスタ３１０が動作することにより、選択信号ＳＥＬ（１）～ＳＥＬ（ｋ）が順次にハイレベル電位になる。このため、各選択信号がハイレベルになるタイミングでこれに対応するソースライン組内のソースラインにＶｃｏｍ電位が与えられることとなる。これにより、休止期間Ｔ２においてソースラインＳＬ１～ＳＬｍがフローティング状態になることによりこれらのソースラインＳＬ１～ＳＬｍが受けるノイズ等の影響が低減される。その結果、表示品位の低下を抑制することができる。 However, if each thin film transistor in the sampling circuit 320 is maintained in the off state in the pause period T2, the source line is in a floating state. For this reason, the source line is likely to be affected by noise or the like in the pause period T2. Since there is a parasitic capacitance between the source line and the pixel electrode, and the pixel electrode is also in a floating state, noise in the source line also affects the pixel potential due to capacitive coupling. As a result, the display quality may be degraded. In contrast, in the present embodiment, the selection signals SEL (1) to SEL (k) are generated by the shift register 310 operating on the first source clock signal SCK1 and the second source clock signal SCK2 in the pause period T2. Sequentially becomes a high level potential. Therefore, the Vcom potential is applied to the source line in the source line group corresponding to each selection signal at the high level. As a result, the influence of noise and the like received by the source lines SL1 to SLm is reduced by the source lines SL1 to SLm being in the floating state in the pause period T2. As a result, it is possible to suppress deterioration in display quality.
　一方、休止期間Ｔ２においてサンプリング回路３２０内の各薄膜トランジスタをオン状態維持すると共に各映像信号をＶｃｏｍ電位にすると、薄膜トランジスタのゲート端子にハイレベル電位を与え続ける必要がある。この薄膜トランジスタにゲートバイアスストレスが長時間掛かることとなるので、この薄膜トランジスタおけるしきい値変動が大きくなる。その結果、この薄膜トランジスタが低下する。これに対して、本実施形態では、休止期間Ｔ２において、第１ソースクロック信号ＳＣＫ１および第２ソースクロック信号ＳＣＫ２に基づいてシフトレジスタ３１０が動作することにより、各Ｘ水平走査期間で選択信号ＳＥＬ（１）～ＳＥＬ（ｋ）が順次にハイレベル電位になる。このように、各Ｘ水平走査期間中の１サンプリング期間にのみ、サンプリング回路３２０内の薄膜トランジスタのゲート端子にハイレベル電位が与えられる。これにより、本実施形態ではこの薄膜トランジスタに掛かるゲートバイアスストレスが低減されるので、この薄膜トランジスタにおけるしきい値変動が低減される。その結果、サンプリング回路３２０内の各薄膜トランジスタの駆動能力（信頼性）の低下を抑制することができる。 On the other hand, if each thin film transistor in the sampling circuit 320 is kept on during the rest period T2 and each video signal is set to the Vcom potential, it is necessary to continuously apply a high level potential to the gate terminal of the thin film transistor. Since the gate bias stress is applied to the thin film transistor for a long time, the threshold fluctuation in the thin film transistor is increased. As a result, the thin film transistor is lowered. On the other hand, in this embodiment, the shift register 310 operates based on the first source clock signal SCK1 and the second source clock signal SCK2 in the pause period T2, so that the selection signal SEL ( 1) to SEL (k) sequentially become high level potentials. As described above, the high level potential is applied to the gate terminal of the thin film transistor in the sampling circuit 320 only in one sampling period in each X horizontal scanning period. Thereby, in this embodiment, since the gate bias stress applied to the thin film transistor is reduced, the threshold fluctuation in the thin film transistor is reduced. As a result, a decrease in driving capability (reliability) of each thin film transistor in the sampling circuit 320 can be suppressed.
　＜１．８　実現例＞
　本実施形態におけるサンプリング回路３２０内の各薄膜トランジスタの半導体層には、例えば、ａ－Ｓｉまたは酸化物半導体等を用いることができる。なお、酸化物半導体としては、典型的には、インジウム、ガリウム、亜鉛、および酸素を主成分とする酸化物半導体であるＩｎＧａＺｎＯx（以下、「ＩＧＺＯ」という）が用いられるが本発明はこれに限定されるものではない。例えば、インジウム、ガリウム、亜鉛、銅、珪素、錫、アルミニウム、カルシウム、ゲルマニウム、および鉛のうち少なくとも１つを含む酸化物半導体であれば良い。 <1.8 Implementation example>
For example, a-Si or an oxide semiconductor can be used for the semiconductor layer of each thin film transistor in the sampling circuit 320 in the present embodiment. Note that as the oxide semiconductor, typically, InGaZnO x (hereinafter referred to as “IGZO”), which is an oxide semiconductor mainly containing indium, gallium, zinc, and oxygen, is used. It is not limited. For example, any oxide semiconductor containing at least one of indium, gallium, zinc, copper, silicon, tin, aluminum, calcium, germanium, and lead may be used.
　図１１は、ａ－ＳｉＴＦＴおよびＩＧＺＯを半導体層に用いたＴＦＴ（以下「ＩＧＺＯＴＦＴ」という）のドレイン電流－ゲート電圧特性を示す図である。図１１において、横軸はゲート電圧Ｖｇを表し、縦軸はドレイン電流Ｉｄｓを表している。図１１に示すように、ＩＧＺＯＴＦＴのリーク電流はａ－ＳｉＴＦＴのリーク電流の１／１０００以下であると共に、ＩＧＺＯＴＦＴのオン電流はａ－ＳｉＴＦＴのオン電流の約２０倍である。 FIG. 11 is a graph showing drain current-gate voltage characteristics of a TFT using a-Si TFT and IGZO as a semiconductor layer (hereinafter referred to as “IGZOTFT”). In FIG. 11, the horizontal axis represents the gate voltage Vg, and the vertical axis represents the drain current Ids. As shown in FIG. 11, the leakage current of the IGZOTFT is 1/1000 or less of the leakage current of the a-Si TFT, and the on-current of the IGZOTFT is about 20 times the on-current of the a-Si TFT.
　ＩＧＺＯＴＦＴは上述のようにリーク電流が小さいので、ＩＧＺＯＴＦＴを本実施形態におけるサンプリング回路３２０内の各薄膜トランジスタとして用いた場合、ａ－ＳｉＴＦＴをこの薄膜トランジスタとして用いた場合によりも、ソースドライバ３００（サンプリング回路３２０）の駆動電力を低減することができる（１／１００以下）。 Since the IGZOTFT has a small leakage current as described above, when the IGZOTFT is used as each thin film transistor in the sampling circuit 320 in the present embodiment, the source driver 300 (sampling circuit 320 is used even when the a-Si TFT is used as this thin film transistor. ) Driving power can be reduced (1/100 or less).
　また、ＩＧＺＯＴＦＴは上述のようにオン電流が大きいので、ＩＧＺＯＴＦＴを用いた場合、ａ－ＳｉＴＦＴを用いた場合に比べてＴＦＴのサイズを１／２０程度に小さくすることができる。 In addition, since the IGZOTFT has a large on-state current as described above, when the IGZOTFT is used, the size of the TFT can be reduced to about 1/20 compared to the case where the a-Si TFT is used.
　なお、ａ－ＳｉＴＦＴを用いた場合は、ＩＧＺＯＴＦＴを用いた場合よりも低コストで本実施形態を実現することができる。 Note that, when an a-Si TFT is used, this embodiment can be realized at a lower cost than when an IGZO TFT is used.
　＜１．９　効果＞
　本実施形態によれば、点順次駆動方式のソースドライバモノリシック型の液晶表示装置において、１フレーム期間内で走査期間Ｔ１の後に休止期間Ｔ２が設けられる。休止期間周波数ｆｃｋ２が走査期間周波数ｆｃｋ１よりも低いので、ソースドライバ３００の１フレーム期間全体の駆動周波数が低減される。このため、ソースドライバ３００の駆動に要する消費電力が低減される。また、ソースドライバ３００がモノリシック化されて形成されているので、液晶表示パネル７００の額縁面積が縮小されると共に、ソースドライバ３００のコストが低減される。 <1.9 Effect>
According to the present embodiment, in the source driver monolithic type liquid crystal display device of the dot sequential driving method, the pause period T2 is provided after the scanning period T1 within one frame period. Since the idle period frequency fck2 is lower than the scanning period frequency fck1, the driving frequency of the entire source frame of the source driver 300 is reduced. For this reason, the power consumption required for driving the source driver 300 is reduced. Further, since the source driver 300 is monolithically formed, the frame area of the liquid crystal display panel 700 is reduced and the cost of the source driver 300 is reduced.
　また、本実施形態によれば、休止期間Ｔ２において、各選択信号がハイレベルになるタイミングでこれに対応するソースライン組内のソースラインにＶｃｏｍ電位が与えられる。このため、休止期間Ｔ２においてソースラインＳＬ１～ＳＬｍがフローティング状態になることによりこれらのソースラインＳＬ１～ＳＬｍが受けるノイズ等の影響が低減される。これにより、表示品位の低下を抑制することができる。また、休止期間Ｔ２において、各Ｘ水平走査期間中の１サンプリング期間にのみ、サンプリング回路３２０内の各薄膜トランジスタのゲート端子にハイレベル電位が与えられるので、この薄膜トランジスタに掛かるゲートバイアスストレスが低減される。その結果、サンプリング回路３２０内の各薄膜トランジスタの駆動能力（信頼性）の低下を抑制することができる。 Further, according to the present embodiment, the Vcom potential is applied to the source line in the corresponding source line group at the timing when each selection signal becomes high level in the pause period T2. For this reason, since the source lines SL1 to SLm are in the floating state in the suspension period T2, the influence of noise and the like received by these source lines SL1 to SLm is reduced. Thereby, the fall of display quality can be suppressed. In addition, since the high level potential is applied to the gate terminal of each thin film transistor in the sampling circuit 320 only in one sampling period in each X horizontal scanning period in the pause period T2, the gate bias stress applied to the thin film transistor is reduced. . As a result, a decrease in driving capability (reliability) of each thin film transistor in the sampling circuit 320 can be suppressed.
　また、本実施形態によれば、休止期間Ｔ２が走査期間Ｔ１よりも長く設けられているので、さらなる消費電力化を図ることができる。 Further, according to the present embodiment, since the pause period T2 is provided longer than the scanning period T1, further power consumption can be achieved.
　ＩＧＺＯＴＦＴを本実施形態におけるサンプリング回路３２０内の各薄膜トランジスタとして用いた場合には、ＩＧＺＯＴＦＴのリーク電流が十分に小さいので、休止期間周波数ｆｃｋ２をさらに低くすることができる。このため、消費電力を低減することができる。また、この場合、ＩＧＺＯＴＦＴのオン電流が十分に大きいので、ＴＦＴサイズを十分に小さくすることができる。これにより、さらなる狭額縁化を図ることができる。なお、ＩＧＺＯＴＦＴを、双安定回路内の各薄膜トランジスタとしても用いることにより、さらなる低消費電力化および狭額縁化を図ることができる。 When the IGZOTFT is used as each thin film transistor in the sampling circuit 320 in the present embodiment, the leakage current of the IGZOTFT is sufficiently small, so that the idle period frequency fck2 can be further reduced. For this reason, power consumption can be reduced. In this case, since the on-current of the IGZO TFT is sufficiently large, the TFT size can be sufficiently reduced. Thereby, further narrowing of the frame can be achieved. Note that by using the IGZOTFT as each thin film transistor in the bistable circuit, further reduction in power consumption and narrowing of the frame can be achieved.
　一方、ａ－ＳｉＴＦＴを本実施形態におけるサンプリング回路３２０内の各薄膜トランジスタとして用いた場合には、さらなる低コスト化を図ることができる。 On the other hand, when the a-Si TFT is used as each thin film transistor in the sampling circuit 320 in this embodiment, the cost can be further reduced.
　＜２．第２の実施形態＞
　＜２．１　休止期間の動作＞
　図１２は、本発明の第２の実施形態における液晶表示装置の休止期間Ｔ２での動作を説明するための信号波形図である。なお、本実施形態は、休止期間の動作を除き上記第１の実施形態と同様であるので、当該同様の部分についての説明を省略する。本実施形態における休止期間振幅Ｖｃｋ２は走査期間振幅Ｖｃｋ１よりも小さい。なお、休止期間Ｔ２においてサンプリング回路３２０内の各薄膜トランジスタを確実にオン状態にするためには、この薄膜トランジスタのしきい値電圧よりも大きい必要がある。すなわち、本実施形態における休止期間振幅Ｖｃｋは、走査期間振幅Ｖｃｋ２よりも小さく且つサンプリング回路３２０内の各薄膜トランジスタのしきい値電圧よりも大きい。 <2. Second Embodiment>
<2.1 Operation during the suspension period>
FIG. 12 is a signal waveform diagram for explaining the operation in the pause period T2 of the liquid crystal display device according to the second embodiment of the present invention. Since the present embodiment is the same as the first embodiment except for the operation during the suspension period, the description of the same portion is omitted. In the present embodiment, the pause period amplitude Vck2 is smaller than the scanning period amplitude Vck1. Note that, in order to ensure that each thin film transistor in the sampling circuit 320 is turned on in the pause period T2, it is necessary to be higher than the threshold voltage of this thin film transistor. That is, the pause period amplitude Vck in this embodiment is smaller than the scanning period amplitude Vck2 and larger than the threshold voltage of each thin film transistor in the sampling circuit 320.
　＜２．２　効果＞
　本実施形態によれば、休止期間Ｔ２における第１ソースクロック信号ＳＣＫ１および第２ソースクロック信号ＳＣＫ２のそれぞれの振幅である休止期間振幅Ｖｃｋ２が、走査期間Ｔ１における第１ソースクロック信号ＳＣＫ１および第２ソースクロック信号ＳＣＫ２のそれぞれの振幅である走査期間振幅Ｖｃｋ１よりも小さい。このため、さらなる低消費電力化を図ることができる。また、休止期間Ｔ２にＲ用薄膜トランジスタ、Ｇ用薄膜トランジスタ、およびＢ用薄膜トランジスタに掛かるゲートバイアスストレスがさらに低減されるので、これらのＲ用薄膜トランジスタ、Ｇ用薄膜トランジスタ、およびＢ用薄膜トランジスタのさらなる高信頼性化を図ることができる。 <2.2 Effect>
According to the present embodiment, the pause period amplitude Vck2, which is the amplitude of each of the first source clock signal SCK1 and the second source clock signal SCK2 in the pause period T2, is the first source clock signal SCK1 and the second source in the scan period T1. It is smaller than the scanning period amplitude Vck1 that is the amplitude of each of the clock signals SCK2. For this reason, further reduction in power consumption can be achieved. In addition, since the gate bias stress applied to the R thin film transistor, the G thin film transistor, and the B thin film transistor is further reduced during the suspension period T2, the R thin film transistor, the G thin film transistor, and the B thin film transistor are further improved in reliability. Can be achieved.
　＜３．第３の実施形態＞
　＜３．１　サンプリング回路の構成＞
　図１３は、本発明の第３の実施形態におけるサンプリング回路３２０の構成を説明するための回路図である。なお、本実施形態は、サンプリング回路３２０の構成および液晶表示装置の詳細な動作を除き上記第１の実施形態と同様であるので、当該同様の部分についての説明を省略する。本実施形態では、サンプリングブロック４０（１）～４０（ｋ）とソースラインＳＬ１～ＳＬｎとの関係が上記第１の実施形態と異なり、画素マトリクスの各列と２４対１で対応するようにサンプリングブロックが設けられている。 <3. Third Embodiment>
<3.1 Configuration of sampling circuit>
FIG. 13 is a circuit diagram for explaining the configuration of the sampling circuit 320 according to the third embodiment of the present invention. Since this embodiment is the same as the first embodiment except for the configuration of the sampling circuit 320 and the detailed operation of the liquid crystal display device, the description of the same parts is omitted. In this embodiment, the relationship between the sampling blocks 40 (1) to 40 (k) and the source lines SL1 to SLn is different from that in the first embodiment, and sampling is performed so as to correspond to each column of the pixel matrix on a one-to-one basis. Blocks are provided.
　本実施形態では、映像信号Ｖｉｄが２４個の映像信号Ｖｉｄｒ１～Ｖｉｄｒ８、Ｖｉｄｇ１～Ｖｉｄｇ８、およびＶｉｄｂ１～Ｖｉｄｂ８からなっている。以下では、映像信号Ｖｉｄｒｘを「第ｘＲ用映像信号」といい、映像信号Ｖｉｄｇｘを「第ｘＧ用映像信号」といい、映像信号Ｖｉｄｂｘを「第ｘＢ用映像信号」という（ｘ＝１～８）。第１～第８Ｒ用映像信号Ｖｉｄｒ１～Ｖｉｄｒ８はＲ画素形成部に対応し、第１～８Ｇ用映像信号Ｖｉｄｇ１～Ｖｉｄｇ８はＧ画素形成部に対応し、第１～８Ｂ用映像信号Ｖｉｄｂ１～Ｖｉｄｂ８はＢ画素形成部に対応している。 In this embodiment, the video signal Vid includes 24 video signals Vidr1 to Vidr8, Vidg1 to Vidg8, and Vidb1 to Vidb8. Hereinafter, the video signal Vidrx is referred to as “xR video signal”, the video signal Vidigx is referred to as “xG video signal”, and the video signal Vidbx is referred to as “xB video signal” (x = 1 to 8). . The first to eighth R video signals Vidr1 to Vidr8 correspond to the R pixel forming unit, the first to 8G video signals Vidg1 to Vidg8 correspond to the G pixel forming unit, and the first to 8B video signals Vidb1 to Vidb8 are This corresponds to the B pixel forming portion.
　サンプリングブロック４０（１）～４０（ｋ）にはそれぞれ選択信号ＳＥＬ（１）～ＳＥＬ（ｋ）が与えられている（対応している）。また、サンプリングブロック４０（１）～４０（ｋ）のそれぞれには互いに異なる２４本のソースラインが接続されている。サンプリングブロック４０（ｊ）にはソースラインＳＬ２４ｊ－２３～ＳＬ２４ｊが接続されている（ｊ＝１～ｋ）。各サンプリングブロックには、第１～第８Ｒ用映像信号Ｖｉｄｒ１～Ｖｉｄｒ８、第１～８Ｇ用映像信号Ｖｉｄｇ１～Ｖｉｄｇ８、および第１～８Ｂ用映像信号Ｖｉｄｂ１～Ｖｉｄｂ８が与えられている。 The selection signals SEL (1) to SEL (k) are given (corresponding) to the sampling blocks 40 (1) to 40 (k), respectively. Also, 24 different source lines are connected to each of the sampling blocks 40 (1) to 40 (k). Source lines SL24j-23 to SL24j are connected to the sampling block 40 (j) (j = 1 to k). Each sampling block is provided with first to eighth R video signals Vidr1 to Vidr8, first to 8G video signals Vidg1 to Vidg8, and first to 8B video signals Vidb1 to Vidb8.
　本実施形態では、ソースラインＳＬ１～ＳＬｎが２４本を単位としてソースライン組ＳＧ１～ＳＧｋに組み分けされている。ここで、ソースライン組ＳＧｊは２４本のソースラインＳＬ２４ｊ－２３～ＳＬ２４ｊからなっている。これらのソースライン組ＳＧ１～ＳＧｋはそれぞれ、サンプリングブロック４０（１）～４０（ｋ）に対応している。各ソースライン組内には、同色に対応するソースラインが８本設けられている。図１３において、ソースライン組ＳＧｊ中の８本のＲ用ソースラインをそれぞれ「第ｘＲ用ソースライン」といい、それぞれを符号ＳＬｒｊ＿ｘで表す（ｘ＝１～８）。同様に、ソースライン組ＳＧｊ中の８本のＧ用ソースラインをそれぞれ「第ｘＧ用ソースライン」といい、それぞれを符号ＳＬｇｊ＿ｘで表す。また同様に、ソースライン組ＳＧｊ中の８本のＢ用ソースラインをそれぞれ「第ｘＢ用ソースライン」といい、それぞれ符号ＳＬｂｊ＿ｘで表している。 In this embodiment, the source lines SL1 to SLn are grouped into source line groups SG1 to SGk in units of 24. Here, the source line set SGj is composed of 24 source lines SL24j-23 to SL24j. These source line sets SG1 to SGk correspond to the sampling blocks 40 (1) to 40 (k), respectively. In each source line group, eight source lines corresponding to the same color are provided. In FIG. 13, the eight R source lines in the source line set SGj are referred to as “xR source lines”, and each is represented by a symbol SLrj_x (x = 1 to 8). Similarly, eight G source lines in the source line set SGj are referred to as “xG source lines”, and each is represented by a symbol SLgj_x. Similarly, the eight B source lines in the source line set SGj are referred to as “xB source lines”, and are represented by reference characters SLbj_x.
　また、第ｘＲ用ソースラインＳＬｒｊ＿ｘとゲートラインＧＬｉとの交差点に対応して設けられたＲ画素形成部を符号ｒｉｊ＿ｘで表し（ｉ～ｍ）、第ｘＧ用ソースラインＳＬｇｊ＿ｘとゲートラインＧＬｉとの交差点に対して設けられたＧ画素形成部を符号ｇｉｊ＿ｘで表し、第ｘｂ用ソースラインＳＬｂｊ＿ｘとゲートラインＧＬｉとの交差点に対応して設けられたＧ画素形成部を符号ｂｉｊ＿ｘで表している。 Further, an R pixel forming portion provided corresponding to the intersection of the xR source line SLrj_x and the gate line GLi is denoted by rij_x (i to m), and the intersection of the xG source line SLgj_x and the gate line GLi. A G pixel forming portion provided for the xb is represented by reference symbol gij_x, and a G pixel forming portion provided corresponding to the intersection of the xb source line SLbj_x and the gate line GLi is represented by bij_x.
　各サンプリングブロックは、図１３に示すように２４個の薄膜トランジスタにより構成されている。以下では、サンプリングブロック４０（ｊ）内の２４個の薄膜トランジスタをそれぞれ、第ｘＲ用薄膜トランジスタ４１ｘ１（ｊ）、第ｘＧ用薄膜トランジスタ４１ｇｘ（ｊ）、および第ｘＢ用薄膜トランジスタ４１ｂｘ（ｊ）という（ｘ＝１～８）。 Each sampling block is composed of 24 thin film transistors as shown in FIG. Hereinafter, the 24 thin film transistors in the sampling block 40 (j) are referred to as an xR thin film transistor 41x1 (j), an xG thin film transistor 41gx (j), and an xB thin film transistor 41bx (j), respectively (x = 1). ~ 8).
　各第ｘＲ用薄膜トランジスタについては、ゲート端子には当該第ｘＲ用薄膜トランジスタを含むサンプリングブロックに対応する選択信号が与えられ、ソース端子には第ｘＲ用映像信号Ｖｉｄｒｘが与えられ、ドレイン端子には当該第ｘＲ用薄膜トランジスタを含むサンプリングブロックに対応するソースライン組内の第ｘＲ用ソースラインが接続されている。各第ｘＧ用薄膜トランジスタについては、ゲート端子には当該第ｘＧ用薄膜トランジスタを含むサンプリングブロックに対応する選択信号が与えられ、ソース端子には第ｘＧ用映像信号Ｖｉｄｇｘが与えられ、ドレイン端子には当該第ｘＧ用薄膜トランジスタを含むサンプリングブロックに対応するソースライン組内の第ｘＧ用ソースラインが接続されている。各第ｘＢ用薄膜トランジスタについては、ゲート端子には当該第ｘＢ用薄膜トランジスタを含むサンプリングブロックに対応する選択信号が与えられ、ソース端子には第ｘＢ用映像信号Ｖｉｄｂｘが与えられ、ドレイン端子には当該第ｘＢ用薄膜トランジスタを含むサンプリングブロックに対応するソースライン組内の第ｘＢ用ソースラインが接続されている。 For each xR thin film transistor, the gate terminal is supplied with a selection signal corresponding to the sampling block including the xR thin film transistor, the source terminal is supplied with the xR video signal Vidrx, and the drain terminal is supplied with the second signal. The xR source line in the source line set corresponding to the sampling block including the xR thin film transistor is connected. For each xG thin film transistor, the gate terminal is supplied with a selection signal corresponding to the sampling block including the xG thin film transistor, the source terminal is supplied with the xG video signal Vidgx, and the drain terminal is supplied with the corresponding second signal. The xG source line in the source line set corresponding to the sampling block including the xG thin film transistor is connected. For each xB thin film transistor, a selection signal corresponding to the sampling block including the xB thin film transistor is given to the gate terminal, the xB video signal Vidbx is given to the source terminal, and the corresponding xth video signal Vidbx is given to the drain terminal. The xB source line in the source line set corresponding to the sampling block including the xB thin film transistor is connected.
　このようなサンプリング回路３２０を含むソースドライバ３００により、１水平走査期間において映像信号Ｖｉｄをブロック単位（ソース組単位）で順次にソースラインに与えて複数の絵素を同時に書き込むブロック順次駆動が実現される。なお、この動作について詳しい説明は後述する。 The source driver 300 including such a sampling circuit 320 realizes block sequential driving in which a video signal Vid is sequentially applied to a source line in block units (source group units) and a plurality of picture elements are simultaneously written in one horizontal scanning period. The This operation will be described in detail later.
　＜３．２　液晶表示装置の動作＞
　＜３．２．１　走査期間の動作＞
　図１４は、本実施形態に係る液晶表示装置の走査期間Ｔ１における動作を説明するための信号波形図である。ここで、本実施形態において上記第１の実施形態との共通部分については適宜説明を省略する。図１４では、第１走査選択期間における、ソースドライバ３００の駆動に関する各種信号波形を示している。なお、第１走査選択期間以外の走査選択期間での動作についても同様であるので、その説明を省略する。 <3.2 Operation of liquid crystal display device>
<3.2.1 Operation during scanning period>
FIG. 14 is a signal waveform diagram for explaining the operation in the scanning period T1 of the liquid crystal display device according to this embodiment. Here, in this embodiment, the description of the common parts with the first embodiment is omitted as appropriate. FIG. 14 shows various signal waveforms related to driving of the source driver 300 in the first scan selection period. The operation in the scan selection period other than the first scan selection period is the same, and the description thereof is omitted.
　第ｘＲ映像信号Ｖｉｄｒｘは、第ｉ走査選択期間中の第ｊサンプリング期間で第ｘＲ画素形成部ｒｉｊ＿ｘに対応する電位となっている（ｘ＝１～８、ｉ＝１～ｍ、ｊ＝１～ｋ）。第ｘＧ映像信号Ｖｉｄｇｘは、第ｉ走査選択期間中の第ｊサンプリング期間で第ｘＧ画素形成部ｇｉｊ＿ｘに対応する電位となっている。第ｘＢ映像信号Ｖｉｄｂｘは、第ｉ走査選択期間中の第ｊサンプリング期間で第ｘＢ画素形成部ｂｉｊ＿ｘに対応する電位となっている。 The xR video signal Vidrx has a potential corresponding to the xR pixel formation unit rij_x in the jth sampling period in the i-th scanning selection period (x = 1 to 8, i = 1 to m, j = 1 to k). The xG video signal Vidgx has a potential corresponding to the xG pixel forming unit gij_x in the jth sampling period in the i-th scanning selection period. The xB video signal Vidbx has a potential corresponding to the xB pixel formation portion bij_x in the jth sampling period in the i-th scanning selection period.
　第１サンプリング期間では選択信号ＳＥＬ（１）がハイレベル電位になるので、図１３に示すサンプリングブロック４０（１）内の第ｘＲ用薄膜トランジスタ４１ｒｘ（１）、第ｘＧ用薄膜トランジスタ４１ｇｘ（１）、および第ｘＢ用薄膜トランジスタ４１ｂｘ（１）がオン状態になる。このため、Ｒ画素形成部ｒ１１＿ｘに対応する電位になっている第ｘＲ用映像信号Ｖｉｄｒｘが第ｘＲ用ソースラインＳＬｒ１＿ｘに与えられ、Ｇ画素形成部ｇ１１＿ｘに対応する電位になっている第ｘＧ用映像信号Ｖｉｄｇｘが第ｘＧ用ソースラインＳＬｇ１＿ｘに与えられ、Ｂ画素形成部ｂ１１＿ｘに対応する電位になっている第ｘＢ用映像信号Ｖｉｄｂｘが第ｘＢ用ソースラインＳＬｂ１＿ｘに与えられる。この第１サンプリング期間では、第ｘＲ用ソースラインＳＬｒ１＿ｘ、第ｘＧ用ソースラインＳＬｇ１＿ｘ、および第ｘＢ用ソースラインＳＬｂ１＿ｘの電位は、先行の休止期間Ｔ２における電位（Ｖｃｏｍ電位）から正極性または負極性に変化する。これらの第ｘＲ用ソースラインＳＬｒ１＿ｘ、第ｘＧ用ソースラインＳＬｇ１＿ｘ、および第ｘＢ用ソースラインＳＬｂ１＿ｘの電位はそれぞれ、Ｒ画素形成部ｒ１１＿ｘ、Ｇ画素形成部ｇ１１＿ｘ、およびＢ画素形成部ｂ１１＿ｘに書き込まれる。なお、第２～ｍサンプリング期間での動作も同様であるので、その説明を省略する。 Since the selection signal SEL (1) becomes a high level potential in the first sampling period, the xR thin film transistor 41rx (1), the xG thin film transistor 41gx (1) in the sampling block 40 (1) shown in FIG. The xB thin film transistor 41bx (1) is turned on. For this reason, the xR video signal Vidrx having a potential corresponding to the R pixel forming portion r11_x is supplied to the xR source line SLr1_x, and the xG video having a potential corresponding to the G pixel forming portion g11_x. The signal Vidx is supplied to the xG source line SLg1_x, and the xB video signal Vidbx having a potential corresponding to the B pixel formation portion b11_x is supplied to the xB source line SLb1_x. In the first sampling period, the potentials of the xR source line SLr1_x, the xG source line SLg1_x, and the xB source line SLb1_x change from the potential (Vcom potential) in the preceding pause period T2 to a positive polarity or a negative polarity. Change. The potentials of the xR source line SLr1_x, the xG source line SLg1_x, and the xB source line SLb1_x are written to the R pixel formation portion r11_x, the G pixel formation portion g11_x, and the B pixel formation portion b11_x, respectively. Since the operation in the second to m sampling periods is the same, the description thereof is omitted.
　以上のような１サンプリング期間が繰り返されることにより１走査選択期間の動作が実現され、この１走査選択期間が繰り返されることにより走査期間Ｔ１の動作が実現される。 The operation of one scanning selection period is realized by repeating the one sampling period as described above, and the operation of the scanning period T1 is realized by repeating this one scanning selection period.
　＜３．２．２　休止期間の動作＞
　図１５は、本実施形態に係る液晶表示装置の休止期間Ｔ２における動作を説明するための信号波形図である。図１５に示すように、この休止期間Ｔ２では第ｘＲ用Ｖｉｄｒｘ、第ｘＧ用Ｖｉｄｇｘ、および第ｘＢ用ＶｉｄｂｘがＶｃｏｍ電位になっている。なお、Ｖｃｏｍ電位に限らず、他の固定電位となっていても良い。 <3.2.2 Operation during idle period>
FIG. 15 is a signal waveform diagram for explaining the operation in the pause period T2 of the liquid crystal display device according to the present embodiment. As shown in FIG. 15, the xR Vidrx, the xG Viggx, and the xB Vidbx are at the Vcom potential in the suspension period T2. Note that the potential is not limited to the Vcom potential, and may be another fixed potential.
　本実施形態では、上記第１の実施形態と同様に、休止期間Ｔ２において、走査期間Ｔ１における周期よりも長い周期で選択信号ＳＥＬ（１）～ＳＥＬ（ｋ）が順次にハイレベル電位になる。このため、サンプリングブロック４０（１）～４０（ｋ）のそれぞれの第ｘＲ用薄膜トランジスタ、第ｘＧ用薄膜トランジスタ、および第ｘＢ用薄膜トランジスタが順次にオン状態になる（ｘ＝１～８）。第ｘＲ用薄膜トランジスタがオン状態になると、Ｖｃｏｍ電位になっている第ｘＲ用映像信号Ｖｉｄｒｘが第ｘＲ用ソースラインに与えられる。第ｘＧ用薄膜トランジスタがオン状態になると、Ｖｃｏｍ電位になっている第ｘＧ用映像信号Ｖｉｄｇｘが第ｘＧ用ソースラインに与えられる。第ｘＢ用薄膜トランジスタがオン状態になると、Ｖｃｏｍ電位になっている第ｘＢ用映像信号Ｖｉｄｂｘが第ｘＢ用ソースラインに与えられる。なお、上述のように休止期間Ｔ２では走査信号ＧＳ（１）～ＧＳ（ｍ）がハイレベル電位にならないので、これらの第ｘＲ用ソースライン、第ｘＧ用ソースライン、第ｘＢ用ソースラインの電位はそれぞれＲ画素形成部、Ｇ画素形成部、およびＢ画素形成部に書き込まれない。 In the present embodiment, as in the first embodiment, in the pause period T2, the selection signals SEL (1) to SEL (k) sequentially become a high level potential in a period longer than the period in the scanning period T1. Therefore, the xR thin film transistor, the xG thin film transistor, and the xB thin film transistor in each of the sampling blocks 40 (1) to 40 (k) are sequentially turned on (x = 1 to 8). When the xR thin film transistor is turned on, the xR video signal Vidrx having the Vcom potential is applied to the xR source line. When the xG thin film transistor is turned on, the xG video signal Vidgx at the Vcom potential is applied to the xG source line. When the xB thin film transistor is turned on, the xB video signal Vidbx having the Vcom potential is applied to the xB source line. Note that, as described above, the scanning signals GS (1) to GS (m) do not become a high level potential in the pause period T2, and therefore, the potentials of the xR source line, the xG source line, and the xB source line. Are not written in the R pixel forming portion, the G pixel forming portion, and the B pixel forming portion, respectively.
　＜３．３　効果＞
　本実施形態によれば、上記第１の実施形態によりも映像信号を一度に書き込める画素形成部数が増加する。このため、上記第１の実施形態よりも走査期間Ｔ１を短くすることにより十分な休止期間Ｔ２を確保することができるか、または、上記第１の実施形態と同じ長さ走査期間Ｔ１を設けることにより各画素形成部に対する映像信号の書き込み時間を十分に確保することができる。また、サンプリングブロックの数を削減することにより、シフトレジスタ３１０の段数を削減することができる。 <3.3 Effects>
According to the present embodiment, the number of pixel forming portions in which a video signal can be written at a time is increased as compared with the first embodiment. For this reason, it is possible to secure a sufficient rest period T2 by shortening the scanning period T1 compared to the first embodiment, or to provide the scanning period T1 having the same length as that of the first embodiment. As a result, it is possible to secure a sufficient video signal writing time for each pixel formation portion. Further, the number of stages of the shift register 310 can be reduced by reducing the number of sampling blocks.
　＜４．第４の実施形態＞
　＜４．１　ソースドライバの構成＞
　図１６は、本発明の第４の実施形態におけるソースドライバ３００の構成を説明するための回路図である。本実施形態はソースドライバ３００の構成を除く上記第１の実施形態と同様であるので、当該同様の部分についての説明を省略する。図１６に示すように、本実施形態におけるソースドライバ３００は、表示部６００の両側（図１６における上下）にそれぞれ分れて構成されている。以下では、ソースドライバ３００のうち、表示部６００の上側に配置されている部分を「第１ソースドライバ」といい、符号３００ａで表す。また、ソースドライバ３００のうち、表示部６００の下側に配置されている部分を「第２ソースドライバ」といい、符号３００ｂで表す。 <4. Fourth Embodiment>
<4.1 Source driver configuration>
FIG. 16 is a circuit diagram for explaining a configuration of a source driver 300 according to the fourth embodiment of the present invention. Since this embodiment is the same as the first embodiment except for the configuration of the source driver 300, the description of the same portion is omitted. As shown in FIG. 16, the source driver 300 in the present embodiment is divided into both sides (upper and lower sides in FIG. 16) of the display unit 600. Hereinafter, a portion of the source driver 300 that is disposed on the upper side of the display unit 600 is referred to as a “first source driver” and is denoted by reference numeral 300a. In addition, a portion of the source driver 300 that is disposed below the display unit 600 is referred to as a “second source driver” and is denoted by reference numeral 300 b.
　本実施形態におけるシフトレジスタ３１０は、表示部６００の両側にそれぞれ分けて構成されている。以下では、シフトレジスタ３１０のうち、表示部６００の上側に配置されている部分を「第１シフトレジスタ」といい、符号３１０ａで表す。また、シフトレジスタ３１０のうち、表示部６００の下側に配置されている部分を「第２シフトレジスタ」といい、符号３１０ｂで表す。第１シフトレジスタ３１０ａは、上記第１の実施形態におけるシフトレジスタ３１０のうちの奇数段の双安定回路からなる部分に相当する。第２シフトレジスタ３１０ｂは、上記第１の実施形態におけるシフトレジスタのうちの偶数段の双安定回路からなる部分に相当する。 The shift register 310 in the present embodiment is configured separately on both sides of the display unit 600. Hereinafter, a portion of the shift register 310 that is disposed on the upper side of the display unit 600 is referred to as a “first shift register” and is denoted by reference numeral 310a. In addition, a portion of the shift register 310 disposed below the display unit 600 is referred to as a “second shift register” and is denoted by reference numeral 310 b. The first shift register 310a corresponds to a portion composed of an odd-stage bistable circuit in the shift register 310 in the first embodiment. The second shift register 310b corresponds to a portion made up of an even number of bistable circuits in the shift register in the first embodiment.
　本実施形態におけるサンプリング回路３２０は、表示部６００の両側にそれぞれ分けて構成されている。以下では、サンプリング回路３２０のうち、表示部６００の上側に配置されている部分を「第１サンプリング回路」といい、符号３２０ａで表す。また、サンプリング回路３２０のうち、表示部６００の下側に配置されている部分を「第２サンプリング回路」といい、符号３２０ｂで表す。第１サンプリング回路３２０ａは、上記第１の実施形態におけるサンプリング回路３２０のうちの、ゲートドライバ４００が配置されている側から数えて奇数番目のサンプリングブロックからなる部分に相当する。第２サンプリング回路３２０ｂは、上記第１の実施形態におけるサンプリング回路３２０のうちの、ゲートドライバ４００が配置されている側から数えて偶数番目のサンプリングブロックからなる部分に相当する。 The sampling circuit 320 in the present embodiment is configured separately on both sides of the display unit 600. Hereinafter, a portion of the sampling circuit 320 that is disposed on the upper side of the display unit 600 is referred to as a “first sampling circuit” and is denoted by reference numeral 320a. In addition, a portion of the sampling circuit 320 disposed below the display unit 600 is referred to as a “second sampling circuit” and is denoted by reference numeral 320b. The first sampling circuit 320a corresponds to a portion of the sampling circuit 320 in the first embodiment, which is composed of odd-numbered sampling blocks counted from the side where the gate driver 400 is disposed. The second sampling circuit 320b corresponds to a part of the sampling circuit 320 in the first embodiment, which is composed of even-numbered sampling blocks counted from the side where the gate driver 400 is arranged.
　第１ソースドライバ３００ａは、第１シフトレジスタ３１０ａおよび第１サンプリング回路３２０ａにより構成されている。第２ソースドライバ３００ｂは、第２シフトレジスタ３１０ｂおよび第２サンプリング回路３２０ｂにより構成されている。 The first source driver 300a includes a first shift register 310a and a first sampling circuit 320a. The second source driver 300b includes a second shift register 310b and a second sampling circuit 320b.
　＜４．２　効果＞
　本実施形態によれば、表示部の上側および下側にそれぞれ配置された第１ソースドライバ３００ａおよび第２ソースドライバ３００ｂのそれぞれの段数が、上記第１の実施形態におけるソースドライバ３００の段数の約半分になる。このため、ゲートラインの延びる方向におけるレイアウトピッチが倍に広がる。これにより、例えばより高精細な液晶表示パネルに対応可能となる。 <4.2 Effects>
According to the present embodiment, the number of stages of the first source driver 300a and the second source driver 300b respectively disposed on the upper and lower sides of the display unit is approximately the number of stages of the source driver 300 in the first embodiment. Halved. For this reason, the layout pitch in the extending direction of the gate line is doubled. Thereby, for example, it becomes possible to deal with a higher-definition liquid crystal display panel.
　なお、本実施形態の構成に限らず、例えば図１７に示すように、第１サンプリング回路３２０ａと第２サンプリング回路３２０ｂがサンプリングブロック４０（１）～４０（ｋ）を共有した構成としても良い。すなわちこの場合、ゲートドライバ４００が配置されている側から数えて奇数番目のサンプリングブロックは、表示部６００の上側に配置されたＲ用薄膜トランジスタおよびＢ用薄膜トランジスタと、表示部６００の下側に配置されたＧ用薄膜トランジスタとにより構成されている。また、ゲートドライバ４００が配置されている側から数えて偶数番目のサンプリングブロックは、表示部６００の上側に配置されたＧ用薄膜トランジスタと、表示部６００の下側に配置されたＲ用薄膜トランジスタおよびＢ用薄膜トランジスタとにより構成されている。なお、この場合、第１シフトレジスタ３１０ａおよび第２シフトレジスタ３１０ｂに代えて、２つの上記第１の実施形態におけるシフトレジスタ３１０がそれぞれ設けられる。このように、図１７に示す例では、第１ソースドライバ３００ａはシフトレジスタ３１０および第１サンプリング回路３２０ａにより構成され、第２ソースドライバ３００ａはシフトレジスタ３１０および第２サンプリング回路３２０ｂにより構成される。 Note that the present invention is not limited to the configuration of the present embodiment, and for example, as shown in FIG. 17, the first sampling circuit 320a and the second sampling circuit 320b may share the sampling blocks 40 (1) to 40 (k). That is, in this case, the odd-numbered sampling blocks counted from the side on which the gate driver 400 is arranged are arranged on the lower side of the display unit 600 and the R thin film transistor and the B thin film transistor. And a thin film transistor for G. Further, the even-numbered sampling blocks counted from the side where the gate driver 400 is disposed include the G thin film transistor disposed on the upper side of the display unit 600, the R thin film transistor disposed on the lower side of the display unit 600, and B Thin film transistor. In this case, two shift registers 310 in the first embodiment are provided instead of the first shift register 310a and the second shift register 310b. As described above, in the example illustrated in FIG. 17, the first source driver 300a includes the shift register 310 and the first sampling circuit 320a, and the second source driver 300a includes the shift register 310 and the second sampling circuit 320b.
　この例によれば、表示部の上側および下側のそれぞれに配置されたシフトレジスタ３１０の段数は、上記第１の実施形態におけるシフトレジスタ３１０の段数と同じであるものの、表示部の上側および下側にそれぞれ配置された第１サンプリング回路３２０ａおよび第２サンプリング回路３２０ｂのそれぞれの段数が、上記第１の実施形態におけるサンプリング回路３２０の段数の約半分になる。このため、上記第４の実施形態と同様に、ゲートラインの延びる方向におけるレイアウトピッチを倍に広げることができる。 According to this example, the number of stages of the shift register 310 arranged on each of the upper side and the lower side of the display unit is the same as the number of stages of the shift register 310 in the first embodiment, but the upper side and the lower side of the display unit. The number of stages of each of the first sampling circuit 320a and the second sampling circuit 320b arranged on the side is about half of the number of stages of the sampling circuit 320 in the first embodiment. For this reason, as in the fourth embodiment, the layout pitch in the direction in which the gate lines extend can be doubled.
　＜５．その他＞
　上記各実施形態では、ソースクロック信号ＳＣＫの周波数および振幅の制御は表示制御回路２００において行われることが望ましいが、ソースドライバ３００においてこのような制御が行われる構成としても良い。 <5. Other>
In each of the above embodiments, it is desirable that the control and control of the frequency and amplitude of the source clock signal SCK be performed by the display control circuit 200, but such a control may be performed by the source driver 300.
　上記各実施形態では、ＲＧＢの３原色によるカラー画像表示が行われる例を挙げて説明したが、本発明はこれに限定されるものではない。例えばＲＧＢＹ等の４原色、または５原色以上によりカラー画像表示が行われても良い。またモノクロ画像表示が行われて良い。 In each of the above embodiments, an example in which color image display using the three primary colors RGB is described has been described, but the present invention is not limited to this. For example, color image display may be performed using four primary colors such as RGBY, or five or more primary colors. Monochrome image display may be performed.
　上記第３の実施形態では、各ソースライン組が２４本のソースラインにより構成されているが本発明はこれに限定されるものではない。例えば、各ソースライン組が原色数の倍数のソースラインにより構成されていれば良い。 In the third embodiment, each set of source lines is composed of 24 source lines, but the present invention is not limited to this. For example, each source line group may be configured by source lines that are multiples of the number of primary colors.
　上記各実施形態では、薄膜トランジスタはすべてｎチャネル型であるものとして説明したが、本発明はこれに限定されるものではない。薄膜トランジスタがｐチャネル型であっても本発明を適用することができる。 In the above embodiments, the thin film transistors are all assumed to be n-channel type, but the present invention is not limited to this. The present invention can be applied even if the thin film transistor is a p-channel type.
　上記各実施形態では液晶表示装置を例に挙げて説明したが、本発明はこれに限定されない。有機ＥＬ（Ｅｌｅｃｔｒｏ　Ｌｕｍｉｎｅｓｃｅｎｃｅ）表示装置等の他の表示装置にも本発明を適用することができる。また、その他、本発明の趣旨を逸脱しない範囲で上記各実施形態を種々変形して実施することができる。 In the above embodiments, the liquid crystal display device has been described as an example, but the present invention is not limited to this. The present invention can also be applied to other display devices such as organic EL (Electro Luminescence) display devices. In addition, the above-described embodiments can be variously modified and implemented without departing from the spirit of the present invention.
　以上により、消費電力を低減した、表示部と映像信号線駆動回路とが一体的に形成された表示装置および当該表示装置内の映像信号線駆動回路の制御方法を提供する。 As described above, a display device in which a display unit and a video signal line driving circuit are integrally formed with reduced power consumption and a method for controlling the video signal line driving circuit in the display device are provided.
　本発明は、表示部と映像信号線駆動回路とが一体的に形成された表示装置に適用することができる。 The present invention can be applied to a display device in which a display unit and a video signal line driving circuit are integrally formed.
４０（ｊ）…サンプリングブロック
４１ｘ（ｊ）…薄膜トランジスタ（ｘ＝ｒ、ｇ、ｂ）
４１ｘ１（ｊ）～４１ｘ８（ｊ）…薄膜トランジスタ（ｘ＝ｒ、ｇ、ｂ）
２００…表示制御回路
３００…ソースドライバ（映像信号線駆動回路）
３１０…シフトレジスタ
３２０…サンプリング回路
４００…ゲートドライバ（走査信号線駆動回路）
６００…表示部
７００…液晶表示パネル
ＳＣＫ１、ＳＣＫ２…ソースクロック信号
Ｖｉｄｘ…映像信号（ｘ＝ｒ、ｇ、ｂ）
Ｖｉｄｘ１～Ｖｉｄｘ８…映像信号（ｘ＝ｒ、ｇ、ｂ）
ＳＬｘｊ…ソースライン（映像信号線）（ｘ＝ｒ、ｇ、ｂ）
ＳＬｘｊ＿１～ＳＬｘｊ＿８…ソースライン（映像信号線）（ｘ＝ｒ、ｇ、ｂ）
ＳＧｊ…ソースライン組（映像信号線組）
ｘｉｊ…画素形成部（ｘ＝ｒ、ｇ、ｂ）
ｘｉｊ＿１～ｘｉｊ＿８…画素形成部（ｘ＝ｒ、ｇ、ｂ）
Ｔ１…走査期間
Ｔ２…休止期間
ｔｃｋ１…走査期間周期
ｔｃｋ２…休止期間周期
ｆｃｋ１…走査期間周波数
ｆｃｋ２…休止期間周波数
Ｖｃｋ１…走査期間振幅
Ｖｃｋ２…休止期間振幅
Ｖｓｓ…ローレベルの直流電源電位
Ｖｄｄ…ハイレベルの直流電源電位 40 (j) ... Sampling block 41x (j) ... Thin film transistor (x = r, g, b)
41 × 1 (j) to 41 × 8 (j)... Thin film transistor (x = r, g, b)
200: Display control circuit 300: Source driver (video signal line driving circuit)
310: shift register 320 ... sampling circuit 400 ... gate driver (scanning signal line driving circuit)
600: Display 700 ... Liquid crystal display panels SCK1, SCK2 ... Source clock signal Vidx ... Video signal (x = r, g, b)
Vidx1 to Vidx8 ... Video signal (x = r, g, b)
SLxj: Source line (video signal line) (x = r, g, b)
SLxj_1 to SLxj_8... Source line (video signal line) (x = r, g, b)
SGj ... Source line group (Video signal line group)
xij: Pixel forming portion (x = r, g, b)
xij_1 to xij_8: Pixel formation portion (x = r, g, b)
T1 ... Scanning period T2 ... Pause period tck1 ... Scanning period cycle tck2 ... Pause period cycle fck1 ... Scanning period frequency fck2 ... Pause period frequency Vck1 ... Scanning period amplitude Vck2 ... Pause period amplitude Vss ... Low level DC power supply potential Vdd ... High level DC power supply potential

Claims (13)

  1. 　複数の映像信号線、該複数の映像信号線と交差する複数の走査信号線を含み、画像を表示するための表示部と、
    　前記表示部と一体的に形成され、前記複数の映像信号線を駆動するための映像信号線駆動回路と、
    　前記映像信号線駆動回路に、オンレベルとオフレベルとを周期的に繰り返すクロック信号、および前記表示部に表示すべき画像に対応する１以上の所定数の映像信号を与える表示制御回路と、
    　前記複数の走査信号線が順次選択される走査期間と該複数の走査信号線のいずれもが非選択状態となる休止期間とが、該走査期間と該休止期間とからなるフレーム期間を周期として交互に現れるように、前記複数の走査信号線を駆動するための走査信号線駆動回路とを備え、
    　前記映像信号線駆動回路は、
    　　前記クロック信号に基づいて複数の出力信号を順次にオンレベルにするシフトレジスタと、
    　　前記複数の出力信号がそれぞれ与えられる複数のサンプリングブロックとを含み、
    　各サンプリングブロックが、該サンプリングブロックの受け取る前記出力信号に基づいて、前記所定数の映像信号を該所定数の映像信号線に与え、
    　前記走査期間における前記クロック信号の周波数よりも、前記休止期間における該クロック信号の周波数が低いことを特徴とする、表示装置。     A plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and a display unit for displaying an image;
    A video signal line driving circuit formed integrally with the display unit for driving the plurality of video signal lines;
    A display control circuit for providing the video signal line driving circuit with a clock signal that periodically repeats an on level and an off level, and one or more predetermined number of video signals corresponding to an image to be displayed on the display unit;
    A scanning period in which the plurality of scanning signal lines are sequentially selected and a pause period in which all of the plurality of scanning signal lines are in a non-selected state alternate with a frame period that includes the scanning period and the pause period as a cycle. And a scanning signal line driving circuit for driving the plurality of scanning signal lines,
    The video signal line driving circuit includes:
    A shift register that sequentially turns on a plurality of output signals based on the clock signal;
    A plurality of sampling blocks each provided with the plurality of output signals,
    Each sampling block applies the predetermined number of video signals to the predetermined number of video signal lines based on the output signal received by the sampling block,
    The display device, wherein the frequency of the clock signal in the idle period is lower than the frequency of the clock signal in the scanning period.
  2. 　前記休止期間における前記クロック信号の振幅が、前記走査期間における該クロック信号の振幅よりも小さいことを特徴とする、請求項１に記載の表示装置。 The display device according to claim 1, wherein an amplitude of the clock signal in the pause period is smaller than an amplitude of the clock signal in the scanning period.
  3. 　前記休止期間が前記走査期間よりも長いことを特徴とする、請求項１に記載の表示装置。 2. The display device according to claim 1, wherein the pause period is longer than the scanning period.
  4. 　各サンプリングブロックは、該サンプリングブロックの受け取る前記出力信号が制御端子に与えられ、前記所定数の映像信号のうちのいずれかが第１導通端子に与えられ、前記複数の映像信号線のうちのいずれかに第２導通端子が接続された１以上のスイッチング素子を有することを特徴とする、請求項１に記載の表示装置。 In each sampling block, the output signal received by the sampling block is supplied to a control terminal, one of the predetermined number of video signals is supplied to a first conduction terminal, and one of the plurality of video signal lines The display device according to claim 1, further comprising one or more switching elements connected to the second conduction terminal.
  5. 　各サンプリングブロックは前記スイッチング素子を複数有することを特徴とする、請求項４に記載の表示装置。 The display device according to claim 4, wherein each sampling block includes a plurality of the switching elements.
  6. 　前記表示部が複数の原色に基づくカラー画像を表示し、
    　前記所定数の映像信号が前記複数の原色にそれぞれ対応し、
    　各サンプリングブロックにおける前記複数のスイッチング素子の数が前記複数の原色と同数であり、
    　前記表示制御回路が、各サンプリングブロックにおける前記複数のスイッチング素子の前記第１導通端子に互いに異なる前記所定数の映像信号をそれぞれ与えることを特徴とする、請求項５に記載の表示装置。     The display unit displays a color image based on a plurality of primary colors;
    The predetermined number of video signals respectively corresponding to the plurality of primary colors;
    The number of the plurality of switching elements in each sampling block is the same number as the plurality of primary colors,
    The display device according to claim 5, wherein the display control circuit supplies the predetermined number of video signals different from each other to the first conduction terminals of the plurality of switching elements in each sampling block.
  7. 　前記表示部が複数の原色に基づくカラー画像を表示し、
    　各サンプリングブロックにおける前記複数のスイッチング素子の数が前記複数の原色の整数倍であり、
    　前記表示制御回路が、各サンプリングブロックにおける前記複数のスイッチング素子のうちの、互いに隣接する映像信号線に前記第２導通端子が接続されたスイッチング素子の前記第１導通端子に、前記所定数の映像信号のうちの互いに異なる原色に対応する映像信号をそれぞれ与えることを特徴とする、請求項５に記載の表示装置。     The display unit displays a color image based on a plurality of primary colors;
    The number of the plurality of switching elements in each sampling block is an integer multiple of the plurality of primary colors;
    The display control circuit includes the predetermined number of images on the first conduction terminals of the switching elements in which the second conduction terminals are connected to the video signal lines adjacent to each other among the plurality of switching elements in each sampling block. 6. The display device according to claim 5, wherein video signals corresponding to different primary colors among the signals are respectively provided.
  8. 　前記映像信号線駆動回路は、
    　　前記表示部に対して一方に位置する第１映像信号線駆動回路と、
    　　前記表示部に対して他方に位置する第２映像信号線駆動回路とにより構成されることを特徴とする、請求項１に記載の表示装置。     The video signal line driving circuit includes:
    A first video signal line driving circuit located on one side with respect to the display unit;
    The display device according to claim 1, further comprising a second video signal line driving circuit positioned on the other side of the display unit.
  9. 　前記映像信号線駆動回路が、酸化物半導体により半導体層が形成された薄膜トランジスタを用いて実現されていることを特徴とする、請求項１から８までのいずれか１項に記載の表示装置。 The display device according to any one of claims 1 to 8, wherein the video signal line driving circuit is realized using a thin film transistor in which a semiconductor layer is formed of an oxide semiconductor.
  10. 　前記映像信号線駆動回路が、アモルファスシリコンにより半導体層が形成された薄膜トランジスタを用いて実現されていることを特徴とする、請求項１から８までのいずれか１項に記載の表示装置。 9. The display device according to claim 1, wherein the video signal line driving circuit is realized by using a thin film transistor in which a semiconductor layer is formed of amorphous silicon.
  11. 　複数の映像信号線、該複数の映像信号線と交差する複数の走査信号線を含み、画像を表示するための表示部と、オンレベルとオフレベルとを周期的に繰り返すクロック信号および該表示部に表示すべき画像に対応する１以上の所定数の映像信号を出力する表示制御回路と、該表示部と一体的に形成され、該クロック信号に基づいて複数の出力信号を順次にオンレベルにするシフトレジスタおよび該複数の出力信号がそれぞれ与えられる複数のサンプリングブロックとを含む映像信号線駆動回路と、前記複数の走査信号線を駆動するための走査信号線駆動回路とを備える表示装置の駆動方法であって、
    　前記複数の走査信号線が順次選択される走査期間と該複数の走査信号線のいずれもが非選択状態となる休止期間とが、該走査期間と該休止期間とからなるフレーム期間を周期として交互に現れるように前記複数の走査信号線を駆動するステップと、
    　各サンプリングブロックの受け取る前記出力信号に基づいて、前記所定数の映像信号を該所定数の映像信号線に与えるステップと、
    　前記走査期間における前記クロック信号の周波数よりも、前記休止期間における該クロック信号の周波数を低くするステップとを備えることを特徴とする、駆動方法。     A display unit that displays a plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, a clock signal that periodically repeats an on level and an off level, and the display unit A display control circuit that outputs one or more predetermined number of video signals corresponding to an image to be displayed on the display, and the display unit are formed integrally, and a plurality of output signals are sequentially turned on level based on the clock signal. Driving a display device comprising a video signal line driving circuit including a shift register to be operated and a plurality of sampling blocks to which the plurality of output signals are respectively provided, and a scanning signal line driving circuit for driving the plurality of scanning signal lines A method,
    A scanning period in which the plurality of scanning signal lines are sequentially selected and a pause period in which all of the plurality of scanning signal lines are in a non-selected state alternate with a frame period that includes the scanning period and the pause period as a cycle. Driving the plurality of scanning signal lines to appear in
    Applying the predetermined number of video signals to the predetermined number of video signal lines based on the output signal received by each sampling block;
    And a step of lowering the frequency of the clock signal in the idle period than the frequency of the clock signal in the scanning period.
  12. 　前記休止期間における前記クロック信号の振幅が、前記走査期間における該クロック信号の振幅よりも小さいことを特徴とする、請求項１１に記載の駆動方法。 12. The driving method according to claim 11, wherein an amplitude of the clock signal in the pause period is smaller than an amplitude of the clock signal in the scanning period.
  13. 　前記休止期間が前記走査期間よりも長いことを特徴とする、請求項１１に記載の駆動方法。 The driving method according to claim 11, wherein the pause period is longer than the scanning period.
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JPWO2013018595A1 (en) 2015-03-05
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