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WO2013097580A1 - Chip on chip package and manufacturing method - Google Patents

Chip on chip package and manufacturing method Download PDF

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Publication number
WO2013097580A1
WO2013097580A1 PCT/CN2012/085782 CN2012085782W WO2013097580A1 WO 2013097580 A1 WO2013097580 A1 WO 2013097580A1 CN 2012085782 W CN2012085782 W CN 2012085782W WO 2013097580 A1 WO2013097580 A1 WO 2013097580A1
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WO
WIPO (PCT)
Prior art keywords
chip
material layer
lead frame
metal
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2012/085782
Other languages
French (fr)
Chinese (zh)
Inventor
秦飞
夏国峰
安彤
刘程艳
武伟
朱文辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing University of Technology
Original Assignee
Beijing University of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing University of Technology filed Critical Beijing University of Technology
Publication of WO2013097580A1 publication Critical patent/WO2013097580A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
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    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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Definitions

  • the present invention relates to the field of semiconductor component manufacturing technology, and more particularly to a chip on chip (CC) package having a multi-turn pin arrangement, and the present invention also includes a method of fabricating the package.
  • CC chip on chip
  • FIG. 1A and FIG. 1B are respectively a schematic rear view and a cross-sectional view of a conventional QFN package structure including a lead frame 11, a molding material 12, a bonding material 13, a C chip 14, a metal wire 15, wherein the lead frame 11 includes a chip carrier 111 and pins 112 arranged around the periphery of the chip carrier 111.
  • the IC chip i4 is fixed on the chip carrier 111 by the adhesive material 13, and the IC chip 13 is electrically connected to the surrounding pins 112 through the metal wires 15.
  • the molding material 12 encapsulates the IC chip 14, the metal wire 15 and the lead frame 11 for protection and support.
  • the pin U2 is exposed on the bottom surface of the molding material i2, and is soldered to a circuit board such as a PCB to realize the external environment. Electrical connection.
  • the bare chip carrier 111 on the bottom surface is soldered to a circuit board such as a PCB, and has a direct heat dissipation channel, which can effectively release the heat generated by the C chip.
  • the QFN package does not have gull-wing leads, short conductive paths, low self-inductance coefficient and low impedance, and provides good electrical performance to meet high-speed or chopping ffi.
  • the exposed chip carrier provides excellent thermal performance.
  • the traditional two-dimensional planar package As IC integration increases and functions continue to increase, the number of IC I/Os increases, and the number of I/O pins in the corresponding electronic package increases accordingly, and is gradually reduced by the traditional two-dimensional planar package.
  • the highly integrated dimensional three-dimensional package form is developed.
  • the traditional four-sided flat leadless package is a typical two-dimensional planar package.
  • the single-turn pins are arranged around the chip carrier, which limits the increase of the number of I/Os. There is no need for high-density ICs with more I/O counts.
  • the traditional lead frame has a stepless structure design, which cannot effectively lock the plastic material, resulting in low bonding strength between the lead frame and the molding material, and is easy to cause delamination of the lead frame and the molding material or even pins or cores;
  • the moisture cannot be effectively prevented from diffusing into the interior of the electronic package along the bonding interface of the lead frame and the molding material, thereby seriously affecting the reliability of the package.
  • the plastic sealing process needs to be pre-applied to the back of the lead frame to prevent the phenomenon of flashing. After the plastic sealing, the cleaning process such as removing the tape and the plastic material flashing edge is required, which increases the packaging cost.
  • the cutting blade will cut the lead frame metal while cutting the molding material, which will not only reduce the cutting efficiency and shorten the life of the cutting blade, but also produce metal burrs. , affecting the reliability of the package. Therefore, in order to break through the low threshold of traditional QFN: the bottleneck of I/O quantity, improve the reliability of package and reduce the cost of packaging, it is urgent to develop a high reliability, low cost, high I/O density dimension package based on QFN package. Structure and its manufacturing method.
  • the invention provides a high-density, multi-turn pin-arranged chip on chip (CC) package and a manufacturing method thereof, so as to overcome the bottleneck of the low I/O number of the conventional QFN and improve the reliability of the package. Sexual purpose.
  • CC chip on chip
  • the present invention adopts a technical solution
  • the invention provides an on-chip core; a package structure comprising a lead frame, a first metal material layer, a second metal material layer, a mother: a C chip, a sub-IC chip, an insulating filler material, a pasting material, a spacer, a metal Wire and molding materials.
  • the lead frame has a stepped structure in the thickness direction, and has an upper surface, a T surface, and a step surface.
  • the lead frame includes a chip carrier and a plurality of arches arranged in a plurality of turns around the chip carrier.
  • the chip carrier is disposed at a central portion of the lead frame, and the four edge portions of the chip carrier have a stepped structure in the thickness direction.
  • the pins arranged in a plurality of turns around the chip carrier have a circular or rectangular cross-sectional shape, wherein each of the pins includes an inner pin disposed on the upper surface and an outer pin disposed on the lower surface.
  • the first metal material layer and the second metal material layer are respectively disposed at an upper surface position and a lower surface position of the lead frame.
  • the insulating filler material is disposed under the stepped structure of the lead frame to support and protect the bow frame.
  • the mother IC chip is disposed on the first metal material layer of the upper surface of the lead frame by the bonding material, and is fixed to the central portion of the chip carrier.
  • Sub-C The C chip is placed on the edge of the C chip by the bonding material, or the spacer is disposed on the edge of the mother K: chip, and the sub IC chip is placed on the spacer.
  • a plurality of bonding pads on the mother IC chip and the sub IC chip are respectively connected to the inner pins of the plurality of pins provided with the first metal material layer through the metal wires to achieve electrical interconnection.
  • the sheet, the lead frame and the first metal substrate layer form a package.
  • the leadframe has a plurality of pins arranged in a circle around the chip carrier.
  • a lead frame including a chip carrier and pins arranged in three turns around the chip carrier has a stepped structure.
  • the cross-sectional shape of the pins arranged in a circle around the chip carrier has a circular shape.
  • the cross-sectional shape of the pins arranged in three turns around the chip carrier has a rectangular shape.
  • the pin arrangement of each side of the chip carrier is arranged in parallel.
  • the pin arrangement on each side of the chip carrier is staggered.
  • the upper surface and the lower surface of the lead frame are respectively provided with a first metal material layer and a second metal material layer.
  • the first metal material layer and the second metal material layer respectively disposed on the upper surface and the T surface of the lead frame include nickel (Ni), palladium (Pd), gold (An) metal.
  • an insulating filler material is disposed under the lead frame stepped structure.
  • the type of insulating filler material disposed under the stepped structure of the lead frame is a thermosetting plastic sealing material, or a material such as a plug resin, an ink, and a solder resist green oil.
  • a bonding material such as an epoxy resin or a tape containing silver particles is disposed on the core of the core IC package;
  • the sub-rc chip is disposed on the edge of the mother ic chip by the bonding material.
  • a spacer is disposed on the edge surface of the mother IC chip, and the sub IC chip is disposed on the spacer.
  • the material of the spacer is a silicon (Si) material to match the mother IC chip and the sub IC chip.
  • the invention provides a chip core; a method for piercing a package, comprising the following steps: Step 1: Configure the mask material layer
  • the thin plate substrate is cleaned and pretreated, and a mask material layer pattern having a window is disposed on the upper and lower surfaces of the thin plate substrate.
  • Step 2 Configure the metal material layer
  • the first metal material layer and the second metal material layer are disposed in the windows of the mask material layer on the upper surface and the lower surface of the dry thin plate substrate, respectively.
  • Step 3 Selective partial etching of the lower surface
  • the mask material layer on the lower surface of the thin plate substrate is removed, and the second metal material layer is used as a resist layer, and the lower surface of the thin plate substrate is selectively partially etched to form a groove.
  • Step 4 Configure the insulation filler
  • a portion of the recess formed by selective half etching under the sheet substrate is filled with an insulating material.
  • Step 5 Selective partial engraving on the upper surface
  • Step 6 Configure the parent IC chip
  • the mother IC chip is placed in the center of the chip carrier by an epoxy resin such as silver-containing particles or a bonding material such as a tape.
  • Step 7 Configure the sub IC chip
  • the sub IC chip is placed on the edge of the mother IC chip by an adhesive material such as an epoxy resin or a tape containing silver particles, or a spacer is disposed on the edge surface of the mother IC chip, and the sub iC chip is placed on the spacer.
  • an adhesive material such as an epoxy resin or a tape containing silver particles
  • a spacer is disposed on the edge surface of the mother IC chip, and the sub iC chip is placed on the spacer.
  • Step 8 Metal wire bonding connection
  • a plurality of bonding pads on the mother IC chip and the sub IC chip are respectively connected to the inner chests of the plurality of chests provided with the first metal material layer through the metal wires to realize electrical interconnection.
  • the mother iC chip, the sub IC chip, the metal wire, the bonding material, the lead frame and the first metal material layer are coated by a molding material to form an array of package products, or a mother IC chip, a sub IC chip, a metal wire, a spacer
  • the lead frame and the first layer of metallic material form an array of package products.
  • Step 12 Cutting the separated product
  • the separated products are cut to form a single, individual package.
  • the first metal material layer and the second metal material layer are disposed by electroplating or electroless plating.
  • the second metal substrate layer is used as a resist layer, and the etching liquid for etching only the thin plate substrate is selectively etched selectively on the upper surface and the lower surface of the thin plate substrate.
  • the insulating filler material is disposed in the half-etching groove by screen printing or coating or the like.
  • the separation product is cut by a blade cutting, laser cutting or water jet cutting method, and only the molding material and the insulating filling material are cut, and the lead frame is not cut.
  • the chip-on-chip package structure of the basic conventional QFN package is: a three-dimensional package, and the height can be controlled within a range of 0.7 mm, with high: I/O density and integration, lead frame
  • the stepped structure increases the bonding area with the molding material and the insulating filler material, and has the effect of interlocking with the molding material and the insulating filler material, and can effectively prevent the delamination of the lead frame from the molding material and the insulating filler material, and the chest or chip.
  • the detachment of the carrier effectively prevents moisture from diffusing from the outside to the inside of the package structure, and the outer lead of the small-area size can effectively prevent the occurrence of bridging during surface mounting, and the first metal material disposed on the upper surface of the lead frame and the T surface
  • the layer and the second metal material layer can effectively improve the metal wire bonding quality and the surface mount quality. Since the single package body is only connected by the molding material and the insulating filler material, when the cutting product is cut by using a cutting blade, the cutting product is not cut.
  • Lead frame metal material which improves cutting efficiency and prolongs the life of the cutting blade
  • the production of metal burrs is eliminated, and the process of attaching the adhesive film on the back side of the plastic lead frame in the conventional QFN packaging process, removing the film after the plastic sealing and flashing of the molding material, and the like, thereby reducing the packaging cost.
  • 1A is a schematic rear view of a conventional QFN package structure
  • Figure B is a schematic cross-sectional view along the section in Figure A;
  • 2A is a cross-sectional view of a chip having a circular cross section and a pin arrangement on each side of the chip carrier arranged in parallel according to an embodiment of the present invention
  • 2B is a schematic rear view of a chip-on-chip package structure in which the pin cross-section is rectangular and the pin arrangement on each side of the chip carrier is parallel arranged according to an embodiment of the present invention
  • FIG. 3A is a schematic rear view of a chip-on-chip chip structure in which the cross-section of the lead is circular and the core; t-carriers are arranged in a staggered arrangement on the chip according to an embodiment of the present invention; FIG.
  • FIG. 3B is a schematic rear view of a chip-on-chip chip structure in which the cross-section of the lead is rectangular, and the chest arrangement on each side of the chip carrier is staggered according to an embodiment of the present invention
  • Figure 4 is a cross-sectional view taken along line W of Figures 2A-B and 3A-B, in accordance with an embodiment of the present invention
  • Figure 5 is an illustration of an embodiment of the present invention
  • Figure 2A-B and FIG. 6A to FIG. 6M are schematic cross-sectional views showing a manufacturing process of an on-chip chip package structure according to an embodiment of the present invention, and all cross-sectional views are schematic cross-sectional views taken along the line of FIG.
  • FIG. i - 2A is a rear schematic view of a chip-on-core package structure in which the lead cross-section is circular in shape and the chest arrangement of each side of the chip carrier is parallel arranged in accordance with the present invention.
  • 2B is a cross-sectional view of a chip having a rectangular cross section and a pin arrangement on each side of the chip carrier in a parallel arrangement according to an embodiment of the present invention
  • the lead frame 201 of the on-chip chip package structures 200a and 200b includes a chip carrier 202 and pins 203 arranged in a plurality of circles around the chip carrier 202, and the chip carrier The pins 203 on each side are arranged in parallel, and a second metal frit layer 23 is disposed on the lower surface of the lead frame 201, and an insulating filler 25 is disposed in the lead frame 201.
  • the difference is that the pin cross-section of the on-chip chip package structure of Fig. 2A is circular, and the pin cross section of the on-chip chip package structure of Fig. 2B is rectangular.
  • 3A is a rear schematic view of a chip-on-chip package structure in which the pin cross-section is circular and the pin arrangement on each side of the core is staggered in accordance with an embodiment of the present invention.
  • 3B is a rear schematic view showing the structure of a chip-on-chip package in which the cross-section of the lead is rectangular and the core is arranged in a staggered arrangement on each side of the t-carrier according to an embodiment of the present invention.
  • the lead frame 201 of the on-chip chip package structures 200c and 200d includes a chip carrier 202 and pins 203 arranged in a plurality of circles around the chip carrier 202, and the chip carrier 202
  • the arrangement of the chests 203 on each side is staggered, and a second metal material layer 23 is disposed on the lower surface of the lead frame 201, and an insulating filler 25 is disposed in the lead frame 201.
  • the difference is that the pin cross-section in the chip-on-chip structure of Fig. 3A is circular, and the pin cross-section in the chip package structure of the core of Fig. 3B is rectangular.
  • Figure 4 is a schematic cross-sectional view taken along line I-I of Figures 2A-B and 3A-B.
  • the on-chip chip package structure 200A includes a lead frame 201, a metal substrate layer 22, a second metal material layer 23, and an insulating pad.
  • the material 25 the bonding material 26, the mother IC chip 27, the sub IC core j ⁇ 28, the metal wires 29, and the molding material 30.
  • the lead frame 201 serves as a passage for conducting, dissipating, and connecting an external circuit, having a stepped structure 24b in the thickness direction, having an upper surface 20a and a lower surface 20b with respect to the upper surface 20a, and a stepped structure 24b.
  • the lead frame 201 includes a chip carrier 202 and pins 203 arranged in a plurality of turns around the chip carrier 202, and the chip carriers 202 and I are arranged in a plurality of turns around the chip carrier 202 to have a stepped structure 24b.
  • the core carrier t is disposed at a central portion of the lead frame 201, and the four edge portions of the chip carrier 202 have a stepped structure 24b in the thickness direction.
  • the plurality of pins 203 are disposed around the chip carrier 202, and the coils are arranged in a plurality of turns around the chip carrier 202.
  • the crucible has a stepped structure 24b in the thickness direction, and the cross-sectional shape thereof is circular or rectangular, wherein each of the pins 203 includes a configuration.
  • the inner lead of the upper surface 20a and the outer bow disposed on the lower surface 20b.
  • the first metal material layer 22 and the second metal material layer 23 are respectively disposed on the upper surface 2 of the lead frame 201 (position and the lower surface 20b of the lead frame 201, and the first metal material layer 22 and the inner lead of the pin 203 have The same size, the second metal material layer 23 has the same size as the outer lead of the lead 203.
  • the first metal material layer 22 has a first metal material layer surface 22a, and the second metal material layer 23 has a second metal material layer. Surface 23a.
  • the insulating filling material 25 is disposed under the stepped structure 24 of the lead frame 20, and supports and protects the lead frame 201.
  • the insulating filling material 25 has an insulating filling material surface 25a, and the insulating filling material surface 25a and the second The metal material layer surface 23a is on the same level.
  • the mother IC chip 27 is placed on the bow by the bonding material 26!
  • the first metal material layer 22 of the upper surface 20a of the wire frame 201 is disposed at a central portion of the chip carrier 202, and the sub IC chip 28 is disposed on the mother IC core by the bonding material 26.
  • the edge of the sheet 27 has a rim.
  • the plurality of bonding pads on the mother chip 27 and the sub-C chip 28 are respectively connected to the inner pins of the plurality of pins on which the first metal material layer 22 is disposed by the metal wires 29 to electrically interconnect.
  • the molding material 30 covers the mother IC chip 27, the sub IC chip 28, the bonding material 26, the metal wires 29, the bow wire frame 201, and the first metal material layer 22, exposing the second metal disposed on the lower surface 20b of the lead frame. Material layer 23.
  • Figure 5 is a cross-sectional view taken along the line I-: ⁇ in Figures 2A-B and 3A-B.
  • the on-chip chip package structure 200B includes a lead frame 20i, a first metal material layer 22, a second metal material layer 23, an insulating filling material 25, The bonding material 26, the mother IC chip 27, the sub IC chip 28, the metal wires 29, the molding material 30, and the spacers 31.
  • the lead frame 20 has a stepped structure 24b in the thickness direction as a passage for conducting, dissipating, and connecting an external circuit, having an upper surface 20a and a T surface 20b with respect to the upper surface 20a, and a stepped structure 24b.
  • the lead frame 201 includes a chip carrier 202 and pins 203 arranged in a plurality of turns around the chip carrier 202.
  • the chip carrier 202 and the pins 203 arranged in a plurality of turns around the chip carrier 202 have stepped hooks 24b.
  • the chip carrier 202 is disposed at a central portion of the lead frame 201, and has a rectangular cross section.
  • the four edge portions of the chip carrier 202 have a stepped structure 24b in the thickness direction.
  • the plurality of pins 203 are disposed around the chip carrier 202, arranged in a plurality of circles around the chip carrier 202, and have a stepped structure 24b in a thickness direction, the cross-sectional shape of which is circular or rectangular, wherein each of the pins 203 includes The inner lead of the upper surface 20a and the outer lead of the lower surface 20b.
  • the first metal material layer 22 and the second metal material layer 23 are respectively disposed at positions of the upper surface 20a of the lead frame 201 and the lower surface 20b of the lead frame 201, and the first metal material layer 22 has the same inner pin as the lead 203. Dimensions, the second metal material layer 23 has the same size as the outer leads of the leads 203.
  • the metal metal layer 22 has a first metal material layer surface 22a, and the second metal material layer 23 has a second metal material layer surface 23a.
  • the insulating filling material 25 is disposed under the stepped structure 24 of the lead frame 201 to support and protect the lead frame 201.
  • the insulating filling material 25 has an insulating filling material surface 25a, an insulating filling material surface 25a and a second metal material layer.
  • the surface 23a is on the same level.
  • the mother IC core j ⁇ 27 is disposed on the first metal material layer 22 of the upper surface 20a of the lead frame 201 by the bonding material 26, and is disposed at the central portion of the chip carrier 202, and the spacer 31 is disposed on the rim surface of the mother IC chip 27.
  • the sub IC chip 28 is disposed on the spacer 3, and the presence of the spacer 31 maintains a pitch of a certain height between the C chip 27 and the sub:C chip 28.
  • the plurality of bonding pads on the mother chip 27 and the sub-C chip 28 are respectively connected to the inner chests of the plurality of chests on which the first metal material layer 22 is disposed by the metal wires 29 to electrically interconnect.
  • the molding material 30 covers the mother IC chip 27, the sub IC chip 28, the metal wires 29, the spacers 31, the lead frame 201, and the first metal material layer 22, exposing the second metal material layer disposed on the lower surface 20b of the lead frame. twenty three.
  • FIGS. 6A through 6M are schematic cross-sectional views showing a manufacturing process of a chip-on-chip (CoC) package structure, which is a cross-sectional view taken along the line of Fig. 4, in accordance with an embodiment of the present invention.
  • a thin plate substrate 20 having an upper surface 20a and a lower surface 20b opposite to the upper surface 20a is provided.
  • the material of the thin plate substrate 20 may be copper, copper alloy, iron, iron alloy, nickel, nickel alloy, and the like. ] 3 ⁇ 4 in the metal material of the lead frame.
  • the thickness of the sheet substrate 20 ranges from 0. mm to 0.25 ram, for example, 0.127 mm, 0, i52 ram, 0. 203 ⁇ ⁇ .
  • the upper surface 20a and the lower surface 20b of the thin plate substrate 20 are cleaned and pretreated, for example, by using plasma water to remove oil, dust, or the like, for the purpose of cleaning the upper surface 20a and the lower surface 20b of the thin plate substrate 20. Referring to FIG.
  • a mask material layer 21a and a mask material layer 2ib having windows are respectively disposed on the upper surface 2 (3 ⁇ 4 and the lower surface 20b of the thin plate base 20), and the window described herein means that there is no mask material.
  • the thin plate substrate 20 covered by the layer 2ia and the mask material layer 21b, the mask material layer 21a and the mask material layer 21b protect the thin plate substrate 20 covered by it, and the layer of the mask material will be layered in a later process step: Ha and the thin-plate base material 20 covered by the mask material layer 21b are etched.
  • a first metal material layer 22 is disposed in a window of the mask material layer 21a disposed on the upper surface 20a of the thin plate base 20, and the first metal material layer 22 has a first metal material layer surface 22a.
  • the second metal material layer 23 is disposed in the window of the mask layer 21b disposed on the lower surface 20b of the thin plate substrate 20, and the second metal layer 23 has the second metal material layer surface 23a.
  • the first metal material layer 22 and the second metal material layer 23 are disposed by plating, electroless plating, evaporation, sputtering, etc., and are allowed to be composed of different metal materials. In this embodiment, electroplating or electroless plating is preferred.
  • the method of arranging the first metal material layer 22 and the second metal material layer 23 is smeared.
  • the materials of the first metal material layer 22 and the second metal material layer 23 are nickel (Ni), palladium (Pd), gold ( ⁇ ⁇ 3 ), silver (Ag), tin (Sn and other metal materials and alloys thereof,
  • the first metal material layer 22 and the second metal material layer 23 are, for example, a nickel-palladium-gold plating layer.
  • the outer gold plating layer and the intermediate palladium plating layer ensure that the metal wire 29 is in the lead wire.
  • the bondability and bonding quality on the frame 201, the nickel plating inside is used as a diffusion barrier to prevent the formation of excessively thick eutectic compounds caused by elemental diffusion-chemical reactions, and the excessively thick eutectic compounds affect the bonding regions.
  • the reliability, for the second metal material layer 23, the outer gold plating layer and the intermediate palladium plating layer ensure the wettability of the solder in the lead frame 201, and improve the quality of the surface mounting of the package on a circuit board such as a PCB.
  • the nickel plating layer acts as a diffusion barrier to prevent the formation of an excessively thick eutectic compound caused by elemental diffusion-chemical reactions, and the excessively thick eutectic compound affects the reliability of the surface mount soldered region.
  • the mask material layer 21 b on the lower surface 20b of the thin plate base 20 is removed.
  • the removal method in this embodiment may be a chemical reaction method or a mechanical method, and the chemical reaction method is selected.
  • a soluble alkaline solution such as potassium hydroxide (KDH) or sodium hydroxide (NaOH) is chemically reacted with the mask material layer 21b on the lower surface 20b of the thin plate substrate 20 by spraying or the like to dissolve it.
  • KDH potassium hydroxide
  • NaOH sodium hydroxide
  • the second metal material layer 23 on the lower surface 20b of the thin plate substrate 20 is etched into a resist layer, and the surface 20b of the thin plate substrate 20 T is selectively partially etched by a spray method.
  • the groove 24 and the stepped structure surface 24a are formed, and the etching depth may range from 40% to 90% of the thickness of the thin plate substrate 20.
  • the spraying method preferably adopts the upper spraying method, and the etching liquid preferentially selects an alkaline etching liquid, such as an alkaline copper chloride engraving liquid, an alkaline etching solution such as ammonium chloride, to reduce the etching liquid pair.
  • an alkaline etching liquid such as an alkaline copper chloride engraving liquid
  • an alkaline etching solution such as ammonium chloride
  • the recess 24 formed by selective partial etching on the lower surface 20b of the thin plate substrate 20 is filled with an insulating filler material 25 having a surface 25a which is at the surface 23a of the second metal material layer.
  • the insulating filling material 25 is an insulating material such as a thermosetting plastic sealing material, a plug resin, an ink, and a solder resist green oil, and the insulating filling material 25 has sufficient tannic acid and alkali resistance to ensure the subsequent process is not The ruthenium may be damaged by the formation of the insulating filler material 25.
  • the filling method of the insulating filler material 25 is filled into the groove 24 by injection molding or screen printing, and the mechanical insulation or chemical treatment is used to remove excessive insulation after the configuration. Filling the material 25 to eliminate the flash of the insulating filler 25, so that the surface 25a of the insulating filler 25 and the surface 23a of the second metal material layer are at the same level, and the insulating filler 25 such as the photosensitive solder resist green oil is developed. The method removes the flash. Referring to FIG. 6G, the mask material layer 21a on the upper surface 20a of the thin plate substrate 20 is removed.
  • the removal method in the present embodiment may be a chemical reaction method and a mechanical method, and the chemical reaction method is selected to be soluble.
  • An alkaline solution such as potassium hydroxide (KDH), sodium hydroxide (NaOH), spray, or the like, chemically reacts with the mask material layer 21a on the upper surface 20a of the thin plate substrate 20 to dissolve it to achieve the shift
  • KDH potassium hydroxide
  • NaOH sodium hydroxide
  • spray or the like
  • the first metal material layer 22 on the upper surface 20a of the thin plate substrate 20 is used as an etching resist layer, and the etching liquid of the thin plate substrate 20 is etched only by the ffl spray method.
  • the upper surface 2 (k is selectively partially etched, etched to the stepped structure surface 24a, exposing the insulating filling material 25.
  • the lead frame 201 includes the chip carrier 202 and a plurality of turns arranged around the chip carrier 202
  • the lead frame 201 is provided with an insulating filling material 25, that is, the chip carrier 202 and the pins 203 of the chip carrier 202 having a plurality of turns of the chip carrier 202 are fixed together by the insulating filling material 25.
  • the selective partial etching is performed.
  • the separate pin 203 has an inner lead and an outer lead. The inner lead is connected to the bond pad of the female IC chip 27 by a metal wire 28 in a subsequent wire bonding process, and the outer pin is connected to an external circuit.
  • the stepped structure 24b has a stepped structure 24b, and the stepped structure 24b has a stepped structure surface 24a.
  • the spray method of the etchant is preferably sprayed. It was engraved preferred alkali etching solution, an etching solution such as alkaline copper chloride, ammonium chloride, alkaline etching solution, an etching solution to reduce the damaging effect on the material of the first metal layer 22.
  • the mother:C chip 27 is disposed on the first metal material layer 22 of the upper surface 20a of the lead frame by the bonding material 26, and is fixed to the central portion of the chip carrier 202.
  • the bonding material 26 is attached. It may be a material such as an adhesive tape or an epoxy resin containing silver particles.
  • the sub-C chip 28 is disposed on the rim surface of the mother C chip 27 by the bonding material 26.
  • the bonding material 26 may be an adhesive tape or an epoxy containing silver particles. Materials such as resins.
  • a plurality of bonding pads on the mother IC chip 27 and the sub IC chip 28 are connected to the multi-pin inner pins of the first metal material layer 22 through the metal wires 29 to realize electrical interconnection.
  • the metal wires 29 are gold wires, aluminum wires, copper wires, palladium-plated copper wires, and the like.
  • the mother IC chip 27, the sub IC chip 28, the adhesive material 26, the metal wires 29, the lead frame 201, and the first metal layer 22 are coated by the molding material 30 by an injection molding method to form an array of products.
  • the molding material 30 may be a material such as a thermosetting polymer, and the filled insulating filler material 25 has similar physical properties as the molding material 30, such as a thermal expansion coefficient, to reduce product failure caused by thermal mismatch, and improve The reliability of the product, the insulating filler material 25 and the molding material 30 may be the same material.
  • the molding material 30 and the insulating filling material 25 have a mutual locking function with the lead frame 201 having the stepped structure 24b, and the delamination of the lead frame 201 and the molding material 30 and the insulating filling material 25 can be effectively prevented.
  • the pin 203 or the chip carrier 202 is detached, and effectively prevents moisture from diffusing along the bonding interface of the lead frame 20 and the molding material 30 and the insulating filler 25 into the inside of the package, thereby improving the reliability of the package.
  • the product array is laser printed.
  • the chip package structure product array is cut on the chip, and the plastic package material 30 and the insulating filler material 25 are completely cut and separated to form a single on-chip chip package structure 200.
  • the single product separation method is blade cutting, Laser cutting or water jet cutting, etc., and cutting only the molding material 30 and the insulating filling material 25, without cutting the lead frame metal material, only two chip-on-chip package structures 200 after cutting and separating are drawn in FIG. 6M.
  • the description of the embodiments of the present invention is intended to be illustrative of the invention, and is not intended to limit the scope of the invention. The above embodiment can be changed. The invention is not limited to the specific embodiments disclosed, but is intended to cover modifications within the spirit and scope of the invention as defined by the appended claims.

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Abstract

Provided are a chip on chip package (200A) and a manufacturing method, which are a 3D package structure and a manufacturing method therefor based on quad-flat no-leads package (QFN) with high reliability, low costs and high input/output (I/O) density. The package (200A) includes a lead frame (201), a first metal material layer (22), a second metal material layer (23), a parent integrated circuit (IC) chip (27), a child IC chip (28), a spacer (31), an adhesive material (26), an insulation filler material (25) and a plastic package material (30). The lead frame (201) includes a chip carrier (202) and a plurality of leads (203) surrounding the chip carrier (202) and arranged in multiple rings. The first metal material layer (22) and the second metal material layer (23) are provided on the upper surface (20a) and the lower surface (20b) of the lead frame (201) respectively. The insulation filler material (25) is provided under a step structure (24b) of the lead frame (201). The parent IC chip (27) is provided at the first metal material layer (22) location on the upper surface (20a) of the lead frame (201), and the child IC chip (28) is provided above the parent IC chip (27). The parent IC chip (27) and the child IC chip (28) are connected to the inner leads of the multiple rings of leads (203) via a metal wire (29) respectively. The plastic package material (30) forms a package piece by wrapping the parent IC chip (27) and the child IC chip (28).

Description

种芯片上芯片封装及制造方法  On-chip chip package and manufacturing method

技术领域 Technical field

本发明涉及半导体元器件制造技术领域， 尤其涉及到具有多圈引脚排列的芯片上芯片 (Chip on Chip, CoC) 封装， 本发明还包括该封装件的制造方法。  The present invention relates to the field of semiconductor component manufacturing technology, and more particularly to a chip on chip (CC) package having a multi-turn pin arrangement, and the present invention also includes a method of fabricating the package.

背景技术  Background technique

随着电子产品如手机、 笔记本电脑等朝着小型化， 便携式， 超薄化， 多媒体化以及满 足大众化所需要的低成本方向发展， 高密度、 高性能、 高可靠性和低成本的封装形式及其 组装技术得到了快速的发展。 与价格昂贵的 BGA等封装形式相比， 近年来快速发展的新 型封装技术， 即四边扁平无引胸 QFN (Quad Flat Non · lead Package)封装， 由于具有良好 的热性能和电性能、 尺寸小、 成本低以及高生产率等众多优点， 引发了微电子封装技术领 域的一场新的革命。  As electronic products such as mobile phones and notebook computers are becoming smaller, portable, ultra-thin, multimedia, and low-cost for the masses, high-density, high-performance, high-reliability, and low-cost packages are available. Its assembly technology has been rapidly developed. Compared with expensive BGA and other package types, the new packaging technology developed in recent years, namely Quad Flat Non-lead Package (BF), has good thermal and electrical properties and small size. The low cost and high productivity advantages have led to a new revolution in the field of microelectronic packaging technology.

图 1A和图 IB分别为传统 QFN封装结构的背面示意图和沿 面的剖面示意图，该 QFN封装结构包括引线框架 11 , 塑封材料 12, 粘片材料 13, :C芯片 14， 金属导线 15, 其中引线框架 11包括芯片载体 111和围绕芯片载体 111四周排列的引脚 112， IC芯片 i4 通过粘片材料 13固定在芯片载体 111上， IC芯片 13与四周排列的引脚 112通过金属导线 15实现电气连接， 塑封材料 12对 IC芯片 14、 金属导线 15和引线框架 11进行包封以达 到保护和支撑的作用， 引脚 U2裸露在塑封材料 i2的底面， 通过焊料焊接在 PCB等电路 板上以实现与外界的电气连接。底面裸露的芯片载体 111通过焊料焊接在 PCB等电路板上， 具有直接散热通道， 可以有效释放】C芯片】 4产生的热量。 与传统的 TSOP和 SOIC封装 相比， QFN封装不具有鸥翼状引线， 导电路径短， 自感系数及阻抗低， 丛而可提供良好的 电性能， 可满足高速或者徼波的应 ffi。 裸露的芯片载体提供了卓越的散热性能。  1A and FIG. 1B are respectively a schematic rear view and a cross-sectional view of a conventional QFN package structure including a lead frame 11, a molding material 12, a bonding material 13, a C chip 14, a metal wire 15, wherein the lead frame 11 includes a chip carrier 111 and pins 112 arranged around the periphery of the chip carrier 111. The IC chip i4 is fixed on the chip carrier 111 by the adhesive material 13, and the IC chip 13 is electrically connected to the surrounding pins 112 through the metal wires 15. The molding material 12 encapsulates the IC chip 14, the metal wire 15 and the lead frame 11 for protection and support. The pin U2 is exposed on the bottom surface of the molding material i2, and is soldered to a circuit board such as a PCB to realize the external environment. Electrical connection. The bare chip carrier 111 on the bottom surface is soldered to a circuit board such as a PCB, and has a direct heat dissipation channel, which can effectively release the heat generated by the C chip. Compared with the traditional TSOP and SOIC packages, the QFN package does not have gull-wing leads, short conductive paths, low self-inductance coefficient and low impedance, and provides good electrical performance to meet high-speed or chopping ffi. The exposed chip carrier provides excellent thermal performance.

随着 IC集成度的提高和功能的不断增强， IC的 I/O数随之增加， 相应的电子封装的 I/O引脚数也相应增加， 且逐渐由传统的二维平面封装形式 ^更高集成度的 维立体封装 形式发展， 传统的四边扁平无引脚封装件为典型的二维平面封装形式， 单圈的引脚围绕芯 片载体呈周边排列， 限制了 I/O数量的提高， 满足不了高密度、 具有更多 I/O数的 IC的需 要。 传统的引线框架无台阶式结构设计， 无法有效的锁住塑料材料， 导致引线框架与塑封 材料结合强度低， 易于引起引线框架与塑封材料的分层甚至引脚或芯； t载体的脱落， 而且 无法有效的阻止湿气沿着引线框架与塑封材料结合界面扩散到电子封装内部， 从而严重影 响了封装体的可靠性。 传统 QFN产品在塑封工艺^需要预先在引线框架背面粘贴胶带以 防止溢料现象， 待塑封后还需迸行去除胶带、 塑封料飞边等清洗工艺， 增加了封装成本增 高。 使用切割刀切割分离传统的四边扁平无引脚封装件， 切割刀在切割塑封材料的同时也 会切割到引线框架金属， 不仅会造成切割效率的降低和切割刀片寿命的缩短， 而且会产生 金属毛刺， 影响了封装体的可靠性。 因此， 为了突破传统 QFN的低: I/O数量的瓶颈， 提高 封装体的可靠性和降低封装成本， 急需研发一种基于 QFN封装的高可靠性、 低成本、 高 I/O密度的 维封装结构及其制造方法。  As IC integration increases and functions continue to increase, the number of IC I/Os increases, and the number of I/O pins in the corresponding electronic package increases accordingly, and is gradually reduced by the traditional two-dimensional planar package. The highly integrated dimensional three-dimensional package form is developed. The traditional four-sided flat leadless package is a typical two-dimensional planar package. The single-turn pins are arranged around the chip carrier, which limits the increase of the number of I/Os. There is no need for high-density ICs with more I/O counts. The traditional lead frame has a stepless structure design, which cannot effectively lock the plastic material, resulting in low bonding strength between the lead frame and the molding material, and is easy to cause delamination of the lead frame and the molding material or even pins or cores; The moisture cannot be effectively prevented from diffusing into the interior of the electronic package along the bonding interface of the lead frame and the molding material, thereby seriously affecting the reliability of the package. In the traditional QFN product, the plastic sealing process needs to be pre-applied to the back of the lead frame to prevent the phenomenon of flashing. After the plastic sealing, the cleaning process such as removing the tape and the plastic material flashing edge is required, which increases the packaging cost. Using a dicing knife to cut and separate the traditional four-sided flat leadless package, the cutting blade will cut the lead frame metal while cutting the molding material, which will not only reduce the cutting efficiency and shorten the life of the cutting blade, but also produce metal burrs. , affecting the reliability of the package. Therefore, in order to break through the low threshold of traditional QFN: the bottleneck of I/O quantity, improve the reliability of package and reduce the cost of packaging, it is urgent to develop a high reliability, low cost, high I/O density dimension package based on QFN package. Structure and its manufacturing method.

发明内容 本发明提供了一种高密度、 多圈引脚排列的芯片上芯片 （Chip on Chip, CoC ) 封装及 其制造方法， 以达到突破传统 QFN的低 I/O数量的瓶颈和提高封装体的可靠性的目的。 Summary of the invention The invention provides a high-density, multi-turn pin-arranged chip on chip (CC) package and a manufacturing method thereof, so as to overcome the bottleneck of the low I/O number of the conventional QFN and improve the reliability of the package. Sexual purpose.

为了实现上述目的， 本发明采/ ¾Τ述技术方案；  In order to achieve the above object, the present invention adopts a technical solution;

本发明提出一种芯片上芯； t封装件结构， 包括引线框架、 第一金属材料层、 第二金属 材料层、 母: C芯片、 子 IC芯片、 绝缘填充材料、 粘贴材料、 隔片、 金属导线和塑封材料。 引线框架沿厚度方向具有台阶式结构， 具有上表面、 T表面和台阶表面。 引线框架包括芯 片载体和多个围绕芯片载体呈多圈排列的弓 i脚。 芯片载体配置于引线框架中央部位， 芯片 载体四边边缘部位沿厚度方向具有台阶式结构。 围绕芯片载体呈多圈排列的引脚的横截面 形状呈圆形或者矩形状， 其中每个引脚包括配置于该上表面的内引脚和配置于该下表面的 外引脚。 第一金属材料层和第二金属材料层分别配置于引线框架的上表面位置和下表面位 置。 绝缘填充材料配置于引线框架的台阶式结构下， 支撑、 保护弓 i线框架。 母 IC芯片通 过粘贴材料配置于引线框架上表面的第一金属材料层位置， 且固定于芯片载体的中央部 位。 子：C芯片通过粘贴材料配置于母 :C芯片的有缘面上， 或在母 K:芯片的有缘面上配 置隔片， 将子 IC芯片配置于隔 j†上。 母 IC芯片和子 IC芯片上的多个键合焊盘通过金属 导线分别连接至配置有第一金属材料层的多个引脚的内引脚， 以实现电气互联。塑封材料， 包覆母】 C芯^、 子 IC芯片、 金属导线、 粘贴材料、 引线框架和第一金属材料层， 形成封 装件， 或者包覆母 IC芯片、 子: C芯片、 金属导线、 隔片、 引线框架和第一金属村料层， 形成封装件。 根据本发明的实施倒， 引脚框架具有多个 绕芯片载体呈≡圈排列的引脚。  The invention provides an on-chip core; a package structure comprising a lead frame, a first metal material layer, a second metal material layer, a mother: a C chip, a sub-IC chip, an insulating filler material, a pasting material, a spacer, a metal Wire and molding materials. The lead frame has a stepped structure in the thickness direction, and has an upper surface, a T surface, and a step surface. The lead frame includes a chip carrier and a plurality of arches arranged in a plurality of turns around the chip carrier. The chip carrier is disposed at a central portion of the lead frame, and the four edge portions of the chip carrier have a stepped structure in the thickness direction. The pins arranged in a plurality of turns around the chip carrier have a circular or rectangular cross-sectional shape, wherein each of the pins includes an inner pin disposed on the upper surface and an outer pin disposed on the lower surface. The first metal material layer and the second metal material layer are respectively disposed at an upper surface position and a lower surface position of the lead frame. The insulating filler material is disposed under the stepped structure of the lead frame to support and protect the bow frame. The mother IC chip is disposed on the first metal material layer of the upper surface of the lead frame by the bonding material, and is fixed to the central portion of the chip carrier. Sub-C: The C chip is placed on the edge of the C chip by the bonding material, or the spacer is disposed on the edge of the mother K: chip, and the sub IC chip is placed on the spacer. A plurality of bonding pads on the mother IC chip and the sub IC chip are respectively connected to the inner pins of the plurality of pins provided with the first metal material layer through the metal wires to achieve electrical interconnection. Molding material, coated mother] C core ^, sub IC chip, metal wire, bonding material, lead frame and first metal material layer, forming a package, or covering the mother IC chip, sub: C chip, metal wire, spacer The sheet, the lead frame and the first metal substrate layer form a package. In accordance with an implementation of the present invention, the leadframe has a plurality of pins arranged in a circle around the chip carrier.

根据本发明的实施例， 包括芯片载体和围绕芯片载体呈三圈排列的引脚的引线框架具 有台阶式结构。  According to an embodiment of the present invention, a lead frame including a chip carrier and pins arranged in three turns around the chip carrier has a stepped structure.

根据本发明的实施倒， 围绕芯片载体呈 圈排列的引脚的横截面形状呈圆形形状。 根据本发明的实施例， 围绕芯片载体呈三圈排列的引脚的横截面形状呈矩形形状。 根据本发明的实施例， 芯片载体每边的引脚棑列方式为平行排列。  According to an embodiment of the present invention, the cross-sectional shape of the pins arranged in a circle around the chip carrier has a circular shape. According to an embodiment of the present invention, the cross-sectional shape of the pins arranged in three turns around the chip carrier has a rectangular shape. According to an embodiment of the invention, the pin arrangement of each side of the chip carrier is arranged in parallel.

根据本发明的实施倒， 芯片载体每边的引脚排列方式为交错排列。  According to an implementation of the present invention, the pin arrangement on each side of the chip carrier is staggered.

根据本发明的实施例， 引线框架上表面和下表面分别配置有第一金属材料层和第二金 属材料层。  According to an embodiment of the present invention, the upper surface and the lower surface of the lead frame are respectively provided with a first metal material layer and a second metal material layer.

根据本发明的实施例， 引线框架上表面和 T表面分别配置的第一金属材料层和第二金 属材料层包括镍 (Ni)、 钯 (Pd)、 金 (An)金属 料。  According to an embodiment of the present invention, the first metal material layer and the second metal material layer respectively disposed on the upper surface and the T surface of the lead frame include nickel (Ni), palladium (Pd), gold (An) metal.

根据本发明的实施倒， 引线框架台阶式结构下配置绝缘填充材料。  According to an implementation of the present invention, an insulating filler material is disposed under the lead frame stepped structure.

根据本发明的实施例， 引线框架台阶式结构下配置绝缘填充材料种类是热固性塑封村 料， 或者塞孔树脂、 油墨以及阻焊绿油等材料。  According to an embodiment of the present invention, the type of insulating filler material disposed under the stepped structure of the lead frame is a thermosetting plastic sealing material, or a material such as a plug resin, an ink, and a solder resist green oil.

根据本发明的实施倒， ^含银颗粒的环氧树脂或者胶带等粘贴材料将母 IC芯片配置于 芯; t载体中央部位。  According to the practice of the present invention, a bonding material such as an epoxy resin or a tape containing silver particles is disposed on the core of the core IC package;

根据本发明的实施倒， 子 rc芯片通过粘贴材料配置于母 ic芯片的有缘面上。  According to an embodiment of the present invention, the sub-rc chip is disposed on the edge of the mother ic chip by the bonding material.

根据本发明的实施倒， 在母 IC芯片的有缘面上配置隔片， 将子 IC芯片配置于隔 j†上。 根据本发明的实施例， 隔片的材料为硅 (Si)材料， 以匹配母 IC芯片和子 IC芯片。 本发明提出一种芯片上芯； t封装件的刺造方法， 包括以下步骤： 歩骤 1 : 配置掩膜材料层 According to the implementation of the present invention, a spacer is disposed on the edge surface of the mother IC chip, and the sub IC chip is disposed on the spacer. According to an embodiment of the invention, the material of the spacer is a silicon (Si) material to match the mother IC chip and the sub IC chip. The invention provides a chip core; a method for piercing a package, comprising the following steps: Step 1: Configure the mask material layer

对薄板基材进行清洗和预处理， 在薄板基材的上表面和下表面配置具有窗口的掩膜材 料层图形。  The thin plate substrate is cleaned and pretreated, and a mask material layer pattern having a window is disposed on the upper and lower surfaces of the thin plate substrate.

步骤 2: 配置金属材料层  Step 2: Configure the metal material layer

在配置干薄板基材上表面和下表面的掩膜材料层的窗口中分别配置第一金属材料层和 第二金属材料层。  The first metal material layer and the second metal material layer are disposed in the windows of the mask material layer on the upper surface and the lower surface of the dry thin plate substrate, respectively.

步骤 3: 下表面选择性部分蚀刻  Step 3: Selective partial etching of the lower surface

移除薄板基材下表面的掩膜材料层， 以第二金属材料层为抗蚀层， 对薄板基材下表面 进行选择性部分蚀刻， 形成凹槽。  The mask material layer on the lower surface of the thin plate substrate is removed, and the second metal material layer is used as a resist layer, and the lower surface of the thin plate substrate is selectively partially etched to form a groove.

步骤 4: 配置绝缘填充材料  Step 4: Configure the insulation filler

在薄板基材下部分经选择性半蚀刻形成的凹槽中填充绝缘 料。  A portion of the recess formed by selective half etching under the sheet substrate is filled with an insulating material.

步骤 5: 上表面选择性部分饨刻  Step 5: Selective partial engraving on the upper surface

移除薄板基材上表面的掩膜材料层， 以第一金属材料层为阻蚀层， 对薄板基材上表面 进行选择性部分蚀刻，形成具有台阶式结构的引线框架，包括分离的芯片载体和多圈引脚。  Removing the mask material layer on the upper surface of the thin plate substrate, selectively etching the upper surface of the thin plate substrate to form a lead frame having a stepped structure, including the separated chip carrier, using the first metal material layer as a resist layer And multi-turn pins.

步骤 6: 配置母 IC芯片  Step 6: Configure the parent IC chip

通过含银颗粒的环氧树脂树脂或者胶带等粘贴材料将母 IC 芯片配置于芯片载体中央 部位。  The mother IC chip is placed in the center of the chip carrier by an epoxy resin such as silver-containing particles or a bonding material such as a tape.

步骤 7: 配置子 IC芯片  Step 7: Configure the sub IC chip

通过含银颗粒的环氧树脂树脂或者胶带等粘贴材料将子 IC芯片配置于母 IC芯片的有 缘面上， 或者在母 IC芯片的有缘面上配置隔片， 将子 iC芯片配置于隔片上。  The sub IC chip is placed on the edge of the mother IC chip by an adhesive material such as an epoxy resin or a tape containing silver particles, or a spacer is disposed on the edge surface of the mother IC chip, and the sub iC chip is placed on the spacer.

步骤 8: 金属导线键合连接  Step 8: Metal wire bonding connection

母 IC芯片和子 IC芯片上的多个键合焊盘通过金属导线分别连接至配置有第一金属材 料层的多个引胸的内引胸上， 以实现电气互联。  A plurality of bonding pads on the mother IC chip and the sub IC chip are respectively connected to the inner chests of the plurality of chests provided with the first metal material layer through the metal wires to realize electrical interconnection.

步骤 9: 塑封  Step 9: Plastic seal

通过塑封材料包覆母 iC芯片、 子 IC芯片、 金属导线、 粘贴材料、 引线框架和第一金 属材料层， 形成封装件产阵列， 或者包覆母 IC芯片、 子 IC芯片、 金属导线、 隔片、 引线 框架和第一金属材料层， 形成封装件产品阵列。  The mother iC chip, the sub IC chip, the metal wire, the bonding material, the lead frame and the first metal material layer are coated by a molding material to form an array of package products, or a mother IC chip, a sub IC chip, a metal wire, a spacer The lead frame and the first layer of metallic material form an array of package products.

歩骤 10: 打印  Step 10: Print

对塑封后的产品阵列进行激光打印。  Laser printing of the molded product array.

步骤 12: 切割分离产品  Step 12: Cutting the separated product

切割分离产品， 形成独立的单个封装件。  The separated products are cut to form a single, individual package.

根据本发明的实施例， 通过电镀或者化学镀方法配置第一金属材料层和第二金属材料 层。  According to an embodiment of the present invention, the first metal material layer and the second metal material layer are disposed by electroplating or electroless plating.

根据本发明的实施例， 以第二金属村料层为抗蚀层， 选 ^仅蚀刻薄板基材的蚀刻液对 薄板基材上表面和下表面选择性部分饨刻。  According to an embodiment of the present invention, the second metal substrate layer is used as a resist layer, and the etching liquid for etching only the thin plate substrate is selectively etched selectively on the upper surface and the lower surface of the thin plate substrate.

根据本发明的实施例， 绝缘填充材料通过丝网印刷或者涂布等方法配置在半饨刻凹槽 中。  According to an embodiment of the present invention, the insulating filler material is disposed in the half-etching groove by screen printing or coating or the like.

根据本发明的实施例， 选用刀片切割、 激光切割或者水刀切割等方法切割分离产品， 旦仅切割塑封材料和绝缘填充材料， 不切割引线框架。 基干上述，根据本发明，基干传统 QFN封装的芯片上芯片封装件结构为：三维立体封装, 高度可控制在 0.7毫米范 i簡内， 具有较高的 : I/O密度和集成度， 引线框架的台阶式结构增 加了与塑封材料和绝缘填充材料的结合面积， 具有与塑封材料和绝缘填充材料相互锁定的 效果， 能够有效防止引线框架与塑封材料和绝缘填充材料的分层以及引胸或芯片载体的脱 落， 有效阻止湿气从封装件结构外部向内部扩散， 小面积尺寸的外引脚能够有效防止表面 贴装时桥连现象的发生， 引线框架上表面和 T表面配置的第一金属材料层和第二金属材料 层能够有效提高金属引线键合质量和表面贴装质量， 由于单个封装体之间仅由塑封材料和 绝缘填充材料相连， 因此当使用切割刀切割分离产品， 不会切割到引线框架金属材料， 从 而提高了切割效率， 延长了切割刀的寿命， 防止了金属毛刺的产生， 同时省去了传统 QFN 封装流程中的塑封前引线框架背面粘贴胶膜、 塑封后去除胶膜和塑封料飞边等工艺， 降低 了封装成本。 According to an embodiment of the present invention, the separation product is cut by a blade cutting, laser cutting or water jet cutting method, and only the molding material and the insulating filling material are cut, and the lead frame is not cut. According to the present invention, the chip-on-chip package structure of the basic conventional QFN package is: a three-dimensional package, and the height can be controlled within a range of 0.7 mm, with high: I/O density and integration, lead frame The stepped structure increases the bonding area with the molding material and the insulating filler material, and has the effect of interlocking with the molding material and the insulating filler material, and can effectively prevent the delamination of the lead frame from the molding material and the insulating filler material, and the chest or chip. The detachment of the carrier effectively prevents moisture from diffusing from the outside to the inside of the package structure, and the outer lead of the small-area size can effectively prevent the occurrence of bridging during surface mounting, and the first metal material disposed on the upper surface of the lead frame and the T surface The layer and the second metal material layer can effectively improve the metal wire bonding quality and the surface mount quality. Since the single package body is only connected by the molding material and the insulating filler material, when the cutting product is cut by using a cutting blade, the cutting product is not cut. Lead frame metal material, which improves cutting efficiency and prolongs the life of the cutting blade The production of metal burrs is eliminated, and the process of attaching the adhesive film on the back side of the plastic lead frame in the conventional QFN packaging process, removing the film after the plastic sealing and flashing of the molding material, and the like, thereby reducing the packaging cost.

下文特举实施倒， 并配合附图对本发明的上述特征和优点做详细说明。  The above features and advantages of the present invention are described in detail below with reference to the accompanying drawings.

爾图说明  Description

图 1A为传统 QFN封装结构的背面示意图；  1A is a schematic rear view of a conventional QFN package structure;

图 B为沿图 A中的 剖面的剖面示意图；  Figure B is a schematic cross-sectional view along the section in Figure A;

图 2A为根据本发明的实施例绘制的引脚横截面为圆形，且芯片载体每边的引脚排列方 式为平行排列的芯片上芯； t封装件结构的背面示意图：  2A is a cross-sectional view of a chip having a circular cross section and a pin arrangement on each side of the chip carrier arranged in parallel according to an embodiment of the present invention;

图 2B为根据本发明的实施例绘制的引脚横截面为矩形，且芯片载体每边的引脚排列方 式为平行排列的芯片上芯片封装件结构的背面示意图；  2B is a schematic rear view of a chip-on-chip package structure in which the pin cross-section is rectangular and the pin arrangement on each side of the chip carrier is parallel arranged according to an embodiment of the present invention;

图 3A为根据本发明的实施^绘制的引脚横截面为圆形,且芯； t载体每边的引胸排列方 式为交错排列的芯片上芯片封装件结构的背面示意图；  3A is a schematic rear view of a chip-on-chip chip structure in which the cross-section of the lead is circular and the core; t-carriers are arranged in a staggered arrangement on the chip according to an embodiment of the present invention; FIG.

图 3B为根据本发明的实施例绘制的引脚横截面为矩形，且芯片载体每边的引胸排列方 式为交错排列的芯片上芯片封装件结构的背面示意图；  3B is a schematic rear view of a chip-on-chip chip structure in which the cross-section of the lead is rectangular, and the chest arrangement on each side of the chip carrier is staggered according to an embodiment of the present invention; FIG.

图 4为根据本发明的实施 ^绘制的，沿图 2A- B和图 3A- B中的 W 剖面的剖面示意图； 图 5为根据本发明的实施例绘制的，沿图 2A- B和图 中的 W 剖面的剖面示意图； 图 6A至图 6M为根据本发明的实施倒绘制的芯片上芯片封装件结构的制造流程剖面示 意图， 所有剖面示意图都为沿图 4剖面所示的剖面示意图。  Figure 4 is a cross-sectional view taken along line W of Figures 2A-B and 3A-B, in accordance with an embodiment of the present invention; Figure 5 is an illustration of an embodiment of the present invention, along Figure 2A-B and FIG. 6A to FIG. 6M are schematic cross-sectional views showing a manufacturing process of an on-chip chip package structure according to an embodiment of the present invention, and all cross-sectional views are schematic cross-sectional views taken along the line of FIG.

图中标号： 100,传统四边扁平无引脚封装结构， 1 1 ,引脚框架， 1 1 1.芯； t载体 U 2.引脚, 12.塑封材料, 13.粘片材料， 14.IC芯片， 15.金属导线, 200 > 200A, 2議、 200a, 200b、 200c, 200d,芯 j†上芯片 ( CoC )封装件结构， 201 .引线框架， 202.芯片载体， 203.引脚， 20. 薄板基材， 20a,薄板基村上表面、弓 I线框架上表面， 20b.薄板基材 T表面、引线框架下表面， 21a, 21b,掩膜材料层， 22,第一金属材料层， 23,第二金属材料层， 22a.第一金属材料层表面， 23a.第二金属材料层表面， 24.凹槽， 24a.台阶式结构表面， 24b.台阶式结构， 25.绝缘填充 材料， 25a,绝缘填充材料表面， 26.粘贴材料， 27,母 IC芯片， 28.子 IC芯片， 29.金属导线， 30,塑封材料， 31.隔片  Number in the figure: 100, traditional four-sided flat leadless package structure, 1 1 , lead frame, 1 1 1. core; t carrier U 2. pin, 12. molding material, 13. adhesive material, 14.IC Chip, 15. Metal wire, 200 > 200A, 2, 200a, 200b, 200c, 200d, core chip (CoC) package structure, 201. Lead frame, 202. Chip carrier, 203. Pin, 20 Thin plate substrate, 20a, upper surface of thin plate base, upper surface of bow I wire frame, 20b. surface of thin plate substrate T, lower surface of lead frame, 21a, 21b, layer of mask material, 22, layer of first metal material, 23 , second metal material layer, 22a. first metal material layer surface, 23a. second metal material layer surface, 24. groove, 24a. stepped structure surface, 24b. stepped structure, 25. insulating filler material, 25a , insulating filler material surface, 26. bonding material, 27, mother IC chip, 28. sub IC chip, 29. metal wire, 30, plastic sealing material, 31. spacer

具体实施方式  detailed description

下面结合 i 图对本发明进行详细说明 - 图 2A为根据本发明的实施飼绘制的引脚横截面为圆形,且芯片载体每边的引胸排列方 式为平行排列的芯片上芯 i†封装件结构的背面示意图。 The present invention will be described in detail below with reference to the figure i - 2A is a rear schematic view of a chip-on-core package structure in which the lead cross-section is circular in shape and the chest arrangement of each side of the chip carrier is parallel arranged in accordance with the present invention.

图 2B为根据本发明的实施例绘制的引脚横截面为矩形，且芯片载体每边的引脚排列方 式为平行排列的芯片上芯； t封装件结构的背面示意图。  2B is a cross-sectional view of a chip having a rectangular cross section and a pin arrangement on each side of the chip carrier in a parallel arrangement according to an embodiment of the present invention;

参照上述图 2A- B可以看出，在本实施例中， 芯片上芯片封装件结构 200a和 200b的引 线框架 201包括芯片载体 202和围绕芯片载体 202呈多圈排列的引脚 203，且芯片载体 202 每边的引脚 203的排列方式为平行排列,在引线框架 201下表面配置有第二金属村料层 23, 在引线框架 201中配置有绝缘填充材料 25。 不同之处在于图 2A的芯片上芯片封装件结构 中的引脚横截面为圆形， 图 2B的芯片上芯片封装件结构中的引脚横截面为矩形。  2A-B, in the present embodiment, the lead frame 201 of the on-chip chip package structures 200a and 200b includes a chip carrier 202 and pins 203 arranged in a plurality of circles around the chip carrier 202, and the chip carrier The pins 203 on each side are arranged in parallel, and a second metal frit layer 23 is disposed on the lower surface of the lead frame 201, and an insulating filler 25 is disposed in the lead frame 201. The difference is that the pin cross-section of the on-chip chip package structure of Fig. 2A is circular, and the pin cross section of the on-chip chip package structure of Fig. 2B is rectangular.

图 3A为根据本发明的实施例绘制的引脚横截面为圆形，且芯 j†载体每边的引脚排列方 式为交错排列的芯片上芯片封装件结构的背面示意图。  3A is a rear schematic view of a chip-on-chip package structure in which the pin cross-section is circular and the pin arrangement on each side of the core is staggered in accordance with an embodiment of the present invention.

图 3B为根据本发明的实施例绘制的引脚横截面为矩形，且芯； t载体每边的引胸排列方 式为交错排列的芯片上芯片封装件结构的背面示意图。  3B is a rear schematic view showing the structure of a chip-on-chip package in which the cross-section of the lead is rectangular and the core is arranged in a staggered arrangement on each side of the t-carrier according to an embodiment of the present invention.

参照上述图 3A B可以看出，在本实施例中，芯片上芯片封装件结构 200c和 200d的引 线框架 201包括芯片载体 202和围绕芯片载体 202呈多圈排列的引脚 203，且芯片载体 202 每边的引胸 203的排列方式为交错排列,在引线框架 201下表面配置有第二金属材料层 23， 在引线框架 201中配置有绝缘填充材料 25。 不同之处在于图 3A的芯片上芯片封装件结构 中的引脚横截面为圆形， 图 3B的芯 j†上芯片封装件结构中的引脚横截面为矩形。  Referring to FIG. 3A B above, it can be seen that in the present embodiment, the lead frame 201 of the on-chip chip package structures 200c and 200d includes a chip carrier 202 and pins 203 arranged in a plurality of circles around the chip carrier 202, and the chip carrier 202 The arrangement of the chests 203 on each side is staggered, and a second metal material layer 23 is disposed on the lower surface of the lead frame 201, and an insulating filler 25 is disposed in the lead frame 201. The difference is that the pin cross-section in the chip-on-chip structure of Fig. 3A is circular, and the pin cross-section in the chip package structure of the core of Fig. 3B is rectangular.

图 4为沿图 2A-B和图 3A- B中的 I-I 剖面的剖面示意图。 结合图 2A-B、 图 3A-B, 参 照图 4, 在本实施例中， 芯片上芯片封装件结构 200A包括引线框架 201、 第 ·金属村料层 22、 第二金属材料层 23、 绝缘填充材料 25、 粘贴材料 26、 母 IC芯片 27、 子 IC芯 j†28、 金属导线 29以及塑封材料 30。  Figure 4 is a schematic cross-sectional view taken along line I-I of Figures 2A-B and 3A-B. Referring to FIG. 2A-B, FIG. 3A-B, referring to FIG. 4, in the embodiment, the on-chip chip package structure 200A includes a lead frame 201, a metal substrate layer 22, a second metal material layer 23, and an insulating pad. The material 25, the bonding material 26, the mother IC chip 27, the sub IC core j†28, the metal wires 29, and the molding material 30.

在本实施倒中， 引线框架 201 作为导电、 散热、 连接外部电路的通道， 沿厚度方向具 有台阶式结构 24b, 具有上表面 20a和相对于上表面 20a的下表面 20b, 以及台阶式结构 24b的台阶表面 24a。引线框架 201包括芯片载体 202和围绕芯片载体 202呈多圈排列的引 脚 203， 芯片载体 202和 I绕芯片载体 202呈多圈排列的弓 i脚 203都具有台阶式结构 24b。 芯; t载体 202配置于引线框架 201中央部位， 芯片载体 202四边边缘部位沿厚度方向具有 台阶式结构 24b。 多个引脚 203配置于芯片载体 202四周， 圈绕芯片载体 202呈多圈排列， ϋ沿厚度方向具有台阶结构 24b， 其橫截面形状呈圆形或者矩形状， 其中每个引脚 203包 括配置于该上表面 20a的內引脚和配置于该下表面 20b的外弓 i脚。  In the present embodiment, the lead frame 201 serves as a passage for conducting, dissipating, and connecting an external circuit, having a stepped structure 24b in the thickness direction, having an upper surface 20a and a lower surface 20b with respect to the upper surface 20a, and a stepped structure 24b. Step surface 24a. The lead frame 201 includes a chip carrier 202 and pins 203 arranged in a plurality of turns around the chip carrier 202, and the chip carriers 202 and I are arranged in a plurality of turns around the chip carrier 202 to have a stepped structure 24b. The core carrier t is disposed at a central portion of the lead frame 201, and the four edge portions of the chip carrier 202 have a stepped structure 24b in the thickness direction. The plurality of pins 203 are disposed around the chip carrier 202, and the coils are arranged in a plurality of turns around the chip carrier 202. The crucible has a stepped structure 24b in the thickness direction, and the cross-sectional shape thereof is circular or rectangular, wherein each of the pins 203 includes a configuration. The inner lead of the upper surface 20a and the outer bow disposed on the lower surface 20b.

第一金属材料层 22和第二金属材料层 23分别配置于引线框架 201的上表面 2( 位置 和引线框架 201的下表面 20b位置， 第一金属材料层 22与引脚 203的内引脚具有相同尺 寸大小， 第二金属材料层 23与引脚 203的外引脚具有相同尺寸大小。 第一金属材料层 22 具有第一金属材料层表面 22a， 第二金属材料层 23具有第二金属材料层表面 23a。  The first metal material layer 22 and the second metal material layer 23 are respectively disposed on the upper surface 2 of the lead frame 201 (position and the lower surface 20b of the lead frame 201, and the first metal material layer 22 and the inner lead of the pin 203 have The same size, the second metal material layer 23 has the same size as the outer lead of the lead 203. The first metal material layer 22 has a first metal material layer surface 22a, and the second metal material layer 23 has a second metal material layer. Surface 23a.

绝缘填充材料 25配置于引线框架 20〗 的台阶式结构 24下， 对引线框架 201起到支撑 和保护的作 ]¾， 绝缘填充材料 25具有绝缘填充材料表面 25a， 绝缘填充材料表面 25a与第 二金属材料层表面 23a处于同一水平面上。  The insulating filling material 25 is disposed under the stepped structure 24 of the lead frame 20, and supports and protects the lead frame 201. The insulating filling material 25 has an insulating filling material surface 25a, and the insulating filling material surface 25a and the second The metal material layer surface 23a is on the same level.

母 IC芯片 27通过粘贴材料 26配置于弓！线框架 201的上表面 20a的第一金属材料层 22 位置， 且配置于芯片载体 202的中央部位， 子 IC芯片 28通过粘贴材料 26配置于母 IC芯 片 27的有缘面上。 母芯片 27和子 C芯片 28上的多个键合焊盘通过金属导线 29分别连 接至配置有第一金属材料层 22的多个引脚的内引脚上， 实现电气互联。 The mother IC chip 27 is placed on the bow by the bonding material 26! The first metal material layer 22 of the upper surface 20a of the wire frame 201 is disposed at a central portion of the chip carrier 202, and the sub IC chip 28 is disposed on the mother IC core by the bonding material 26. The edge of the sheet 27 has a rim. The plurality of bonding pads on the mother chip 27 and the sub-C chip 28 are respectively connected to the inner pins of the plurality of pins on which the first metal material layer 22 is disposed by the metal wires 29 to electrically interconnect.

塑封材料 30包覆上述母 IC芯片 27、 子 IC芯片 28、 粘贴材料 26、 金属导线 29、 弓 I线 框架 201和第一金属材料层 22, 暴露出配置于引线框架下表面 20b的第二金属材料层 23。  The molding material 30 covers the mother IC chip 27, the sub IC chip 28, the bonding material 26, the metal wires 29, the bow wire frame 201, and the first metal material layer 22, exposing the second metal disposed on the lower surface 20b of the lead frame. Material layer 23.

图 5为沿图 2A- B和图 3A- B中的 I- :ί 剖面的剖面示意图。 结合图 2Α- E、 图 3 A-E 参 照图 5， 在本实施例中， 芯片上芯片封装件结构 200B包括引线框架 20i、 第一金属材料层 22、 第二金属材料层 23、 绝缘填充材料 25、 粘贴材料 26、 母 IC芯片 27、 子 IC芯片 28、 金属导线 29、 塑封材料 30和隔片 31。  Figure 5 is a cross-sectional view taken along the line I-: ί in Figures 2A-B and 3A-B. Referring to FIG. 2A-E, FIG. 3 AE, FIG. 5, in this embodiment, the on-chip chip package structure 200B includes a lead frame 20i, a first metal material layer 22, a second metal material layer 23, an insulating filling material 25, The bonding material 26, the mother IC chip 27, the sub IC chip 28, the metal wires 29, the molding material 30, and the spacers 31.

在本实施倒中， 引线框架 20】 作为导电、 散热、 连接外部电路的通道， 沿厚度方向具 有台阶式结构 24b， 具有上表面 20a和相对于上表面 20a的 T表面 20b， 以及台阶式结构 24b的台阶表面 24a。引线框架 201包括芯片载体 202和围绕芯片载体 202呈多圈排列的引 脚 203 , 芯片载体 202和 绕芯片载体 202呈多圈排列的引脚 203都具有台阶式结钩 24b。 芯片载体 202配置于引线框架 201中央部位， 其横截面形状呈矩形状， 芯片载体 202四边 边缘部位沿厚度方向具有台阶式结构 24b。 多个引脚 203配置于芯片载体 202四周， 围绕 芯片载体 202呈多圈排列， 且沿厚度方向具有台阶结构 24b, 其横截面形状呈圆形或者矩 形状， 其中每个引脚 203包括配置于该上表面 20a的内引脚和配置于该下表面 20b的夕卜引 脚。  In the present embodiment, the lead frame 20 has a stepped structure 24b in the thickness direction as a passage for conducting, dissipating, and connecting an external circuit, having an upper surface 20a and a T surface 20b with respect to the upper surface 20a, and a stepped structure 24b. Step surface 24a. The lead frame 201 includes a chip carrier 202 and pins 203 arranged in a plurality of turns around the chip carrier 202. The chip carrier 202 and the pins 203 arranged in a plurality of turns around the chip carrier 202 have stepped hooks 24b. The chip carrier 202 is disposed at a central portion of the lead frame 201, and has a rectangular cross section. The four edge portions of the chip carrier 202 have a stepped structure 24b in the thickness direction. The plurality of pins 203 are disposed around the chip carrier 202, arranged in a plurality of circles around the chip carrier 202, and have a stepped structure 24b in a thickness direction, the cross-sectional shape of which is circular or rectangular, wherein each of the pins 203 includes The inner lead of the upper surface 20a and the outer lead of the lower surface 20b.

第一金属材料层 22和第二金属材料层 23分别配置于引线框架 201的上表面 20a位置 和引线框架 201的下表面 20b位置， 第一金属材料层 22与引脚 203的内引脚具有相同尺 寸大小， 第二金属材料层 23与引脚 203的外引脚具有相同尺寸大小。 第 ·金属村料层 22 具有第一金属材料层表面 22a， 第二金属材料层 23具有第二金属材料层表面 23a。  The first metal material layer 22 and the second metal material layer 23 are respectively disposed at positions of the upper surface 20a of the lead frame 201 and the lower surface 20b of the lead frame 201, and the first metal material layer 22 has the same inner pin as the lead 203. Dimensions, the second metal material layer 23 has the same size as the outer leads of the leads 203. The metal metal layer 22 has a first metal material layer surface 22a, and the second metal material layer 23 has a second metal material layer surface 23a.

绝缘填充材料 25配置于引线框架 201的台阶式结构 24下， 对引线框架 201起到支撑 和保护的作用， 绝缘填充材料 25具有绝缘填充材料表面 25a, 绝缘填充材料表面 25a与第 二金属材料层表面 23a处于同一水平面上。  The insulating filling material 25 is disposed under the stepped structure 24 of the lead frame 201 to support and protect the lead frame 201. The insulating filling material 25 has an insulating filling material surface 25a, an insulating filling material surface 25a and a second metal material layer. The surface 23a is on the same level.

母 IC芯 j† 27通过粘贴材料 26配置于引线框架 201的上表面 20a的第一金属材料层 22 位置， 且配置于芯片载体 202的中央部位， 隔片 31配置于母 IC芯片 27的有缘面上， 子 IC芯片 28配置于隔片 3】上， 隔片 31的存在保持母 : C芯片 27与子 : C芯片 28之间具有 一定高度的间距。 母芯片 27和子 C芯片 28上的多个键合焊盘通过金属导线 29分別连接 至配置有第一金属材料层 22的多个引胸的內引胸上， 实现电气互联。  The mother IC core j† 27 is disposed on the first metal material layer 22 of the upper surface 20a of the lead frame 201 by the bonding material 26, and is disposed at the central portion of the chip carrier 202, and the spacer 31 is disposed on the rim surface of the mother IC chip 27. The sub IC chip 28 is disposed on the spacer 3, and the presence of the spacer 31 maintains a pitch of a certain height between the C chip 27 and the sub:C chip 28. The plurality of bonding pads on the mother chip 27 and the sub-C chip 28 are respectively connected to the inner chests of the plurality of chests on which the first metal material layer 22 is disposed by the metal wires 29 to electrically interconnect.

塑封材料 30包覆上述母 IC芯片 27、 子 IC芯片 28、 金属导线 29、 隔片 31、 引线框架 201和第一金属材料层 22, 暴露出配置于引线框架下表面 20b的第二金属材料层 23。  The molding material 30 covers the mother IC chip 27, the sub IC chip 28, the metal wires 29, the spacers 31, the lead frame 201, and the first metal material layer 22, exposing the second metal material layer disposed on the lower surface 20b of the lead frame. twenty three.

下面将以图 6A至图 6M来详细说明一种芯片上芯片 （CoC) 封装件结构的制造流程。 图 6A至图 6M为根据本发明的实施例绘制的芯片上芯片（CoC)封装件结构的制造流 程剖面示意图， 所有剖面示意图都为沿图 4剖面所示的剖面示意图。  The manufacturing process of a chip-on-chip (CoC) package structure will be described in detail below with reference to Figs. 6A to 6M. 6A through 6M are schematic cross-sectional views showing a manufacturing process of a chip-on-chip (CoC) package structure, which is a cross-sectional view taken along the line of Fig. 4, in accordance with an embodiment of the present invention.

请参照图 6A, 提供具有上表面 20a和相对于上表面 20a的下表面 20b的薄板基材 20, 薄板基材 20 的材料可以是铜、 铜合金、 铁、 铁合金、 镍、 镍合金以及其他适 ]¾于制作引 线框架的金属材料。薄板基材 20的厚度范围为 0. mm-0.25ram，例如为 0.127mm， 0, i52ram， 0。203ηπη。对薄板基 20的上表面 20a和下表面 20b迸行清洗和预处理， 倒如用等离子水 去油污、 灰尘等， 以实现薄板基材 20的上表面 20a和下表面 20b清洁的目的。 请参照图 6B, 在薄板基村 20的上表面 2(¾和下表面 20b上分别配置具有窗口的掩膜材料 层 21a和掩膜材料层 2ib， 这里所述的窗口是指没有被掩膜材料层 2ia和掩膜材料层 21b覆盖 的薄板基材 20, 掩膜材料层 21a和掩膜材料层 21b保护被其覆盖的薄板基材 20, 在后面的工 艺步骤中将对被掩膜材料层: Ha和掩膜材料层 21b覆盖的薄板基材 20进行饨刻。 Referring to FIG. 6A, a thin plate substrate 20 having an upper surface 20a and a lower surface 20b opposite to the upper surface 20a is provided. The material of the thin plate substrate 20 may be copper, copper alloy, iron, iron alloy, nickel, nickel alloy, and the like. ] 3⁄4 in the metal material of the lead frame. The thickness of the sheet substrate 20 ranges from 0. mm to 0.25 ram, for example, 0.127 mm, 0, i52 ram, 0. 203 η πη. The upper surface 20a and the lower surface 20b of the thin plate substrate 20 are cleaned and pretreated, for example, by using plasma water to remove oil, dust, or the like, for the purpose of cleaning the upper surface 20a and the lower surface 20b of the thin plate substrate 20. Referring to FIG. 6B, a mask material layer 21a and a mask material layer 2ib having windows are respectively disposed on the upper surface 2 (3⁄4 and the lower surface 20b of the thin plate base 20), and the window described herein means that there is no mask material. The thin plate substrate 20 covered by the layer 2ia and the mask material layer 21b, the mask material layer 21a and the mask material layer 21b protect the thin plate substrate 20 covered by it, and the layer of the mask material will be layered in a later process step: Ha and the thin-plate base material 20 covered by the mask material layer 21b are etched.

请参照图 6C, 在配置于薄板基村 20的上表面 20a上的掩膜材料层 21a的窗口中配置 第一金属材料层 22，第一金属材料层 22具有第一金属材料层表面 22a，在配置于薄板基材 20的下表面 20b上的掩膜 料层 21b的窗口中配置第二金属材料层 23 , 第二金属 料层 23具有第二金属材料层表面 23a。 第一金属材料层 22和第二金属材料层 23的配置方法为 电镀、 化学镀、 蒸发、 溅射等方法， 并且允许由不同的金属材料组成， 在本实施例中， 优 先选择电镀或者化学镀诈为第一金属材料层 22和第二金属材料层 23的配置方法。 第一金 属材料层 22和第二金属材料层 23的村料是镍 (Ni)、 钯 (Pd)、 金 (Αί3)、 银 (Ag)、 锡 (Sn等金 属材料及其合金， 在本实施倒中， 第一金属材料层 22和第二金属材料层 23例如是镍-钯- 金镀层， 对于第一金属材料层 22， 外面的金镀层和中间的钯镀层是保证金属导线 29在引 线框架 201上的可键合性和键合质量， 里面的镍镀层是作为扩散阻挡层以防止由元素扩散 -化学反应引起的过厚共晶化合物的生成， 过厚的共晶化合物影响键合区域的可靠性， 对于 第二金属材料层 23 ,外面的金镀层和中间的钯镀层是保证焊料在引线框架 201的可浸润性， 提高封装体在 PCB等电路板上表面贴装的质量，里面的镍镀层是作为扩散阻挡层以防止由 元素扩散-化学反应引起的过厚共晶化合物的生成，过厚的共晶化合物影响表面贴装焊接区 域的可靠性。 Referring to FIG. 6C, a first metal material layer 22 is disposed in a window of the mask material layer 21a disposed on the upper surface 20a of the thin plate base 20, and the first metal material layer 22 has a first metal material layer surface 22a. The second metal material layer 23 is disposed in the window of the mask layer 21b disposed on the lower surface 20b of the thin plate substrate 20, and the second metal layer 23 has the second metal material layer surface 23a. The first metal material layer 22 and the second metal material layer 23 are disposed by plating, electroless plating, evaporation, sputtering, etc., and are allowed to be composed of different metal materials. In this embodiment, electroplating or electroless plating is preferred. The method of arranging the first metal material layer 22 and the second metal material layer 23 is smeared. The materials of the first metal material layer 22 and the second metal material layer 23 are nickel (Ni), palladium (Pd), gold (Α ί3 ), silver (Ag), tin (Sn and other metal materials and alloys thereof, In the implementation, the first metal material layer 22 and the second metal material layer 23 are, for example, a nickel-palladium-gold plating layer. For the first metal material layer 22, the outer gold plating layer and the intermediate palladium plating layer ensure that the metal wire 29 is in the lead wire. The bondability and bonding quality on the frame 201, the nickel plating inside is used as a diffusion barrier to prevent the formation of excessively thick eutectic compounds caused by elemental diffusion-chemical reactions, and the excessively thick eutectic compounds affect the bonding regions. The reliability, for the second metal material layer 23, the outer gold plating layer and the intermediate palladium plating layer ensure the wettability of the solder in the lead frame 201, and improve the quality of the surface mounting of the package on a circuit board such as a PCB. The nickel plating layer acts as a diffusion barrier to prevent the formation of an excessively thick eutectic compound caused by elemental diffusion-chemical reactions, and the excessively thick eutectic compound affects the reliability of the surface mount soldered region.

请参照图 61〕， 将薄板基村 20的下表面 20b上的掩膜材料层 21 b移除， 在本实施例中 的移除方法可以是化学反应方法和机械方法， 化学反应方法是选 ^可溶性的碱性溶液， 例 如氢氧化钾 （KDH) 、 氢氧化钠 （NaOH) , 采用喷淋等方式与薄板基材 20的下表面 20b 上的掩膜材料层 21b进行化学反应， 将其溶解从而达到移除的效果， 移除掩膜材料层: Hb 后， 薄板基材 20的下表面 20b上仅剩下第二金属材料层 23。  Referring to FIG. 61], the mask material layer 21 b on the lower surface 20b of the thin plate base 20 is removed. The removal method in this embodiment may be a chemical reaction method or a mechanical method, and the chemical reaction method is selected. A soluble alkaline solution such as potassium hydroxide (KDH) or sodium hydroxide (NaOH) is chemically reacted with the mask material layer 21b on the lower surface 20b of the thin plate substrate 20 by spraying or the like to dissolve it. To achieve the effect of removal, after removing the mask material layer: Hb, only the second metal material layer 23 remains on the lower surface 20b of the thin plate substrate 20.

请参照图 6E，以薄板基材 20的下表面 20b上的第二金属材料层 23诈为蚀刻的抗蚀层， 采 ffl喷淋方式对薄板基材 20 T表面 20b迸行选择性部分蚀刻， 形成凹槽 24和台阶式结构 表面 24a, 蚀刻深度范围可以是占薄板基材 20的厚度的 40%- 90%。在本实施例中， 喷淋方 式优先采用上喷淋方式， 蚀刻液优先选择碱性蚀刻液， 如碱性氯化铜饨刻液、 氯化铵等碱 性蚀刻液， 以减少蚀刻液对第二金属材料层 23的破坏作用。  Referring to FIG. 6E, the second metal material layer 23 on the lower surface 20b of the thin plate substrate 20 is etched into a resist layer, and the surface 20b of the thin plate substrate 20 T is selectively partially etched by a spray method. The groove 24 and the stepped structure surface 24a are formed, and the etching depth may range from 40% to 90% of the thickness of the thin plate substrate 20. In the embodiment, the spraying method preferably adopts the upper spraying method, and the etching liquid preferentially selects an alkaline etching liquid, such as an alkaline copper chloride engraving liquid, an alkaline etching solution such as ammonium chloride, to reduce the etching liquid pair. The damaging action of the second metal material layer 23.

请参照图 6F, 在薄板基材 20的下表面 20b经选择性部分蚀刻形成的凹槽 24中填充绝 缘填充材料 25 , 绝缘填充材料 25具有表面 25a， 该表面与第二金属材料层表面 23a处于同 一水平面上。 在本实施倒中， 绝缘填充村料 25 是热固性塑封材料、 塞孔树脂、 油墨以及 阻焊绿油等绝缘材料， 绝缘填充材料 25 具有足够的酎酸、 耐碱性， 以保证后续的工艺不 会对巳形成绝缘填充材料 25造成破坏， 绝缘填充村料 25的填充方法是通过注塑或者丝网 印刷等方法填充到凹槽 24 中， 配置后用机械研磨方法或者化学处理方法去除过多的绝缘 填充材料 25 , 以消除绝缘填充材料 25的溢料， 使绝缘填充材料 25的表面 25a与第二金属 材料层表面 23a处于同一水平面上， 对于感光型阻焊绿油等绝缘填充材料 25， 通过显影方 法去除溢料。 请参照图 6G， 将薄板基材 20的上表面 20a上的掩膜材料层 21a移除， 在本实施倒中 的移除方法可以是化学反应方法和机械方法， 化学反应方法是选 ^可溶性的碱性溶液， 例 如氢氧化钾 （KDH) 、 氢氧化钠 （NaOH) , 采 ffl喷淋等方式与薄板基材 20的上表面 20a 上的掩膜材料层 21a化学反应， 将其溶解从而达到移除的效果， 移除掩膜材料层 2】a后， 薄板基材 20的上表面 20a上仅剩下第 ·金属材料层 22。 Referring to FIG. 6F, the recess 24 formed by selective partial etching on the lower surface 20b of the thin plate substrate 20 is filled with an insulating filler material 25 having a surface 25a which is at the surface 23a of the second metal material layer. On the same level. In the embodiment, the insulating filling material 25 is an insulating material such as a thermosetting plastic sealing material, a plug resin, an ink, and a solder resist green oil, and the insulating filling material 25 has sufficient tannic acid and alkali resistance to ensure the subsequent process is not The ruthenium may be damaged by the formation of the insulating filler material 25. The filling method of the insulating filler material 25 is filled into the groove 24 by injection molding or screen printing, and the mechanical insulation or chemical treatment is used to remove excessive insulation after the configuration. Filling the material 25 to eliminate the flash of the insulating filler 25, so that the surface 25a of the insulating filler 25 and the surface 23a of the second metal material layer are at the same level, and the insulating filler 25 such as the photosensitive solder resist green oil is developed. The method removes the flash. Referring to FIG. 6G, the mask material layer 21a on the upper surface 20a of the thin plate substrate 20 is removed. The removal method in the present embodiment may be a chemical reaction method and a mechanical method, and the chemical reaction method is selected to be soluble. An alkaline solution, such as potassium hydroxide (KDH), sodium hydroxide (NaOH), spray, or the like, chemically reacts with the mask material layer 21a on the upper surface 20a of the thin plate substrate 20 to dissolve it to achieve the shift In addition, after removing the mask material layer 2]a, only the second metal material layer 22 remains on the upper surface 20a of the thin plate substrate 20.

请参照图 6H，以薄板基材 20的上表面 20a上的第一金属材料层 22作为蚀刻的抗蚀层， 选 ffl仅蚀刻薄板基材 20的蚀刻液， 采 ffl喷淋方式对薄板基材 20上表面 2(k进行选择性部 分蚀刻， 蚀刻至台阶式结构表面 24a, 暴露出绝缘填充材料 25。 形成引线框架 201 , 引线 框架 201包括芯片载体 202和围绕芯片载体 202呈多圈排列的引脚 203 , 引线框架 201中 配置有绝缘填充材料 25，即芯片载体 202和 i簡绕芯片载体 202呈多圈棑列的引脚 203通过 绝缘填充材料 25固定在一起。 经选择性部分蚀刻后形成的分离的引脚 203具有内引脚与 外引胸， 内引脚在后续的引线键合工艺中由金属导线 28连接至母 IC芯片 27的键合焊盘， 外引脚作为连接外部电路的通道。 形成台阶式结构 24b, 台阶式结构 24b具有台阶式结构 表面 24a。 在本实施例中， 蚀刻液的喷淋方式优先采用上喷淋方式， 蚀刻液优先选择碱性 蚀刻液， 如碱性氯化铜蚀刻液、 氯化铵等碱性蚀刻液， 以减少蚀刻液对第一金属材料层 22 的破坏作用。  Referring to FIG. 6H, the first metal material layer 22 on the upper surface 20a of the thin plate substrate 20 is used as an etching resist layer, and the etching liquid of the thin plate substrate 20 is etched only by the ffl spray method. The upper surface 2 (k is selectively partially etched, etched to the stepped structure surface 24a, exposing the insulating filling material 25. Forming the lead frame 201, the lead frame 201 includes the chip carrier 202 and a plurality of turns arranged around the chip carrier 202 In the leg 203, the lead frame 201 is provided with an insulating filling material 25, that is, the chip carrier 202 and the pins 203 of the chip carrier 202 having a plurality of turns of the chip carrier 202 are fixed together by the insulating filling material 25. The selective partial etching is performed. The separate pin 203 has an inner lead and an outer lead. The inner lead is connected to the bond pad of the female IC chip 27 by a metal wire 28 in a subsequent wire bonding process, and the outer pin is connected to an external circuit. The stepped structure 24b has a stepped structure 24b, and the stepped structure 24b has a stepped structure surface 24a. In the embodiment, the spray method of the etchant is preferably sprayed. It was engraved preferred alkali etching solution, an etching solution such as alkaline copper chloride, ammonium chloride, alkaline etching solution, an etching solution to reduce the damaging effect on the material of the first metal layer 22.

请参照图 61 ,通过粘贴材料 26将母：C芯片 27配置于引线框架上表面 20a的第一金属 材料层 22位置， 且固定于芯片载体 202的中央部位， 在本实施例中， 粘贴材料 26可以是 粘片胶带、 含银颗粒的环氧树脂等材料。  Referring to FIG. 61, the mother:C chip 27 is disposed on the first metal material layer 22 of the upper surface 20a of the lead frame by the bonding material 26, and is fixed to the central portion of the chip carrier 202. In the present embodiment, the bonding material 26 is attached. It may be a material such as an adhesive tape or an epoxy resin containing silver particles.

请参照图 6,ί，通过粘贴材料 26将子：C芯片 28配置于母 :C芯片 27的有缘面上，在本 实施例中， 粘贴材料 26可以是粘片胶带、 含银颗粒的环氧树脂等材料。  Referring to FIG. 6, ί, the sub-C chip 28 is disposed on the rim surface of the mother C chip 27 by the bonding material 26. In the embodiment, the bonding material 26 may be an adhesive tape or an epoxy containing silver particles. Materials such as resins.

请参照图 6K, 母 IC芯片 27和子 IC芯片 28上的多个键合焊盘通过金属导线 29连接 至配置有第一金属材料层 22 的多引脚的内引脚上， 实现电气互联， 在本实施例中， 金属 导线 29是金线、 铝线、 铜线以及镀钯铜线等。  Referring to FIG. 6K, a plurality of bonding pads on the mother IC chip 27 and the sub IC chip 28 are connected to the multi-pin inner pins of the first metal material layer 22 through the metal wires 29 to realize electrical interconnection. In the present embodiment, the metal wires 29 are gold wires, aluminum wires, copper wires, palladium-plated copper wires, and the like.

请参照图 6L, 采用注塑方法， 通过塑封材料 30包覆母 IC芯片 27、 子 IC芯片 28、 粘 贴材料 26、 金属导线 29、 引线框架 201和第一金属 料层 22, 形成产品阵列。 在本实施 例中， 塑封材料 30可以是热固性聚合物等材料， 所填充的绝缘填充材料 25具有与塑封材 料 30相似的物理性质， 例如热膨胀系数， 以减少由热失配引起的产品失效， 提高产品的 可靠性， 绝缘填充材料 25与塑封材料 30可以是同一种材料。 塑封后进行烘烤后固化， 塑 封材料 30和绝缘填充材料 25与具有台阶式结构 24b的引线框架 201具有相互锁定功能， 可以有效防止引线框架 201与塑封材料 30和绝缘填充材料 25的分层以及引脚 203或芯片 载体 202的脱落， 而且有效阻止湿气沿着引线框架 20】与塑封材料 30和绝缘填充材料 25 的结合界面扩散到封装体内部， 提高了封装体的可靠性。 形成产品阵列后， 对产品阵列进 行激光打印。  Referring to FIG. 6L, the mother IC chip 27, the sub IC chip 28, the adhesive material 26, the metal wires 29, the lead frame 201, and the first metal layer 22 are coated by the molding material 30 by an injection molding method to form an array of products. In the present embodiment, the molding material 30 may be a material such as a thermosetting polymer, and the filled insulating filler material 25 has similar physical properties as the molding material 30, such as a thermal expansion coefficient, to reduce product failure caused by thermal mismatch, and improve The reliability of the product, the insulating filler material 25 and the molding material 30 may be the same material. After the post-baking curing, the molding material 30 and the insulating filling material 25 have a mutual locking function with the lead frame 201 having the stepped structure 24b, and the delamination of the lead frame 201 and the molding material 30 and the insulating filling material 25 can be effectively prevented. The pin 203 or the chip carrier 202 is detached, and effectively prevents moisture from diffusing along the bonding interface of the lead frame 20 and the molding material 30 and the insulating filler 25 into the inside of the package, thereby improving the reliability of the package. After the product array is formed, the product array is laser printed.

请参照图 6M , 切割芯片上芯片封装件结构产品阵列， 彻底切割分离塑封材料 30和绝 缘填充材料 25形成单个芯片上芯片封装件结构 200, 在本实施例中， 单个产品分离方法是 刀片切割、 激光切割或者水刀切割等方法， 且仅切割塑封材料 30和绝缘填充材料 25 , 不 切割引线框架金属材料， 图 6M中仅绘制出切割分离后的 2个芯片上芯片封装件结构 200。 对本发明的实施例的描述是出干有效说明和描述本发明的目的，并非用以限定本发明， 任何所属本领域的技术人员应当理解： 在不脱离本发明的发明构思和范围的条件下， 可对 上述实施例迸行变化。 故本发明并不限定于所披露的具体实施倒， 而是覆盖权利要求所定 义的本发明的实质和范围内的修改。 Referring to FIG. 6M, the chip package structure product array is cut on the chip, and the plastic package material 30 and the insulating filler material 25 are completely cut and separated to form a single on-chip chip package structure 200. In this embodiment, the single product separation method is blade cutting, Laser cutting or water jet cutting, etc., and cutting only the molding material 30 and the insulating filling material 25, without cutting the lead frame metal material, only two chip-on-chip package structures 200 after cutting and separating are drawn in FIG. 6M. The description of the embodiments of the present invention is intended to be illustrative of the invention, and is not intended to limit the scope of the invention. The above embodiment can be changed. The invention is not limited to the specific embodiments disclosed, but is intended to cover modifications within the spirit and scope of the invention as defined by the appended claims.

Claims

权利要求书 Claim 1、 一种芯片上芯片封装件结构， 其特征在于包括： What is claimed is: 1. An on-chip chip package structure, comprising: 引线框架，沿厚度方向具有台阶式结构，具有上表面、下表面和台阶表面， 其中弓 [线框架包括芯片载体、 多个引脚：  The lead frame has a stepped structure in the thickness direction, and has an upper surface, a lower surface, and a step surface, wherein the bow [line frame includes a chip carrier, a plurality of pins: 芯片载体， 配置于引线框架中央部位， 芯片载体四边边缘部位沿厚度方向 具有台阶式结构， 具有上表面、 下表面和台阶表面， 以及  a chip carrier disposed at a central portion of the lead frame, the four edge portions of the chip carrier having a stepped structure in a thickness direction, having an upper surface, a lower surface, and a step surface, and 多个引脚， 配置于芯片载体四周， 围绕芯片载体呈多圈 列， 沿厚度方向 具有台阶式结构， 具有上表面、 下表面和台阶表面， 其中每个引脚包括配置 于该上表面的内引脚和配置于该下表面的外引脚；  a plurality of pins disposed around the chip carrier, arranged in a plurality of rows around the chip carrier, having a stepped structure in the thickness direction, having an upper surface, a lower surface, and a step surface, wherein each of the pins includes a surface disposed on the upper surface a pin and an outer pin disposed on the lower surface; 第一金属村料层， 配置于引线框架的上表面位置；  a first metal village layer disposed on an upper surface of the lead frame; 第二金属村料层， 配置于引线框架的下表面位置；  a second metal village layer disposed on a lower surface of the lead frame; 金属材料层， 配置于引线框架的上表面和下表面位置；  a layer of metal material disposed on the upper surface and the lower surface of the lead frame; 绝缘填充村料， 配置于引线框架的台阶式结构下；  Insulating filled village material, disposed under the stepped structure of the lead frame; 母 IC芯片， 配置于引线框架上表面位置的第一金属材料层上， ϋ配置于 芯片载体的中央部位；  a mother IC chip disposed on the first metal material layer at the upper surface of the lead frame, and disposed on the central portion of the chip carrier; 子 IC芯片， 通过粘贴材料配置于母 IC芯片的上方， 或者通过隔片配置于 母 IC芯片的上方；  The sub IC chip is disposed above the mother IC chip through a bonding material, or is disposed above the mother IC chip through the spacer; 金属导线，母 IC芯片和子 IC芯片上的多个键合焊盘通过金属导线分别连 接至配置有第一金属材料层的多个弓 I脚的内引脚；  a metal wire, a plurality of bonding pads on the mother IC chip and the sub IC chip are respectively connected to the inner pins of the plurality of pins of the first metal material layer through the metal wires; 塑封材料， 包覆母 IC芯片、 子 IC芯片、 金属导线、 粘贴材料、 引线框架 和第一金属村料层， 形成封装件， 或者包覆母 IC芯片、 子 IC芯片、 金属导 线、 隔片、 弓 I线框架和第一金属材料层， 形成封装件。  a molding material, a mother IC chip, a sub IC chip, a metal wire, a bonding material, a lead frame, and a first metal material layer, forming a package, or covering a mother IC chip, a sub IC chip, a metal wire, a spacer, The bow I-line frame and the first metal material layer form a package. 2、 根据权利要求 1所述的一种芯片上芯片封装件结构， 其特征在于， 上 述芯片上芯片封装件结构包括一个或多个子 IC芯片； 子 [C芯片与子 IC芯片 之间通过粘贴材料或者隔片连接。  2. The on-chip chip package structure according to claim 1, wherein the on-chip chip package structure comprises one or more sub-IC chips; and the sub-C chip and the sub-IC chip pass the bonding material. Or a septum connection. 3、 根据权利要求 1所述的一种芯片上芯片封装件结构， 其特征在于， 上 述引线框架具有多个围绕芯片载体呈多圈排列的引脚， 引脚横截面形状为圆 形或矩形， 排列圈数为单圈、 双圈， 三圈或三圈以上。  3. The chip-on-chip package structure according to claim 1, wherein the lead frame has a plurality of pins arranged in a plurality of circles around the chip carrier, and the cross-sectional shape of the pins is circular or rectangular. The number of laps is single, double, three or more. 4、 根据权利要求 1所述的一种芯片上芯片封装件结构， 其特征在于， 芯 片载体每边的多圈引脚排列方式为平行排列或交错排列。  4. The on-chip chip package structure according to claim 1, wherein the plurality of turns of the pins on each side of the chip carrier are arranged in parallel or staggered. 5、 根据权利要求 1所述的一种芯片上芯片封装件结构的制造方法， 其特 配置掩膜村料层，在薄板基材的上表面和下表面配置具有窗口的掩膜村料 层图形； 5. The method of fabricating a chip-on-chip package structure according to claim 1, wherein Configuring a masking village layer, and arranging a mask layer pattern having a window on the upper surface and the lower surface of the sheet substrate; 配置第一金属材料层和第二金属材料层，在配置于薄板基材上表面和下表 面的掩膜材料层的窗口中分别配置第一金属材料层和第二金属材料层；  Disposing a first metal material layer and a second metal material layer, respectively disposing a first metal material layer and a second metal material layer in a window disposed on the upper surface of the thin plate substrate and the mask material layer on the lower surface; 下表面选择性部分蚀刻， 移除薄板基材下表面的掩膜材料层， 以第二金属 材料层为抗蚀层， 对薄板基材下表面进行选择性部分蚀刻， 形成凹槽；  The lower surface is selectively partially etched, the mask material layer on the lower surface of the thin plate substrate is removed, and the second metal material layer is used as a resist layer, and the lower surface of the thin plate substrate is selectively partially etched to form a groove; 配置绝缘填充材料，在薄板基村下表面经选择性部分蚀刻形成的凹槽中填 充绝缘材料；  The insulating filling material is disposed, and the insulating material is filled in the groove formed by selective partial etching on the lower surface of the thin plate base; 上表面选择性部分蚀刻， 移除薄板基材上表面的掩膜材料层， 以第一金属 材料层为阻蚀层， 对薄板基材上表面进行选择性部分烛刻， 形成具有台阶式 结构的引线框架， 包括分离的芯片载体和多圈引脚；  The upper surface is selectively partially etched, the mask material layer on the upper surface of the thin plate substrate is removed, and the first metal material layer is used as a resist layer, and the upper surface of the thin plate substrate is selectively partially candle-cut to form a stepped structure. a lead frame comprising a separate chip carrier and a multi-turn pin; 配置母 IC芯片，通过粘贴材料将母 IC芯片配置于引线框架上表面的第一 金属材料层位置， ϋ固定于芯片载体的中央部位；  Configuring the mother IC chip, arranging the mother IC chip on the upper surface of the lead metal frame by the bonding material, and fixing it to the central portion of the chip carrier; 配置子 IC芯片，将子 IC芯片通过粘贴材料配置于母 IC芯片的有缘面上, 或在母 IC芯片的有缘面上配置隔片， 将子 IC芯片配置于隔片上；  Configuring the sub-IC chip, disposing the sub-IC chip on the edge of the mother IC chip through the bonding material, or arranging the spacer on the edge surface of the mother IC chip, and arranging the sub-IC chip on the spacer; 金属导线键合连接，母 IC芯片和子 IC芯片上的多个键合焊盘通过金属导 线分别连接至配置有第一金属材料层的多个引脚的内引脚；  Metal wire bonding connection, a plurality of bonding pads on the mother IC chip and the sub IC chip are respectively connected to the inner pins of the plurality of pins configured with the first metal material layer through the metal wires; 形成塑封体， 用塑封材料包覆母 IC芯片、 子 IC芯片、 金属导线、 粘贴材 料、 引线框架和第一金属材料层， 形成封装件， 或者包覆母 IC 芯片、 子 芯片、 金属导线、 隔片、 引线框架和第一金属材料层， 形成封装件， 或者包 覆母 芯片、 子]C芯片、 金属导线、 隔片、 引线框架和第一金属材料层， 形成封装件；  Forming a plastic body, covering the mother IC chip, the sub IC chip, the metal wire, the bonding material, the lead frame and the first metal material layer with a plastic sealing material to form a package, or covering the mother IC chip, the chip, the metal wire, and the spacer a sheet, a lead frame and a first metal material layer, forming a package, or coating a mother chip, a sub-C chip, a metal wire, a spacer, a lead frame and a first metal material layer to form a package; 切割分离形成单个封装件， 切割分离形成独立的单个封装件。  The dicing is separated to form a single package, and the dicing is separated to form a single individual package. 6、 根据权利要求 5所述的方法， 其特征在于， 经该蚀刻形成的分离的芯 片载体和多圈引脚由绝缘填充材料连接固定。  6. The method of claim 5 wherein the separated chip carrier and the multi-turn pins formed by the etching are joined by an insulating filler material. 7、 根据权利要求 5所述的方法， 其特征在于， 切割分离形成单个封装件， 是用刀片切割、 激光切割或者水刀切割方法切割， 且仅切割塑封材料和绝缘 填充材料。  7. The method according to claim 5, wherein the cutting is separated to form a single package, which is cut by a blade cutting, laser cutting or water jet cutting method, and only the molding material and the insulating filling material are cut.
PCT/CN2012/085782 2011-12-30 2012-12-04 Chip on chip package and manufacturing method Ceased WO2013097580A1 (en)

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