WO2013095010A1

WO2013095010A1 - Manufacturing method of back contact solar cell

Info

Publication number: WO2013095010A1
Application number: PCT/KR2012/011179
Authority: WO
Inventors: Woo Won Jung; Jae Eock Cho; Hong Gu Lee; Se-Young Seo; Deoc Hwan Hyun; Yong Hwa Lee; Gang II KIM
Original assignee: Hanwha Chemical Corp
Current assignee: Hanwha Chemical Corp
Priority date: 2011-12-23
Filing date: 2012-12-20
Publication date: 2013-06-27
Anticipated expiration: 2014-06-23

Abstract

Provided is a manufacturing method of a back contact solar cell, the method including: a) forming a via hole to pass through two opposing surfaces of a semiconductor substrate of a first conductive type; b) doping an impurity of a second conductive type into surfaces of the semiconductor substrate to form layers of a second conductive type; c) forming an etching-resist pattern on one of the two opposing surfaces to cover an opening portion of the via hole; d) selectively etching one surface of the semiconductor substrate using the etching-resist pattern as an etching mask, to thereby remove a portion of the layer of a second conductive type present on one surface of the semiconductor substrate on which the etching-resist pattern is not formed; and e) partially etching the layer of a second conductive type present on the other surface of the semiconductor substrate, which is opposite to one surface of the semiconductor substrate, to thereby control a concentration of the impurity in the layer of a second conductive type present on the other surface of the semiconductor substrate.

Description

Title of Invention: MANUFACTURING METHOD OF BACK

CONTACT SOLAR CELL

Technical Field

[1] The following disclosure relates to a manufacturing method of a back contact solar cell, and in particular, to a manufacturing method of a back contact solar cell allowing a light receiving surface and a back surface, which is an opposite surface to the light receiving surface, to have different sheet resistances, by a simple doping process, and having high short current, open voltage, and fidelity to thereby exhibit excellent photovoltaic conversion efficiency.

Background Art

[2] The problems, such as, high-flying oil costs, global environmental problems,

depletion of fossil fuels, waste disposal of nuclear power generation, and positioning of new generation stations due to construction thereof, and the like are throwing the current spotlight on the renewable energy. In particular, solar cells, which are non- polluting energy sources, are actively being researched and developed.

[3] The solar cell is a device that converts light energy into electric energy by using photovoltaic effect, and has advantages of non-polluting energy, indefinite resources, and semi-permanent lifespan, and the like. In addition, the solar energy is expected to be used as an energy source that can ultimately solve energy problems for humans without considering environmental problems.

[4] Among the solar cells, crystalline silicon solar cells are classified into silicon solar cells, thin film solar cells, dye-sensitized solar cells, and organic polymer solar cells, according to the constituent material. Since the crystalline solar cells count for most of the total global output of solar cells, has higher efficiency than other type batteries, and have been continuously developed to lower manufacturing costs thereof, they are the most popular solar cells.

[5] As disclosed in Korean Patent Laid-Open Publication No. 2007-0004671, an emitter wrap through (EWT) structure of back contact silicon solar cell has several advantages as compared with general silicon solar cells. The first advantage is that a back contact solar cell has high conversion efficiency by allowing a contact to remove the reduction in the light receiving area (contact shadowing losses). The second advantage is that since both of two contacts are on the same surface, the back contact solar cell is more easily assembled in an electric circuit, and thus can be produced at even lower manufacturing unit cost at the time of manufacturing the modules. The third advantage is that the existing back contact silicon solar cells (interdigitated back contact) are manu- factured in an n-type substrate having long electron lifespan, but recently, may be manufactured also in a p-type substrate having low manufacturing unit cost by forming holes for moving electrons therethrough in the substrate, thereby lowering manufacturing unit cost.

[6] There are several approaches for manufacturing the back contact silicon solar cells.

Among these approaches, in a metallization wrap through (MWT) solar cell, an inside of the hole and a back contact are connected by an electrode in order to manufacture a back contact cell. The distinctive feature of the back contact solar cell as compared with the MWT solar cell is that an inside of a hole and a back contact are connected with each other by an emitter to allow movement of electrons. These conductive channels may be formed by generating holes in a silicon substrate using a laser and then forming emitters on front and back surfaces and forming an emitter inside of the hole. The back contact solar cell has all anode and cathode collection junctions in the back surface thereof. Since the light is mostly absorbed near the front surface thereof, a back junction battery is requested to have very high material characteristics so as to secure enough time for carriers to perform collection junction on the back surface and diffuse from the front surface to the back surface.

[7] In the case of a solar cell having a back contact structure, respective sheet resistances of the light receiving surface and thee back surface need to be precisely controlled in order to reduce surface recombination and facilitate electron movement. Therefore, a multistage doping process or an etching process using a mask is employed. However, these methods of the prior art cause long processing time and complicated stage, which may block improvement of productivity.

[8] [Related Art Document]

[9] [Patent Document]

[ 10] (Patent Document 1 ) Korean Patent Laid-Open Publication No. 2007-0004671

Disclosure of Invention

Technical Problem

[1 1] An embodiment of the present invention is directed to providing a manufacturing method of a back contact solar cell having high short current, open voltage, and fidelity, through a single doping process to thereby exhibit excellent photovoltaic conversion efficiency; a manufacturing method of a back contact solar cell capable of preventing generation of leakage current at the time of forming electrodes; and a manufacturing method of a back contact solar cell capable of decreasing the number of process stages and reducing the manufacturing time to thereby achieve cost reduction and high productivity.

Solution to Problem [12] In one general aspect, a manufacturing method of a back contact solar cell, the method includes: a) forming a via hole to pass through two opposing surfaces of a semiconductor substrate of a first conductive type; b) doping an impurity of a second conductive type into surfaces of the semiconductor substrate to form layers of a second conductive type; c) forming an etching-resist pattern on one of the two opposing surfaces to cover an opening portion of the via hole; d) selectively etching one surface of the semiconductor substrate using the etching-resist pattern as an etching mask, to thereby remove a portion of the layer of a second conductive type present on one surface of the semiconductor substrate on which the etching-resist pattern is not formed; and e) partially etching the layer of a second conductive type present on the other surface of the semiconductor substrate, which is opposite to one surface of the semiconductor substrate, to thereby control a concentration of the impurity in the layer of a second conductive type present on the other surface of the semiconductor substrate.

[13] The method may further include: f) forming dielectric layers by forming a passivation film on one surface of the semiconductor substrate and an anti-reflection film on the other surface of the semiconductor substrate; g) partially removing the passivation film by partially coating an etching paste for etching the passivation film on one surface, to thereby expose a region of the semiconductor substrate, from which the layer of a second conductive type is removed by the selective etching; and h) forming electrodes by forming, on one surface, a first electrode connected with the exposed region of the semiconductor substrate and a second electrode connected with layer of a second conductive type through punch-through.

[14] Here, a surface step height may be formed between a surface of the semiconductor substrate, which is exposed by removing the layer of a second conductive type due to the selective etching, and the layer of a second conductive type below the etching- resist pattern, and the surface step height may be 1 to 15^m.

[15] The layer of a second conductive type formed in the doping may have a sheet resistance of 10~40Q/sq., and in the partial etching, the layer of a second conductive type formed on the other surface of the semiconductor substrate may be partially removed so as to have a sheet resistance of 30~150Q/sq.

[16] The partial etching may be carried out by dry etching.

[17] Hear, a thickness of the layer of a second conductive type formed on an inner surface of the via hole may be controlled by the partial etching.

[18] The thickness of the layer of a second conductive type formed on an inner surface of the via hole may be reduced from one surface of the semiconductor substrate toward the other surface of the semiconductor substrate by the partial etching.

[19] The method may further include, after the partial etching, performing a washing process using a radio corporation of America (RCA) washing method.

[20] The etching-resist pattern may be formed by a printing process, and the printing

process may include screen printing.

[21] In another general aspect, a back contact solar cell is manufactured by the foregoing method.

Advantageous Effects of Invention

[22] As set forth above, the solar cell manufactured by the manufacturing method of the present invention can have high short current, open voltage, and fidelity, through a single doping process to thereby exhibit excellent photovoltaic conversion efficiency; prevent generation of leakage current at the time of forming electrodes; and decrease the number of process stages and reduce the manufacturing time to thereby achieve cost reduction and high productivity.

Brief Description of Drawings

[23] FIG. 1 is a process view showing a manufacturing method of a back contact solar cell according to an embodiment of the present invention;

[24] FIG. 2 is a scanning electron microscope (SEM) image obtained by observing a cross section of a via hole when partial etching is performed using dry etching, in the manufacturing method according to the embodiment of the present invention; and

[25] FIG. 3 is a process view showing a manufacturing method of a back contact solar cell according to another embodiment of the present invention.

[26] [Detailed Description of Main Elements]

[27] 100: semiconductor substrate of first conductive type

[28] 1: via hole

[29] 210: back emitter layer 21 1 : patterned back emitter layer

[30] 220: front emitter layer

[31] 221 : front emitter layer having controlled doping concentration

[32] 230: via hole emitter layer 300: etching-resist pattern

[33] 400: antireflection film 500: passivation film

[34] 510: etched passivation film

[35] 600: p-type electrode (first electrode)

[36] 610: back surface field (BSF)

[37] 700: n-type electrode (second electrode)

[38] 710: 2-1 electrode before heat treatment

[39] 711: 2-1 electrode after punch through

[40] 720: 2-2 electrode

Best Mode for Carrying out the Invention

Hereinafter, a manufacturing method of the present invention will be described detail with reference to the accompanying drawings. The drawings shown below are provided by way of examples so that the spirit of the present invention can be sufficiently transferred to those skilled in the art to which the present invention pertains. Therefore, the prevent invention is not limited to the drawings set forth below, and may be embodied in different forms, and the drawings set forth below may be exaggerated in order to clarify the spirit of the present invention. Also, the same reference numerals denote the same elements throughout the specification.

[42] Here, unless indicated otherwise, the terms used in the specification including

technical and scientific terms have the same meaning as those that are usually understood by those who skilled in the art to which the present invention pertains, and detailed description of the known functions and constitutions that may obscure the gist of the present invention will be omitted.

[43] A manufacturing method of a back contact solar cell according to the present

invention may include: doping an impurity of a second conductive type into surfaces of a semiconductor substrate of a first conductive type, a via hole being formed to pass through two opposing surfaces of the semiconductor substrate; forming an etching- resist pattern on one surface of the two opposing surfaces to cover an opening portion of the via hole; and selectively etching one surface of the semiconductor substrate using the etching-resist pattern as an etching mask, to thereby remove a portion of the layer of a second conductive type exposed on one surface of the semiconductor substrate.

[44] Specifically, a manufacturing method of a back contact solar cell according to the present invention may include: a) forming a via hole to pass through two opposing surfaces of a semiconductor substrate of a first conductive type; b) forming layers of a second conductive type by doping an impurity of a second conductive type into surfaces of the semiconductor substrate; c) forming an etching-resist pattern on one of the two opposing surfaces to cover an opening portion of the via hole; d) selectively etching one surface of the semiconductor substrate using the etching-resist pattern as an etching mask, to thereby remove a portion of the layer of a second conductive type present on one surface of the semiconductor substrate, on which the etching-resist pattern is not formed; and e) partially etching the layer of a second conductive type present on the other surface of the semiconductor substrate, which is opposite to one surface of the semiconductor substrate, to thereby control a concentration of the impurity in the layer of a second conductive type present on the other surface of the semiconductor substrate.

[45] FIG, 1 is a process view showing a manufacturing method of a back contact solar cell according to an embodiment of the present invention. As shown in FIG. 1, the manufacturing method according to an embodiment of the present invention, may include: forming a via hole 1 to pass through two opposing surfaces of a semiconductor substrate 100 of a first conductive type; allowing an impurity of a second conductive type to be diffused into surfaces of the semiconductor substrate 100 including the two opposing surfaces of the semiconductor substrate and an inner surface of the via hole, to thereby form layers of a second conductive type 210, 220, and 230 on the two opposing surfaces of the semiconductor substrate and the inner surface of the via hole 1 ; coating an etching-resist on at least one of the two opposing surfaces to cover an opening portion of the via hole 1 to form an etching-resist pattern 300; selectively etching one surface of the semiconductor substrate using the etching-resist pattern 300 as an etching mask, to thereby remove a portion of the layer of a second conductive type present on one surface of the semiconductor substrate, on which the etching-resist pattern 300 is not formed; and partially etching the layer of a second conductive type present on the other surface of the semiconductor substrate, which is opposite to one surface of the semiconductor substrate, in a depth direction (in a direction of the shortest straight line connecting the two opposing surfaces), to thereby control a concentration of the impurity in the layer of a second conductive type present on the other surface of the semiconductor substrate.

[46] The first conductive type means p-type conductivity or n-type conductivity, and the second conductive type means to have conductivity complementary to the first conductive type. Hereinafter, the present invention will be described by using the first conductive type as p-type conductivity and the second conductive type as n-type conductivity, but the technical scope of the present invention is of course maintained even when the first conductive type is n-type conductivity and the second conductive type is p-type conductivity.

[47] The first conductive type may mean p-type conductivity due to a p-type impurity, and the second conductive type may mean n-type conductivity due to an n-type impurity which is an impurity complementary to the p-type impurity. Here, the p-type impurity may include an impurity that is doped in a semiconductor substrate to provide holes, and the n-type impurity may include an impurity that is doped in a semiconductor substrate to provide electrons. When silicon semiconductor is exemplified, the p-type impurity may be one or two or more selected from aluminum, boron, and indium, and the n-type impurity may be one or two or more selected from arsenic and phosphorous.

[48] Examples of the semiconductor substrate 100 may include a Group IV semiconductor substrate including silicon (Si), germanium (Ge), or silicon germanium (SiGe); a Group III-V semiconductor substrate including gallium arsenic (GaAs), indium phosphide (InP), or gallium phosphide (GaP); a Group II- VI semiconductor substrate including cadmium sulfide (CdS) or zinc telluride (ZnTe); and a Group IV- VI semiconductor substrate including lead sulfide (PbS). Crystallographically, examples of the semiconductor substrate 100 may include mono-crystalline, polycrystalline, and amorphous crystalline substrate.

[49] The forming of the via hole (step (a)) may include forming the via hole 1 to pass through the two opposing surfaces of the semiconductor substrate 100, for example, a light receiving surface receiving a solar light and a back surface which is an opposite surface to the light receiving surface.

[50] The forming of the via hole (step (a)) may be carried out by using laser drilling, and the via hole may be formed by other methods such as dry etching, wet etching, mechanical drilling, water-jet machining, and the like. In the case of using the laser drilling, the laser preferably has sufficient power or intensity at an operation wavelength so that the holes can be formed within the shortest time period such as 0.5 ms to 5 ms per hole. For example, an Nd:YAG laser may be used in the laser drilling. In the forming of the via hole (step (a)), the formed via hole 1 may have a diameter of, for example, 25 to 125 ιη, and preferably 30 to 60 ^ra.

[51] In the forming of the via hole (step (a)), a plurality of via holes 1 may be formed in the semiconductor substrate 100 such that they are spaced apart from each other.

Specifically, based on the opening portion of the via hole 1 exposed on one of the two opposing surfaces, a plurality of via holes may be regularly spaced apart from each other such that an MxN matrix is composed of M opening portions of via holes 1 in a first direction and N opening portions of via holes 1 in a second direction. Here, the first direction and the second direction belong in the same plane (a surface of the semiconductor substrate), and the first direction and the second direction may have a predetermined angle including 90°.

[52] According to essential spirit of the present invention, a photocurrent movement path having a low sheet resistance in the solar cell is formed, resulting in reducing density of the via holes 1 (the number of via holes per surface area of the semiconductor substrate), and thus the light active area for receiving the light per area of the semiconductor substrate can be maximized. As a substantial example, the density of via holes 1 may be 0.25 to 0.5/mm².

[53] Since the forming of the via hole (step (a)) carried out by the laser drilling may give thermal damage to the semiconductor substrate 100, an etching process for removing a damaged region (damage removal etching) may be further carried out after the forming of the via hole (step (a)).

[54] The etching process for removing the damaged region at the time of forming the via hole may be a process generally adopted in a semiconductor process. For example, the etching process for the damaged region, such as burr on the surface, may be carried out by using an alkaline etching solution. As a substantial example, the etching process may be carried out at a temperature of 80~90°C by using sodium hydroxide or potassium hydroxide.

[55] The forming of the via hole (step (a)) allows a plurality of via holes 1 to be spaced apart from each other in the semiconductor substrate 100. After that, the doping (step (b)) may be carried out to dope the impurity of a second conductive type into the semiconductor substrate.

[56] In the doping (step (b)), the impurity of a second conductive type is doped into the surfaces of the semiconductor substrate 100 including the two opposing surfaces of the semiconductor substrate and an inner surface of the via hole, thereby forming surface doping layers where the impurity of a second conductive type is doped into the surfaces of the semiconductor substrate 100.

[57] In the doping (step (b)), the layers of a second conductive type 210, 220, and 230 are formed by doping the impurity of a second conductive type into the surfaces of the semiconductor substrate 100 including the two opposing surfaces of the semiconductor substrate 100 and the surface (the inner surface) of the via hole 1 as the surface doping layers. Hereinafter, the layer of a second conductive type formed on one surface of the two opposing surfaces of the semiconductor substrate 100 is referred to as a front emitter layer 220; the layer of a second conductive type formed on the surface of the via hole 1 is referred to as a via hole emitter layer 230; and the layer of a second conductive type formed on the other surface of the two opposing surfaces of the semiconductor substrate 100 is referred to as a back emitter layer 210.

[58] The doping (step (b)) may be carried out by subjecting the semiconductor substrate 100 to heat treatment in the presence of gas containing an impurity of a second conductive type, or using a solid phase source containing an impurity of a second conductive type or a spray on diffusion type source. For example, the impurity of a second conductive type, which is at least material selected from gas phase POCl₃, P₂0₅ and PH₃, is supplied in a mixture with a carrier gas of an inactive gas. The semiconductor substrate 100 is subjected to heat treatment at a temperature of 800°C to 900°C for 10 to 60 minutes, so that the impurity of a second conductive type can be doped into the semiconductor substrate 100. Here, a process for removing an impurity film, such as phosphosilicate glass, generated due to the doping and heat treatment, may be further carried out by using an HF etching solution.

[59] In the doping (step (b)) as described above, the layers of a second conductive type including the front emitter layer 220, the via hole emitter layer 230, and the back emitter layer 210 are formed. In the doping (step (b)), the layers of a second

conductive type may have a sheet resistance of 10~40Q/sq.

[60] Here, in the doping (step (b)), a process of appropriately sealing a lateral surface of the semiconductor substrate 100, that is, a surface parallel with the via hole to allow the surface to be not doped with the impurity of a second conductive type or removing the layer of a second conductive type formed on the lateral surface of the semiconductor substrate 100 may be further carried out.

[61] In the forming of the etching-resist pattern (step (c)), the etching-resist pattern 300 may be formed on one of the opposing surfaces of the semiconductor substrate 100 through which the via hole 1 passes, to cover the opening portion of the via hole 1.

[62] Specifically, the etching-resist pattern 300 may be formed on the surface of the semiconductor substrate 100 on which the back emitter layer 210 is formed, and the etching-resist pattern 300 may have a shape corresponding to an n-type electrode which is electrically connected with the via hole emitter layer 230.

[63] As the etching-resist paste, any material that can be physicochemically stable at the time of etching the semiconductor substrate may be used, and any material that can have corrosion resistance against to an alkaline or acidic etching solution. As the etching-resist paste, for example a commercial product containing SGC-2500 (Seoul Chemical Research Laboratory Company) may be used. The etching-resist paste is preferably coated by using a printing method such as inkjet printing, masking, stencil printing, or screen printing. The etching-resist paste is directly printed, thereby simplifying process conditions, reducing the production time and the manufacturing cost, and increasing the production yield.

[64] The etching-resist pattern 300 may be formed by coating the etching resist paste to have a plurality of band shapes covering the opening portions of the via holes 1. The plurality of band shapes may correspond to a shape of the n-type electrode having a fish-bone structure or a comb structure.

[65] Specifically, the etching-resist pattern 300 formed by coating the etching-resist paste may include a plurality of band (etching resist band) shaped patterns covering the opening portions of the via holes 1 , which are exposed on the surface of the semiconductor substrate 100 on which the back emitter layers 210 are formed.

[66] More specifically, when, based on the opening portion of the via hole 1 positioned on the surface of the semiconductor substrate 100 on which the back emitter layer 210 is formed, a plurality of via holes 1 are formed such that M (M is an integer of M>1) opening portions of via holes 1 in a first direction and N (N is an integer of N >1) opening portions of via holes 1 in a second direction are regularly spaced apart from each other, the etching-resist pattern 300 may include a plurality of bands spaced apart in parallel with each other in the first direction and the bands (etching-resist bands) may cover all the opening portions of the plurality of via holes 1 positioned on the same line in the second direction.

[67] Here, the etching-resist band of the etching-resist pattern 300 may have a width of three to six times the diameter of the opening portion of the via hole 1. [68] After the forming of the etching-resist pattern 300 (step (c)), the selective etching (step (d)) may be carried out on the surface of the semiconductor substrate 100 on which the back emitter layer 210 is formed by using the etching-resist pattern 300 as an etching mask. Specifically, a portion of the back emitter layer 210, on which the etching-resist pattern 300 is not formed, may be removed by the selective etching (step (d)).

[69] In the selective etching (step (d)), the back emitter layer 210 is patterned by

removing a portion of the back emitter layer 210, which is formed on the rest surface region except a predetermined surface region adjacent to the opening portion of the via hole 1. The portion of the back emitter layer 210 present in a region where the etching- resist pattern 300 is not formed, may be removed by controlling the depth for etching in the selective etching (step (d)).

[70] In the selective etching (step (d)), the surface of the semiconductor substrate on

which the back emitter layer 210 is formed is etched by a predetermined depth, and thus, the portion of the back emitter layer 210 present in a region where the etching- resist pattern 300 is not formed may be removed by controlling the etching time in the selective etching. After the selective etching (step (d)), the etching-resist pattern 300 may be of course removed. After removing the etching-resist pattern, a process of washing the semiconductor substrate in a mixture solution where ammonia water, peroxide, and water may be further carried out.

[71] Through the selective etching (step (d)), the back emitter layer 210 may be patterned to have a shape corresponding to the etching-resist pattern 300.

[72] Specifically, when, based on the opening portion of the via hole 1 positioned on the surface of the semiconductor substrate on which the back emitter layer 210 is formed, a plurality of via holes 1 may be formed that M (M is an integer of M>1) opening portions of via holes 1 in a first direction and N (N is an integer of N>1) opening portions of via holes 1 in a second direction are regularly spaced apart in parallel with each other, a patterned back emitter layer 211 patterned by the selective etching (step (d)) may have a plurality of band shapes spaced apart in parallel with each other in the first direction and the surface doping layer of a second conductive type having a single band shape is positioned on the extension line connecting the opening portions of the plurality of via holes 1 positioned on the same line in the second direction.

[73] That is, by the selective etching (step (d)), the surface doping layer of a second

conductive type is selectively formed at a region where the n-type electrode (n-type finger electrodes) positioned on the back surface of the back contact solar cell is formed.

[74] Here, the etching-resist pattern 300 may have a pattern where a plurality of band shapes covering all the opening portions of the plurality of via holes 1 positioned on the same line are spaced apart from each other, and may further include other band shapes crossing the plurality of bands spaced apart from each other.

[75] That is, the etching-resist pattern 300 may include a pattern formed by coating an etching resist to have a shape and a place corresponding to a shape and a place of the n-type finger electrode of the back contact solar cell, and may include a pattern formed by coating an etching resist to have a shape or a place corresponding to a shape and a place of an n-type bus bar electrode connecting the n-type finger electrodes together with the pattern corresponding to the n-type finger electrodes.

[76] Therefore, the surface doping layer of a second conductive type (the patterned back emitter layer 21 1) may be selectively formed on the surface of the semiconductor substrate at a region where the n-type finger electrode is formed and a region where the n-type bus bar electrode is formed.

[77] By the selective etching (step (d)), a surface step height may be formed in one

surface of the semiconductor substrate 100, that is, the back surface of the semiconductor substrate 100.

[78] That is, the surface step height may be formed between the patterned back emitter layer 211 and a region of the p-type semiconductor substrate, which is exposed by the etching made due to the non-formation of the etching-resist pattern 300.

[79] The back emitter layer 210 is patterned to have a shape and a place corresponding to a shape and a place of the n-type finger electrodes (and the n-type bus bar electrode) by carrying out the selective etching (step (d)), and a surface step height is formed in the back surface of the semiconductor substrate 100, so that leakage current can be prevented from being generated and fidelity can be improved.

[80] The selective etching (step (d)) may be earned out by using wet etching or dry

etching, and the wet etching may employ a general etching solution of nitric acid, hydrofluoric acid, or acetic acid. In the case where the wet etching is used for the selective etching (step (d)), one surface of the semiconductor substrate (one surface on which the back emitter layer is formed) is immersed in the etching solution and the immersing time of one surface thereof is regulated, so that the etched depth can be of course controlled. Even in the case of the dry etching, the etched depth can be of course controlled by controlling the etching time.

[81] After the selective etching (step (d)), the partial etching (step (e)) is carried out so that the surface of the semiconductor substrate 100 on which the front emitter layer 220 is formed, is etched by a predetermined depth. While the impurity of a second conductive type is heavily doped into the surfaces of the semiconductor substrate in the doping (step (b)), the front emitter layer 220 is removed by a predetermined depth in the partial etching (step (e)), thereby controlling the doping concentration of the impurity of a second conductive type of the front emitter layer 220.

I [82] As the etching of the front emitter layer 220 is carried out, the concentration of the impurity of a second conductive type remaining in the surface thereof is decreased, and thus the sheet resistance of the front emitter layer 220 is increased. As the sheet resistance of the front emitter layer 220 is increased, surface re-coupling is reduced. For this reason, the collecting efficiency of carriers generated by short-wavelength light is increased, and thus, short current density and open voltage are increased, resulting in increasing conversion efficiency of the solar cell. Here, the partial etching (step (e)) may be carried out such that the front emitter layer 220 has a sheet resistance of 30~ 150Q/sq.

[83] The partial etching (step (e)) may be carried out by dry etching. That is, in the partial etching (step (e)), etching may be carried out by dry etching having directivity at the time of etching, and the dry etching may include plasma etching.

[84] As the partial etching (step (e)) is earned out by dry etching having directivity, the concentration of impurity of the via hole emitter layer 230, which is adjacent to the front emitter layer 220, may also be regulated, together with the front emitter layer 220, and thus the short current density, open voltage, and fidelity can be more improved.

[85] Specifically, the surface of the semiconductor substrate 100, on which the front

emitter layer 220 is formed, is etched by a predetermined depth, using dry etching having directivity, so that the thickness of the via hole emitter layer 230 formed on the inner surface of the via hole can be also regulated. That is, through the partial etching (step (e)), the thickness of the via hole emitter layer 230 formed on the inner surface of the via hole 1 may be decreased from the back surface of the semiconductor substrate 100 toward the light receiving surface of the semiconductor substrate 100, and the thickness of the via hole emitter layer 230 may be continuously decreased from the back surface of the semiconductor substrate 100 toward the light receiving surface of the semiconductor substrate 100.

[86] More specifically, in the case where the surface of the semiconductor substrate 100, on which the front emitter layer 220 is formed, is dry etched, the via hole emitter layer 230 may be also etched through the opening portion of the via hole 1 due to etching directivity. As the drying etching has straight directivity, more etching is done closer to the front emitter layer 220, and thus, the concentration of impurity of a second conductive type in a portion of the via hole emitter layer 230, which is adjacent to the front emitter layer 220, may be controlled to have a similar resistance to the front emitter layer, and a portion of the via hole emitter layer 230, which is adjacent to the back emitter layer 210, may have a low resistance due to the heavy doping in the doping (step (b)).

[87] FIG. 2 is a scanning electron microscope (SEM) image obtained by observing a cross section of the via hole when the partial etching is performed using plasma etching. In FIG. 2, the term "front surface" means the light receiving surface and the term "rear surface" means the back surface. P1-P5 represent regions analyzed by using an energy dispersive spectroscopy (EDS) equipped at the scanning electron microscope (SEM). Each of numerals (mm) positioned below P1~P5 shows p-n junction depth, that is, thickness of the via hole emitter layer for each region.

[88] As shown in FIG. 2, it can be seen that, in the case where the front emitter layer 220 is etched by a predetermined depth through dry etching in order to control the resistance of the front emitter layer 220 of the light receiving surface, the p-n junction depth between the via hole emitter layer and the substrate is thinner from the back surface toward the light receiving surface. This results from straight directivity of etching at the time of dry etching, and it can be seen that the depth of the via hole emitter layer is gradually thinner from the back surface toward the light receiving surface due to dry etching.

[89] In the case of a solar cell manufactured by forming via holes with a diameter of 75 ΐη in a p-type semiconductor substrate with a thickness of 150~180/ m at density of 58/cm 2, forming layers of a second conductive type having a resistance of 25Q/sq. in surfaces of the semiconductor substrate through doping of a p-type impurity, carrying out an etching-resist forming process and a selective etching process to pattern a back emitter layer to have a fishbone structure of 1-2 mm width, and carrying out plasma etching on a light receiving surface of the semiconductor substrate to allow a front emitter layer to have a resistance of 47Q/sq., the thus manufactured solar cell had short current density (Jsc) of 40.59 mA/cm², an open voltage (Voc) of 0.628V, a fill factor (FF) of 0.721%, and an energy conversion efficiency (η) of 18.37%. In the case of a solar cell manufactured by wet etching a light receiving surface to have the same resistance of 47Q/sq., the thus manufactured solar cell had short current density (Jsc) of 40.58 mA/ cm², an open voltage (Voc) of 0.623V, a fill factor (FF) of 0.676%, and an energy conversion efficiency (η) of 17.1%. In the case of a solar cell manufactured by not etching a light receiving surface to have a resistance of 25Q/sq., the thus manufactured solar cell had short current density (Jsc) of 37.06 mA/cm², an open voltage (Voc) of 0.61 IV, a fill factor (FF) of 0.752%, and an energy conversion efficiency (η) of 17.03%.

[90] As described above, the open voltage and short current density can be improved by controlling the resistance of the front emitter layer, and in addition, fidelity can be further improved by controlling the resistance of the front emitter layer using dry etching.

[91] In the partial etching (step (e)), a washing process using a radio corporation of

America (RCA) washing method may be further carried out after dry etching is carried out. Specifically, according to the RCA washing method used to wash a substrate in a semiconductor field, oxide and metal impurities are moved by using a chemical solution combination including sulfuric acid (H₂S0 ), hydrochloric acid (HCI), ammonium hydroxide (NH₄OH), hydrofluoric acid (HF), and peroxide (H₂0₂). The washing may be earned out by using a general RCA washing method. Here, at the time of washing using the RCA washing method, SC-1 washing may be carried out, and subsequently SC-2 washing may be carried out.

[92] As described above, in the manufacturing method according to the present invention, the surface doping layers of a second conductive type are uniformly formed on the two opposing surfaces of the semiconductor substrate and the inner surface of the via hole through the doping (step (b)); the portion of the doping layer, on which the etching- resist pattern 300 is not formed, is etched and removed to locally form a high- concentration emitter layer in only a forming region of the n-type electrode (finger electrode and bus bar electrode) by using the selective etching (step (d)); and a front emitter layer 221 is formed with a doping concentration controlled by using the partial etching (step (e)).

[93] In the manufacturing method according to an embodiment of the present invention, after carrying out the partial etching (step (e)), preferably, the washing process, forming of dielectric films (step f) may be further carried out by forming a passivation film 500 on one surface of the semiconductor substrate and an antireflection film 400 on the other surface of the semiconductor substrate.

[94] Specifically, after controlling the concentration of impurity of a second conductive type in the front emitter layer 220 through the partial etching (step (e)), forming of the dielectric films (step (f)) may be carried out by forming the antireflection film 400 on the front emitter layer and the passivation film 500 on one surface of the semiconductor substrate on which the patterned back emitter layer 211 is formed.

[95] The antireflection film 400 formed on one surface of the semiconductor substrate 100 on which the front emitter layer 220 is formed means a film that does both of roles of preventing the light received into the solar cell from again escaping out of the solar cell and passivating a surface defect acting as an electron trap site in the surface of the semiconductor substrate 100.

[96] The antireflection film 400 may be a single layer thin film in the case where the reflection preventing action and the passivating action are done by a single material. The antireflection film 400 may be a multilayer thin film where different material layers are stacked in the case where the reflection preventing action and the passivating action are done by different materials.

[97] Alternatively, even in the case where the reflection preventing action and the passivating action are done by a single material, the antireflection film 400 may be a multilayer thin film where different material layers are stacked, in order to maximize the reflection preventing action and effectively passivate the defect.

[98] For example, the antireflection film 400 may be a single film of at least one selected from semiconductor oxide, semiconductor nitride, semiconductor oxide containing nitrogen, semiconductor nitride containing hydrogen, A1₂0₃, MgF₂, ZnS, MgF₂, Ti0₂, and Ce0₂, or a multilayer thin film where films of at least two selected therefrom are stacked.

[99] As an example of the silicon solar cell, a single film type antireflection film 400 may be a silicon nitride film, a silicon nitride film or containing hydrogen, or a silicon oxynitride film, and a multilayer thin film type antireflection film 400 may include a stacked thin film where films of at least two selected from silicon oxide, silicon nitride, A1₂0₃, MgF₂, ZnS, MgF₂, Ti0₂, and Ce0₂ are stacked.

[100] The passivation film 500 formed on the other surface of the semiconductor substrate, on which the patterned back emitter layer 211 is formed, means a film that does a role of passivating a surface defect acting as an electron trap site in the surface of the semiconductor substrate 100.

[101] For example, the passivation film 500 may include a film of semiconductor oxide, semiconductor nitride, semiconductor oxide containing nitrogen, semiconductor nitride containing hydrogen, semiconductor carbide, or titania, or a stacked thin film thereof.

[ 102] As an example of the silicon solar cell, the passivation film 500 may be a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, an alumina film, or a silicon oxynitride film, and a multilayer thin film type passivation film 500 may include a stacked thin film where at least two films selected from a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, an alumina film, a silicon oxynitride film, and a titania film are stacked.

[103] The antireflection film 400 and the passivation film 500 may be formed by using a thin film forming method generally employed in the semiconductor passivation process, and may be formed by at least one selected from, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), and thermal evaporation. Alternatively, the antireflection film 400 may be formed by a general printing process using ink or paste.

[104] After forming the antireflection film 400 and the passivation film 500 in the forming of the dielectric films (step (f)), partial removing of the passivation film (step (g)) is carried out by partially removing a portion of the passivation film 500, which is positioned above the patterned back emitter layer, as shown in FIG. 3.

[105] The partial removing of the passivation film 500 (step (g)) may be carried out by coating an etching paste for etching a passivation film.

[106] As the etching paste, any paste that can etch the passivation film 500 may be used. For example, use products including SolarEtch series (MERCK Company) may be used as the etching paste.

[107] The etching paste may be coated by printing. Specifically, the etching paste may be coated by using a printing method, such as, ink jet printing, masking, stencil, or screen printing. Direct printing of the etching paste can simplify the process conditions, reduce the producing time, and increase the manufacturing cost and the production efficiency.

[108] The etching paste is coated on the passivation film in a predetermined pattern, and thus, a region of the passivation film, on which the etching paste is coated, is partially removed, to thereby form an etched passivation film 510.

[109] The etching paste is coated to have a shape and a place corresponding to a shape and a place of the p-type finger electrodes connected with the p-type semiconductor substrate, preferably, the p-type finger electrodes and the p-type bus bar electrode, to thereby expose the surface of the p-type semiconductor substrate.

[110] In other words, in the removing of the passivation film (step (g)), the etching paste is coated such that a p-type semiconductor region of the p-type semiconductor substrate corresponds to the shape and the place of the p-type finger electrodes, preferably, the p-type finger electrodes and the p-type bus bar electrode, to thereby etch the passivation film.

[I l l] A p-type electrode 600 is formed on the p-type semiconductor region surface- exposed due to the removal of the passivation film. The p-type electrode 600 may include a plurality of band shaped finger electrodes spaced apart from each other and a bus bar electrode electrically connecting the plurality of finger electrodes.

[112] The n-type electrode (n-type finger electrodes and n-type bus bar electrode) and the p-type electrode (p-type finger electrodes and p-type bus bar electrode) each may have a fish bone structure. The p-type electrode and the n-type electrode may have an inter- digitated structure.

[113] The constitution described above of forming the layers of a second conductive type through one stage of doping process, forming the high-concentration back emitter layer through selective etching, forming a low-concentration front emitter layer through partial etching, forming the dielectric film, and removing the passivation film for forming the p-type electrode, can have high short current, open voltage, and fidelity, through a simple process such as partial etching using one stage of doping and printing; prevent leakage current from being generated at the time of forming •electrodes; and allowing the manufacture of a high-efficiency solar cell in a short time through the simple process, thereby realizing reduction of cost and superior productivity.

[1 14] After the removing of the passivation film (step (g)), forming of electrodes (step (h)) is carried out to form the n-type electrode and the p-type electrode. Specifically, the n- type electrode and the p-type electrode are formed by coating an n-type electrode material and coating a p-type electrode material and then carrying out heat treatment.

[115] More specifically, the p-type electrode material is coated on the p-type region

exposed (the surface-exposed p-type semiconductor substrate) by removing the passivation film, and the n-type electrode material is coated on the passivation film above the patterned back emitter layer 211, and then heat treatment is carried out, so that the p-type electrode 600 is connected with the semiconductor substrate and the n-type electrode 710 and 720 is connected with the patterned back emitter layer 211 by punch through.

[116] The coating of the p-type electrode material and the coating of the n-type electrode material may be carried out by printing a paste containing corresponding materials, independently and respectively. The printing includes inkjet printing, masking, stencil, and screen printing.

[1 17] A back surface field (BSF) 610 is formed by the heat treatment at the time of forming the p-type electrode, and the p-type electrode material preferably contains aluminum so as to be bound to the semiconductor substrate.

[1 18] The n-type electrode (second electrode) 700 includes a 2-1 electrode after punch through 71 1 and a 2-2 electrode 720. The 2-1 electrode 71 1 is connected with the patterned back emitter layer 211 through a punch through phenomenon penetrating the passivation film. The 2-2 electrode 720 is formed on the 2-1 electrode 711 such that the 2-2 electrode 720 does not pass through the passivation film and covers the 2-1 electrode 711.

[119] A 2-1 electrode before heat treatment 710 is a connection electrode for passing

through the passivation film to be connected with the patterned back emitter layer 211, and it is adopted in order to minimize damage of the passivation film and be electrically connected with the patterned back emitter layer 211. The 2-2 electrode 720 is adopted in order to reduce an increase in resistance generated due to an electrode fine structure of the 2-1 electrode 710.

[120] The 2-1 electrode passing through the passivation film means that a material for the 2-1 electrode interface-reacts with the passivation film to thereby be physically contacted with the patterned back emitter layer, and means that the material for the 2-1 electrode is contacted with the patterned back emitter layer by the punch through phenomenon. See, J. Hoomstra, et al, 31st IEEE PVSC Florida 2005 for specific mechanism with regard to the punch through phenomenon.

[121] Specifically, the meaning that the passivation film is passed through is that the

electrode material for the 2-1 electrode before heat treatment 710 coated on the passivation film performs an oxidation-reduction reaction at an interface surface with the passivation film by heat energy to thereby etch the passivation film, and the conductive material contained in the electrode material for the 2-1 electrode is melted and recrys- tallized to thereby be contacted with the patterned back emitter layer by using the etched region of the passivation film as a passage.

[122] For example, the electrode material for the 2-1 electrode includes glass frit that

etches the passivation film through the interface reaction, and includes a conductive metal material that passes through the etched region of the passivation film to make a low-resistant passage through melting and recrystallizing.

[123] Representative examples of the conductive metal material contained in the 2-1

electrode may be one or two or more selected from silver (Ag), copper (Cu), titanium (Ti), gold (Au), aluminum (Al), tungsten (W), nickel (Ni), chrome (Cr), molybdenum (Mo), platinum (Pt), lead (Pb), palladium (Pd), and an alloy thereof, and silver, copper, nickel, aluminum, or an alloy thereof is preferable in view of a low melting point and excellent electric conductivity. As the glass frit that is contained in the 2-1 electrode and etches the passivation film, lead glass containing lead oxide or lead-free glass containing bismuth oxide or boron oxide, which is generally used to form an electrode of a solar cell, may be used. Examples of the lead glass based frit may be PbO-Si0₂-B₂ 0₃-Al₂0₃ glass frit, PbO-Si0₂-B₂0₃-Al₂O Zr0₂ glass frit, PbO-Si0₂-B₂0₃-Al₂0₃-ZnO glass frit, and PbO-Si0₂-B₂0₃-Al₂0₃-ZnO-Ti0₂ glass frit. Examples of the lead-free glass based frit may be Bi₂0₃-ZnO-Si0₂-B₂0₃-Al₂0₃ glass frit, Bi₂0₃-SrO-Si0₂-B₂0₃ - A1₂0₃ glass frit, Bi₂0₃-ZnO-Si0₂-B₂0₃-La₂0₃-Al₂0₃ glass frit, Bi₂0₃-ZnO-Si0₂-B₂0₃ - Ti0₂ glass frit, Bi₂0₃-Si0₂-B₂0₃-SrO glass frit, and Bi₂0₃-Si0₂-B₂0₃-ZnO-SrO glass frit. Here, the lead glass or the lead-free glass may further contain one or two or more additives selected from Ta₂0₅, Sb₂0₅, Hf0₂, ln₂0₃, Ga₂0₃, Y₂0₃, and Yb₂0₃. The 2-1 electrode preferably contains 3 to 5 wt% of the lead glass or the lead-free glass.

[124] The 2-1 electrode before heat treatment 710 may be a plurality of dot shapes or fine line shapes uniformly arranged.

[125] The 2-2 electrode 720 is formed on the 2-1 electrode before heat treatment 710 and the passivation layer to cover the 2-1 electrode before heat treatment 710. The meaning that the 2-2 electrode covers the 2-1 electrode is that the entire surface of the 2-1 electrode is wrapped by the 2-2 electrode..

[126] Among the 2-1 electrode and the 2-2 electrode, the 2-2 electrode does not pass

through the passivation film and only the 2-1 electrode selectively passes through the passivation film to be connected with the substrate. The meaning that the 2-2 electrode does not pass through the passivation film is that the electrode material for the 2-2 electrode does not interface-react with the passivation film, and the meaning thereof is that the punch through of the passivation film by the electrode material for the 2-2 electrode does not occur even in the case where heat energy is applied. [127] Preferably, the 2-2 electrode 720 contains glass frit and a conductive metal material that do not interface-react with the passivation film.

[128] The glass frit contained in the 2-2 electrode does not interface-react with the passivation film to improve physical binding strength of the 2-2 electrode, and thus serves to increase interface binding strength between the patterned back emitter layer and the 2-1 electrode.

[129] The conductive material contained in the 2-2 electrode is preferably a conductive material enables smooth densification and grain growth by the heat that is applied for punch through of the first electrode.

[130] Representative examples of the conductive metal material contained in the 2-2

electrode may be one or two or more selected from silver (Ag), copper (Cu), titanium (Ti), gold (Au), aluminum (Al), tungsten (W), nickel (Ni), chrome (Cr), molybdenum (Mo), platinum (Pt), lead (Pb), palladium (Pd), and an alloy thereof. Examples of the glass frit that is contained in the 2-2 electrode and does not etch the passivation film may be a general silica based or phosphate based glass not containing B, Bi, and Pb. More preferably, the glass frit contained in the 2-2 electrode is preferably a silica based or phosphate based glass not containing B, Bi, and Pb, of which the glass temperature (Tg) 1.2 - 2 times that of the glass frit contained in the 2-1 electrode.

[131] The silica based glass frit preferably contains one or two or more selected from Li₂0, Na₂0, K₂0, MgO, CaO, BaO, SrO, ZnO, A1₂0₃, Ti0₂, Zr0₂, Ta₂O_s, Sb₂0₅, Hf0₂, ln₂0₃, Ga₂0₃, Y₂0₃ and Yb₂0₃ while using Si0₂ as a network-forming component. The phosphate based glass frit is a vanadium-phosphate based glass, P₂0₅-V₂0₅, or a zinc- antimony-phosphate based glass, P₂0₅-ZnO-Sb₂0₃. The phosphate based glass frit preferably contains one or two or more selected from K₂0, Fe₂0₃, Sb₂0₃, ZnO, Ti0₂, A1₂0₃, and W0₃. Here, the 2-2 electrode preferably contains 3 to 5 wt% of the silica based or phosphate based glass.

[132] The 2-2 electrode 720 may have a band shape connecting a plurality of dot shaped 2-1 electrodes before heat treatment 710 or a band shape covering a fine line shaped 2-1 electrode before heat treatment 710.

[133] The dot diameter or fine line width of the 2-1 electrode before heat treatment 710 may be 30μη to 300/_~m, and the width of the 2-2 electrode 720 may be 50μϋΐ to Ι,ΟΟΟ πι. These widths may minimize the reduction of a light receiving area by the 2-2 electrode and lower the increase of a resistance by the 2-2 electrode, and allow the n-type electrode including the 2-1 electrode and the 2-2 electrode to have a resistance of 3~6 10-⁶Qcm.

[134] As such, after the 2-1 electrode before heat treatment 710 is printed and the 2-2

electrode 720 is formed on the 2-1 electrode 710 to cover the 2-1 electrode 710, the heat treatment is carried out so that, between the 2-1 electrode and the 2-2 electrode, only the 2-1 electrode is selectively connected with the patterned back emitter layer. Here, the p-type electrode is also printed before the heat treatment, and thus, the p-type electrode 600 and the BSF 610 are preferably formed together with the n-type electrode including the 2-1 electrode after punch through 711 and the 2-2 electrode 720 wrapping the 2-1 electrode, through single heat treatment.

[135] As described above, in the solar cell according to the present invention, the n-type electrode that collects electrons or holes generated by irradiation of light may include the 2-1 electrode and the 2-2 electrode.

[136] The n-type electrode that collects the electrons or holes includes the n-type finger electrodes and/or n-type bus bar electrode of the solar cell.

[137] Here, a soldering layer for solar cell modularizing by which two or more solar cells are connected in series or in parallel with each other may be further formed above the n-type electrode including the 2-1 electrode and the 2-2 electrode. Specifically, in order to connect electrodes of two or more solar cells in series or in parallel with each other, a conductive ribbon is soldered and bound to the electrode, and a soldering layer for soldering may be further formed.

[138] Specifically, the soldering layer is for improving fusion characteristics between the conductive ribbon and the electrode and wetting characteristics of a solder material at the time when the soldering is carried out between the conductive ribbon and the n- type electrode including the 2-1 electrode and the 2-2 electrode.

[139] As the conductive ribbon, any conductive ribbon that can be generally used to

modularize the solar cell may be used. A non-limited example of the conductive ribbon may be a copper ribbon plated with a soldering material such as lead tin or silver. As the soldering layer, any soldering layer that can be generally used to improve binding strength with the soldering material and wetting characteristics at the time of solar cell modularization may be used. The soldering layer may be appropriately selected in consideration of the soldering material.

[140] However, the foregoing solder cell may be of course modularized by using a

conductive adhesive that is hardenable by heat or light or chemically hardenable, instead of the soldering.

[141] In the manufacturing method of a solar cell according to the present invention, a

surface texturing process may be further carried out by etching the semiconductor substrate 100 to form fine concave and convex portions in the surface of the semiconductor substrate 100, before forming the etching-resist pattern and after forming the via hole. The etching includes dry or wet etching, and the textured surface include a surface in which a plurality of inverted pyramid shaped fine concave-convex patterns are arranged.

[142] As set forth above, the solar cell manufactured by the manufacturing method of the present invention can have high short current, open voltage, and fidelity, through a single doping process to thereby exhibit excellent photovoltaic conversion efficiency; prevent generation of leakage current at the time of forming electrodes; and decrease the number of process stages and reduce the manufacturing time to thereby achieve cost reduction and high productivity.

[143] As described above, although the present invention is described by specific matters such as concrete components and the like, embodiments, and drawings, they are provided only for assisting in the entire understanding of the present invention.

Therefore, the present invention is not limited to the exemplary embodiments. Various modifications and changes may be made by those skilled in the art to which the present invention pertains from this description.

[144] Therefore, the spirit of the present invention should not be limited to the above- described embodiments, and the following claims as well as all modified equally or equivalently to the claims are intended to fall within the scope and spirit of the invention.

[145]

Claims

A manufacturing method of a back contact solar cell, the method comprising:

a) forming a via hole to pass through two opposing surfaces of a semiconductor substrate of a first conductive type;

b) doping an impurity of a second conductive type into surfaces of the semiconductor substrate to form layers of a second conductive type; c) forming an etching-resist pattern on one of the two opposing surfaces to cover an opening portion of the via hole;

d) selectively etching one surface of the semiconductor ^"substrate using the etching-resist pattern as an etching mask, to thereby remove a portion of the layer of the second conductive type present on one surface of the semiconductor substrate on which the etching-resist pattern is not formed; and

e) partially etching the layer of the second conductive type present on the other surface of the semiconductor substrate, which is opposite to one surface of the semiconductor substrate, to thereby control a concentration of the impurity in the layer of the second conductive type present on the other surface of the semiconductor substrate.

The method of claim 1, further comprising:

f) forming dielectric layers by forming a passivation film on one surface of the semiconductor substrate and an anti-reflection film on the other surface of the semiconductor substrate;

g) partially removing the passivation film by partially coating an etching paste for etching the passivation film on one surface, to thereby expose a region of the semiconductor substrate, from which the layer of the second conductive type is removed by the selective etching; and h) forming electrodes by forming, on one surface, a first electrode connected with the exposed region of the semiconductor substrate and a second electrode connected with layer of a second conductive type through punch-through.

The method of claim 1, wherein a surface step height is formed between a surface of the semiconductor substrate, which is exposed by removing the layer of the second conductive type due to the selective etching, and the layer of the second conductive type below the etching- resist pattern.

The method of claim 1, wherein the layer of the second conductive type formed in the doping has a sheet resistance of 10~40Q/sq., and wherein in the partial etching, the layer of the second conductive type formed on the other surface of the semiconductor substrate is partially removed so as to have a sheet resistance of 30- 150Q/sq.

The method of claim 1, wherein the partial etching is carried out by dry etching.

The method of claim 5, wherein a thickness of the layer of the second conductive type formed on an inner surface of the via hole is controlled by the partial etching.

The method of claim 5, wherein the thickness of the layer of the second conductive type formed on an inner surface of the via hole is reduced from one surface of the semiconductor substrate toward the other surface of the semiconductor substrate by the partial etching.

The method of claim 5, further comprising, after the partial etching, performing a washing process using a radio corporation of America (RCA) washing method.

The method of claim 1 , wherein the etching-resist pattern is formed by a printing process.

A back contact solar cell manufactured by any one of claims 1 to 9.