[go: up one dir, main page]

WO2013086861A1 - Procédé d'accès à un équipement d'entrée/sortie (e/s) multichemin, et gestionnaire et système multichemin d'e/s - Google Patents

Procédé d'accès à un équipement d'entrée/sortie (e/s) multichemin, et gestionnaire et système multichemin d'e/s Download PDF

Info

Publication number
WO2013086861A1
WO2013086861A1 PCT/CN2012/079307 CN2012079307W WO2013086861A1 WO 2013086861 A1 WO2013086861 A1 WO 2013086861A1 CN 2012079307 W CN2012079307 W CN 2012079307W WO 2013086861 A1 WO2013086861 A1 WO 2013086861A1
Authority
WO
WIPO (PCT)
Prior art keywords
hard partition
hard
pci
node
partition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2012/079307
Other languages
English (en)
Chinese (zh)
Inventor
雕峻峰
刘云海
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of WO2013086861A1 publication Critical patent/WO2013086861A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Definitions

  • the present invention relates to the field of communications, and in particular, to a method for multi-path access to an I/O device, an I/O multipath manager, and a system. Background technique
  • computing nodes in network communications such as servers, directly access I/O (Input/Output) devices through PCI-E (Peripheral Component Interconnect-Express).
  • PCI-E Peripheral Component Interconnect-Express
  • Most of them are based on the cluster scenario, that is, each interface (port) of the default PCI-E switch is connected to different systems, and is not well considered based on NUMA (Non-Uniform Memory Access).
  • NUMA Non-Uniform Memory Access
  • System scenario In a NUMA system, all compute nodes are divided into sets of nodes, and each set of nodes is electrically isolated from other sets of nodes. Such a set is called a hard partition (or a large node), and each hard partition It includes one or more computing nodes, each of which has an RC (Root Complex) that can be connected to PCI-E.
  • RC Root Complex
  • a NUMA system is composed of multiple computing nodes aggregated through a NUMA network.
  • the hardware resources of these physical nodes are managed by an OS (Operating System) or a hypervisor.
  • OS Operating System
  • a hypervisor Take the NUMA system as an example.
  • Figure 1 a network diagram showing only one large node (or hard partition), including NUMA office and network 1, hard partition 2 including 3 compute nodes 21 ⁇ 23, PCI- E switch 3, external I/O device 4, each compute node has at least 1 CPU (Central Processing Unit), an NC (Node Controller), located at ⁇ (Input/Output Hub, The root complex (RC) in the input and output hub), the external I/O device 6 includes a Fibre Channel network card 31 and an Ethernet card 32.
  • CPU Central Processing Unit
  • NC Node Controller
  • the computing node 21 is the master node, and assumes the tasks of primary partition initiation and resource management, and the computing nodes 22-24 are slave nodes.
  • the three compute nodes form a 6-way system through a NUMA aggregation network (actually, this PCI-E switch is also connected to other hard-partitioned compute nodes in the NUMA system).
  • the compute node 21 is externally connected to the PCI-E link of the PCI-E switch.
  • 01 is a solid line display, and the PCI-E links 02 and 03 of the computing nodes 22 to 23 connected to the PCI-E switch are dotted lines.
  • FIG. 2 it is a schematic diagram of the resource information table of the system shown in Figure 1.
  • the compute nodes 22 ⁇ 23 cannot directly see I/O devices such as Ethernet cards and Fibre Channel network cards.
  • To access I/O devices such as Ethernet cards To pass through the NUMA aggregation network through the NUMA link, and then access through the link of the compute node 21. This increases the delay.
  • the primary node itself may have a bottleneck of input and output, and the PCI-E links that are connected to other slave nodes have no effect, and the bandwidth utilization is low. Summary of the invention
  • Embodiments of the present invention provide a method for multipath access I/O device, an I/O multipath manager, and a system, which can effectively enable a PCI-E link between all computing nodes and a PCI-E switch, eliminating the Bottlenecks in case of latency and high traffic increase bandwidth utilization.
  • a method for accessing an I/O device by using a multi-path includes: configuring a PCI-E switch according to the received configuration information of the first hard partition, to isolate the a hard partition other than the first hard partition, the computing node of the first hard partition accessing only the I/O device of the first hard partition; establishing the location according to the received configuration information of the first hard partition a mapping relationship between the computing node of the first hard partition and the I/O device of the first hard partition, so that the operating system instructs the computing node that performs the I/O task to access the first hard according to the mapping relationship Partitioned I/O devices.
  • an I/O multipath manager includes: a PCI-E switch configuration module, configured to configure a peripheral component to quickly interconnect a standard PCI-E switch according to the received configuration information of the first hard partition, to isolate And other hard partitions other than the first hard partition, so that the computing node of the first hard partition accesses only the I/O device of the first hard partition;
  • An I/O multipath configuration module configured to establish, according to the received configuration information of the first hard partition, a mapping relationship between the computing node of the first hard partition and the I/O device of the first hard partition And causing the operating system to instruct the computing node performing the I/O task to access the I/O device of the first hard partition according to the mapping relationship.
  • a system for providing multi-path access to an I/O device includes:
  • An I/O multipath manager configured to configure a PCI-E switch according to the received configuration information of the first hard partition, to isolate other hard partitions except the first hard partition, so that the first hard partition
  • the computing node only accesses the I/O device of the first hard partition, and establishes the computing node of the first hard partition and the I/ of the first hard partition according to the received configuration information of the first hard partition.
  • the I/O multipath manager is located in the firmware Or an operating system; an aggregation network, configured to connect computing nodes in the system, so that the system controls the computing node through an operating system; at least two hard partitions, wherein each hard partition includes at least one computing node;
  • a PCI-E switch configured to establish a connection between the computing node and the I/O device, so that the computing node accesses the computing node by using a PCI-E link established between itself and the PCI-E switch I/O device belonging to a hard partition;
  • An I/O device configured to connect between the computing node and an external network; a storage device, configured to store firmware, an operating system, an I/O application.
  • the method for multi-path access I/O device, the I/O multi-path manager and the system provided by the embodiments of the present invention enable the PCI-E link between all the computing nodes and the PCI-E switch to be valid, so that the slave node It can also access I/O devices through its own PCI-E link, eliminating bottlenecks in case of delay and high traffic, and improving bandwidth utilization.
  • FIG. 1 is a schematic diagram of a networking diagram of a prior art NUMA system
  • FIG. 2 is a schematic structural diagram of a system resource information table of a prior art NUMA system
  • FIG. 3 is a schematic flowchart of a method for multipath accessing an I/O device according to an embodiment of the present invention
  • FIG. 4 is a schematic flowchart of a method for accessing an I/O device for multi-path access according to an embodiment of the present invention
  • FIG. 5 is a schematic flowchart of a method for accessing an I/O device for multi-path access according to an embodiment of the present invention
  • FIG. 7 is a schematic diagram of the networking of the NUMA system of the multi-path access I/O device according to the embodiment of the present invention
  • FIG. 8 is a schematic diagram of the networking of the NUMA system of the multi-path access I/O device according to the embodiment of the present invention
  • FIG. 9 is a schematic structural diagram of a system resource information table of a NUMA system according to an embodiment of the present invention
  • FIG. 10 is a schematic diagram of a system resource information table of a NUMA system according to an embodiment of the present invention
  • FIG. 11 is a schematic structural diagram of a system resource information table of an SMP system according to an embodiment of the present invention.
  • the method for the multi-path access I/O device provided by the embodiment of the present invention, as shown in FIG. 3, includes:
  • a method for accessing an I/O device by using a multi-path according to an embodiment of the present invention includes:
  • the master node invokes an I/O multipath manager, and receives configuration information for analyzing the first hard partition.
  • the configuration information generally comes from a system management module (not shown) that manages the entire NUMA system by running management software.
  • the I/O multipath manager analyzes the number of RCs in the first hard partitioned computing node in the configuration information, analyzes the number of I/O devices of the first hard partition, and types of devices, and identifies PCI.
  • -E A corresponding port of the switch with the first hard partitioned compute node and a corresponding port of the PCI-E switch with the first hard partitioned I/O device.
  • the master node invokes the I/O multipath manager to configure the PCI-E switch to isolate other hard partitions except the first hard partition.
  • the corresponding port of the PCI-E switch and the first hard partitioned computing node and the corresponding port of the first hard partitioned I/O device in the PCI-E switch are configured as a virtual switch to isolate
  • the other hard partitioned I/O devices and I/O accesses other than the first hard partition enable the first hard partitioned compute node to access only the first hard partitioned I/O device.
  • the master node searches for an I/O device and boots the slave node to start initialization. Specifically, the master node scans the first node of the first hard partition according to the number of the first hard partitioned computing nodes and the number and type of the first hard partitioned I/O devices. A hard-partitioned I/O device bus that searches for valid I/O devices. After searching for I/O devices, each of the RCs in the master node and the searched I/O devices are assigned addresses and memory, and are booted after the scan is complete. Initialize from the node. S205. The master node invokes the I/O multipath manager to establish a mapping relationship between the compute node of the first hard partition and the I/O device of the first hard partition.
  • the master node invokes the I/O multipath manager to send the address of the first hard partition I/O device to the RC of each slave node through a pointer, and the pointer points to the address of the above I/O device, so that A mapping relationship is established between the compute node of the first hard partition and the I/O device.
  • the master node invokes an I/O multipath manager to form a system resource information table.
  • the master node invokes the I/O multipath manager to form a system resource information table and sends a pointer of the system resource information table to the operating system, where the system resource information table includes the first hard partition computing node and the I/O device.
  • S207. Receive an I/O task, and allocate hardware resources for the I/O task according to the system resource information table. Specifically, the operating system receives the I/O task into the I/O task queue, invokes the system resource information table through the pointer of the system resource information table, and then determines the processor that executes the current I/O task and allocates the memory according to the I/O. The type of task determines which I/O device to access.
  • the operating system instructs the processor that performs the I/O task to access the I/O device through the shortest path according to the system resource information table. Specifically, the operating system selects one according to a mapping relationship between the first hard partitioned computing node and the I/O device in the system resource information table, and a PCI-E link available between the computing node and the PCI-E switch. Perform the shortest path of the current I/O task. In general, this path is the PCI-E link between the compute node and the PCI-E switch where the processor itself performs the current I/O task.
  • the primary node needs to exit the hard partition due to a failure or resource reallocation, etc., as shown in the figure
  • the system management module receives the master node to issue an exit request instruction. Normally, when the primary node of the first hard partition needs to exit the first hard partition due to a failure or resource reallocation, the primary node sends an exit request command to the system management software through the system management module.
  • the system management module receives an exit response command from the master node, instructing the master node to exit the first hard partition.
  • the system management module After receiving the exit request instruction, the system management module sends an instruction to upgrade to the new primary node to one of the slave nodes. After receiving the exit request instruction, the management module of the system selects one of the slave nodes according to the policy of the system, and sends an instruction to the new master node.
  • the new master node receives hardware resource information and I/O tasks from the original master node.
  • the hardware resource information includes processor information for performing an I/O task, information of an I/O device that needs to be accessed to perform an I/O task, memory information, and PCI-E link information that is required to perform an I/O task. 5305.
  • the original primary node exits the first hard partition and waits for maintenance or reallocation.
  • the new master node updates the system resource information table.
  • the new primary node enables the I/O multipath manager to configure the PCI-E switch according to the updated system resource information table, and isolates other hard partitions other than the first hard partition, and the preparation method is the same as step 203 in FIG. It is exactly the same and will not be described again.
  • the system in this embodiment may be a NUMA system or an SMP system, and the computing node may be a server.
  • the method for multi-path accessing an I/O device provided by the embodiment of the present invention enables a PCI-E link between all computing nodes and a PCI-E switch to be valid by establishing a mapping relationship between the computing node and the I/O device.
  • the I/O multipath manager 10 provided by the embodiment of the present invention, as shown in FIG. 6, includes: a call function interface 101, where a master node in a compute node of a first hard partition is invoked through an operating system or firmware The I/O multipath manager.
  • the hard partition resource analysis module 102 is configured to receive configuration information of the first hard partition, analyze the number and address of the RC in the first hard partition of the configuration information, and analyze the number of I/O devices in the first hard partition. And a type of the device, identifying a corresponding port of the PCI-E switch with the compute node of the first hard partition, and a corresponding port of the PCI-E switch with the I/O device of the first hard partition.
  • the PCI-E switch configuration module 103 is configured to configure a PCI-E switch according to the received configuration information of the first hard partition to isolate other hard partitions except the first hard partition, so that the first hard partition compute node only Access the I/O device of the first hard partition.
  • the I/O multipath configuration module 104 is configured to establish a mapping relationship between the first hard partitioned computing node and the first hard partitioned I/O device according to the received configuration information of the first hard partition, so that The operating system instructs the computing node performing the I/O task to access the I/O device of the first hard partition according to the mapping relationship.
  • the I/O multipath manager provided by the embodiment of the present invention enables the PCI-E link between all the computing nodes and the PCI-E switch to be valid by establishing a mapping relationship between the computing node and the I/O device, thereby The slave node can also access the I/O device through its own PCI-E link, thereby eliminating the bottleneck in the case of delay and high traffic, and improving the bandwidth utilization.
  • the fourth embodiment of the present invention provides a multi-path access I/O device.
  • the NUMA system is taken as an example.
  • the method includes: an I/O multipath manager 10 as shown in FIG.
  • the firmware 51 is configured to configure the PCI-E switch 3 according to the received configuration information of the first hard partition 2 to isolate other hard partitions except the first hard partition 2, so that the computing nodes 21-22 access only the first The I/O device 4 of the hard partition 2, and establishing a mapping relationship between the computing nodes 21 ⁇ 23 and the I/O device 4 according to the received configuration information of the first hard partition 2, so that the computing nodes 21 ⁇ 23 and the PCI- The PCI-E links 01 ⁇ 03 between the E switches 3 become valid.
  • the PCI-E links 01 ⁇ 03 are all solid lines. Then, the I/O multipath manager 10 compares the mapping relationship between the compute nodes 21-23 and the I/O device 4, the processor information, the memory information, and the available PCI between the compute nodes 21-23 and the PCI-E switch 3.
  • the E links 01 ⁇ 03 are associated to form a system resource information table.
  • the operating system 52 accesses the I/O device according to the shortest path according to the indication computer points 21 ⁇ 23 according to the system resource information table, which is generally the shortest.
  • the path is the link between the compute node itself and the PCI-E switch that performs the I/O task.
  • NUMA aggregation network 1 is used to connect all compute nodes through NC aggregation and control all compute nodes through an operating system.
  • At least one hard partition 2 (only the first hard partition 2 is drawn in FIG. 7, other hard partitions are not shown), including one master node 21 and two slave nodes 22, 23, of course, more slave nodes can be added.
  • each computing node includes: a node controller NC, used for computing nodes and NUMA converged network connection; two CPUs for performing I/O tasks; one RC for I/O device scanning and compute node connection to PCI-E corresponding port.
  • the RC is located in an IOH (Input-Output Hub), and the RC can also be located in a CPU or a MUX (Multiplexer).
  • the above computing node can be a server.
  • the PCI-E switch 3 is configured to establish a link between the computing nodes 21 ⁇ 23 of the first hard partition 2 and the I/O device 4 of the first hard partition, as shown in FIG. 7, the calculation of the first hard partition 2.
  • the nodes 21 ⁇ 23 and the PCI-E switch link are both solid lines, and the compute nodes 21 ⁇ 23 can directly access the I/O device 4 of the first hard partition 2 through the own link 01-03.
  • the PCI-E switch is also connected to other hard partitions, not shown in the figure.
  • the I/O device 4 includes a Fibre Channel (FC) network card 41 and an Ethernet card for connecting the computing nodes to the external network.
  • the storage device 5 is for storing the firmware 51, the operating system 52, and the firmware 51 includes an I/O multipath manager 511.
  • Another multi-path access I/O device system provided by this embodiment takes a NUMA system as an example. As shown in FIG. 8, the storage device 5 is configured to store firmware 51, an operating system 52, and an I/O multipath manager. 10 is located in the operating system 52, and the rest is exactly the same as the system shown in FIG. 4, and will not be described again.
  • the system resource information table of the NUMA system is shown in FIG. 9.
  • the system of the multi-path access I/O device provided by the embodiment of the present invention enables the PCI-E link between all the computing nodes and the PCI-E switch to be valid by establishing a mapping relationship between the computing node and the I/O device. Therefore, the slave node can also access the I/O device through its own PCI-E link, thereby eliminating the bottleneck in the case of delay and high traffic, and improving the bandwidth utilization.
  • the fifth embodiment of the present invention provides a multi-path access I/O device.
  • the SMP (Symmetric Multi-Process) system is used as an example. As shown in FIG.
  • the method includes: /O Multipath Manager 10, located in firmware 51, for receiving
  • the configuration information of the second hard partition 2a is configured to configure the PCI-E switch 3 to isolate other hard partitions except the second hard partition, so that the computing node 2al ⁇ 2a2 only accesses the I/O device 4 of the second hard partition 2a.
  • the roads 01 ⁇ 03 are all valid.
  • the PCI-E links 01 ⁇ 03 are all solid lines.
  • the I/O multipath manager 10 compares the mapping relationship between the compute nodes 2al ⁇ 2a3 and the I/O device 4, the processor information, the memory information, and the available PCI between the compute nodes 2al ⁇ 2a3 and the PCI-E switch 3.
  • the E links 01 ⁇ 03 are associated to form a system resource information table.
  • the operating system 52 accesses the I/O device according to the shortest path according to the indication computer point 2al ⁇ 2a3 according to the system resource information table, which is generally the shortest.
  • the path is the link between the compute node itself and the PCI-E switch that performs the I/O task.
  • the I/O multipath manager 10 can also be located in the operating system 52 (not shown in FIG. 10).
  • the SMP aggregation network 1 is used to directly interconnect the CPUs of all computing nodes, does not require an NC, and controls all computing nodes through an operating system.
  • At least two hard partitions (only the second hard partition 2a is shown in FIG. 10, other hard partitions are not shown), including one master node 2al and two slave nodes 2a2, 2a3, and of course, more slave nodes can be added.
  • Each compute node includes: two CPUs for performing I/O tasks and direct interconnection between the nodes; and an RC for calculating the connection of the node to the corresponding port of the PCI-E.
  • the RC is located in the IOH, and the RC may also be located in the CPU or the MUX.
  • the above computing node can be a server.
  • the rest of the system provided by this embodiment is completely the same as the system shown in FIG. 7, and will not be described again.
  • the system resource table of the system is shown in FIG.
  • the system of the multi-path access I/O device provided by the embodiment of the present invention enables the PCI-E link between all the computing nodes and the PCI-E switch to be valid by establishing a mapping relationship between the computing node and the I/O device. Therefore, the slave node can also access the I/O device through its own PCI-E link, thereby eliminating the bottleneck in the case of delay and high traffic, and improving the bandwidth utilization.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

La présente invention concerne un procédé d'accès à un équipement d'entrée/sortie (E/S) multichemin, et un gestionnaire et un système multichemin d'E/S qui se rapportent au domaine des technologies de l'information (TI). Grâce à l'invention, les liaisons d'interconnexion de composants périphériques express (PCI-E) entre tous les nœuds de calcul et un commutateur PCI-E peuvent être efficaces, et les nœuds esclaves peuvent également accéder à l'équipement d'E/S par leurs propres liaisons PCI-E, si bien que le temps de retard et le goulot d'étranglement dans des conditions de trafic de service élevé sont éliminés, et le taux d'utilisation de la bande passante est augmenté. Le procédé comprend les étapes suivantes : configurer, selon les informations de configuration reçues de la première zone difficile, le commutateur PCI-E pour faire en sorte que les nœuds de calcul de la première zone difficile accèdent seulement à l'équipement d'E/S de la première zone difficile ; et établir, en fonction des informations de configuration reçues de la première zone difficile, une relation de correspondance entre les nœuds de calcul de la première zone difficile et l'équipement d'E/S de la première zone difficile pour faire en sorte qu'un système d'exploitation indique les nœuds de calcul exécutant des tâches d'E/S pour accéder à l'équipement d'E/S de la première zone difficile selon la relation de correspondance. Le mode de réalisation de l'invention est utilisé pour l'accès multichemin de l'équipement d'E/S.
PCT/CN2012/079307 2011-12-13 2012-07-28 Procédé d'accès à un équipement d'entrée/sortie (e/s) multichemin, et gestionnaire et système multichemin d'e/s Ceased WO2013086861A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201110415345.XA CN102497432B (zh) 2011-12-13 2011-12-13 一种多路径访问i/o设备的方法、i/o多路径管理器及系统
CN201110415345.X 2011-12-13

Publications (1)

Publication Number Publication Date
WO2013086861A1 true WO2013086861A1 (fr) 2013-06-20

Family

ID=46189217

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/079307 Ceased WO2013086861A1 (fr) 2011-12-13 2012-07-28 Procédé d'accès à un équipement d'entrée/sortie (e/s) multichemin, et gestionnaire et système multichemin d'e/s

Country Status (2)

Country Link
CN (1) CN102497432B (fr)
WO (1) WO2013086861A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110430601A (zh) * 2019-08-09 2019-11-08 西安科技大学 一种PCI Express链路速率管理系统和管理方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102497432B (zh) * 2011-12-13 2014-06-25 华为技术有限公司 一种多路径访问i/o设备的方法、i/o多路径管理器及系统
CN103312720B (zh) * 2013-07-01 2016-05-25 华为技术有限公司 一种数据传输方法、设备及系统
CN108880857B (zh) * 2015-08-24 2021-03-16 上海天旦网络科技发展有限公司 发现与呈现网络应用访问信息的方法和系统
CN105959176B (zh) * 2016-04-25 2019-05-28 浪潮(北京)电子信息产业有限公司 基于Gem5模拟器的一致性协议测试方法和系统
US11249808B2 (en) * 2017-08-22 2022-02-15 Intel Corporation Connecting accelerator resources using a switch
US10585833B1 (en) * 2019-01-28 2020-03-10 Quanta Computer Inc. Flexible PCIe topology
CN115811446A (zh) * 2021-09-14 2023-03-17 华为技术有限公司 一种总线系统、通信方法及相关设备
CN114168499A (zh) * 2021-11-10 2022-03-11 上海安路信息科技股份有限公司 PCIe设备的访问控制方法、装置及系统
CN117492967B (zh) * 2023-12-28 2024-03-19 苏州元脑智能科技有限公司 一种存储系统资源管理的方法、装置、设备及介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007021513A2 (fr) * 2005-08-09 2007-02-22 Intel Corporation Accès exclusif pour un programme audio sécurisé
CN101425046A (zh) * 2008-10-28 2009-05-06 北京航空航天大学 分布式i/o资源虚拟化技术的实现方法
CN101901207A (zh) * 2010-07-23 2010-12-01 中国科学院计算技术研究所 异构共享存储多处理机系统的操作系统及其工作方法
CN102497432A (zh) * 2011-12-13 2012-06-13 华为技术有限公司 一种多路径访问i/o设备的方法、i/o多路径管理器及系统

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7395367B2 (en) * 2005-10-27 2008-07-01 International Business Machines Corporation Method using a master node to control I/O fabric configuration in a multi-host environment
US7631050B2 (en) * 2005-10-27 2009-12-08 International Business Machines Corporation Method for confirming identity of a master node selected to control I/O fabric configuration in a multi-host environment

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007021513A2 (fr) * 2005-08-09 2007-02-22 Intel Corporation Accès exclusif pour un programme audio sécurisé
CN101425046A (zh) * 2008-10-28 2009-05-06 北京航空航天大学 分布式i/o资源虚拟化技术的实现方法
CN101901207A (zh) * 2010-07-23 2010-12-01 中国科学院计算技术研究所 异构共享存储多处理机系统的操作系统及其工作方法
CN102497432A (zh) * 2011-12-13 2012-06-13 华为技术有限公司 一种多路径访问i/o设备的方法、i/o多路径管理器及系统

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110430601A (zh) * 2019-08-09 2019-11-08 西安科技大学 一种PCI Express链路速率管理系统和管理方法
CN110430601B (zh) * 2019-08-09 2023-05-09 西安科技大学 一种PCI Express链路速率管理系统和管理方法

Also Published As

Publication number Publication date
CN102497432B (zh) 2014-06-25
CN102497432A (zh) 2012-06-13

Similar Documents

Publication Publication Date Title
WO2013086861A1 (fr) Procédé d'accès à un équipement d'entrée/sortie (e/s) multichemin, et gestionnaire et système multichemin d'e/s
EP3582108B1 (fr) Systèmes ultraconvergés ayant de multiples zones de disponibilité
CN103201721B (zh) 虚拟机热迁移的系统和方法
EP3252608B1 (fr) Système de noeud, dispositif de serveur, procédé de commande de mise à l'echelle et programme
US9031081B2 (en) Method and system for switching in a virtualized platform
US9558041B2 (en) Transparent non-uniform memory access (NUMA) awareness
US7870301B2 (en) System and method for modification of virtual adapter resources in a logically partitioned data processing system
US9154451B2 (en) Systems and methods for sharing devices in a virtualization environment
US20100287262A1 (en) Method and system for guaranteed end-to-end data flows in a local networking domain
CN103609077B (zh) 用于数据传输的方法、装置和系统以及物理网卡
WO2016065643A1 (fr) Procédé de configuration de cartes réseau et centre de gestion de ressources
EP3332325B1 (fr) Procédés, appareil, et systèmes pour assurer l'accès à des ports série de machines virtuelles dans des applications virtuelles auto-déployées
US11005968B2 (en) Fabric support for quality of service
WO2012177359A2 (fr) Informatique en nuage native par intermédiaire de segmentation de réseau
US20160203030A1 (en) Load calculation method, load calculation program, and load calculation apparatus
JP2009075718A (ja) 仮想ｉ／ｏパスの管理方法、情報処理システム及びプログラム
WO2016107023A1 (fr) Système serveur en nuage
CN114860387A (zh) 一种面向虚拟化存储应用的hba控制器i/o虚拟化方法
CN108351802B (zh) 计算机数据处理系统和用于虚拟机通信的基于通信流量的优化的方法
CN118467093A (zh) 资源处理方法、装置、设备、可读存储介质及程序产品
CN115827148A (zh) 一种资源管理方法、装置、电子设备及存储介质
JP2022087808A (ja) ストレージ・エリア・ネットワーク輻輳のエンドポイント通知を行う方法、システム、およびコンピュータ・プログラム
US11474827B1 (en) Reboot migration between bare-metal servers
CN114428757A (zh) 一种架构可重构的计算装置及其重构方法
US20200387396A1 (en) Information processing apparatus and information processing system

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12856777

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12856777

Country of ref document: EP

Kind code of ref document: A1