[go: up one dir, main page]

WO2012135363A2 - Circuit intégré comportant une surface d'entretoise modifiée chimiquement - Google Patents

Circuit intégré comportant une surface d'entretoise modifiée chimiquement Download PDF

Info

Publication number
WO2012135363A2
WO2012135363A2 PCT/US2012/030977 US2012030977W WO2012135363A2 WO 2012135363 A2 WO2012135363 A2 WO 2012135363A2 US 2012030977 W US2012030977 W US 2012030977W WO 2012135363 A2 WO2012135363 A2 WO 2012135363A2
Authority
WO
WIPO (PCT)
Prior art keywords
dielectric material
sidewall spacers
spacers
gate stack
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2012/030977
Other languages
English (en)
Other versions
WO2012135363A3 (fr
Inventor
Brian K. Kirkpatrick
Amitabh Jain
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Japan Ltd
Texas Instruments Inc
Original Assignee
Texas Instruments Japan Ltd
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/427,062 external-priority patent/US9496359B2/en
Application filed by Texas Instruments Japan Ltd, Texas Instruments Inc filed Critical Texas Instruments Japan Ltd
Priority to JP2014502758A priority Critical patent/JP2014514757A/ja
Publication of WO2012135363A2 publication Critical patent/WO2012135363A2/fr
Publication of WO2012135363A3 publication Critical patent/WO2012135363A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0184—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation

Definitions

  • Disclosed embodiments relate to semiconductor processing and integrated circuit (IC) devices therefrom which include metal-oxide-semiconductor (MOS) transistors, including MOS transistors having multi-layer sidewall spacers.
  • MOS metal-oxide-semiconductor
  • Thin silicon nitride sidewall spacers are commonly used as an implant mask to provide a space between the lightly doped drain (LDD) implants into the semiconductor surface and the gate stack.
  • LDD lightly doped drain
  • a typical process flow has a first spacer layer that acts first as an offset spacer, then as an underlay er/etch- stop while additional films, such as disposable second sidewall spacer comprising SiGe, is deposited on top, used, which is then subsequently removed.
  • hot phosphoric acid (HP A) is used to remove the second sidewall spacer.
  • etch stop characteristics can be lost resulting in inadvertent removal of the silicon nitride offset sidewall spacer, and as a result subsequent shorting between the gate and source and/or drain, such as due to a subsequently deposited silicide ion the gate, source and drain.
  • semiconductor devices are shrunk in size, and the distance between the top of the gate stack and the top surface of the source/drain regions is reduced, the probability of electrical shorts due to the silicide forming on the sidewalls of the gate stack increases.
  • Disclosed embodiments describe solutions to the above-described inadvertent removal of thin sidewall spacers for metal-oxide-semiconductor (MOS) transistors that use multi-layer sidewall spacers.
  • MOS metal-oxide-semiconductor
  • the second material can substantially increase the etch resistance compared to the first spacer material.
  • the subsequent removal of a disposable second spacer on the first spacer will not remove the first spacer since the second dielectric material can act as an etch stop, or at least provide some etch protection for the first dielectric material of the first spacer.
  • One disclosed embodiment comprises a method of fabricating an integrated circuit that includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric.
  • the first dielectric material is etched, such as using RIE, to form sidewall spacers on sidewalls of the gate stack.
  • a top surface of the first dielectric material is chemically converted to a second dielectric material by adding at least one element to provide surface converted sidewall spacers.
  • the second dielectric material is chemically bonded across a transition region to the first dielectric material.
  • ion implanting can follow to form lightly doped drains (LDDs) in the semiconductor surface lateral to the gate stack.
  • Second spacers are then formed on the surface converted sidewall spacers.
  • Sources and drains are then formed lateral to the gate stack.
  • Ion implanting can be used to form sources and drains in the semiconductor surface lateral to the gate stack after forming the second spacers.
  • the second sidewall spacers can be used for a SiGe S/D process (e.g., where recesses are formed typically in the PMOS region and replaced with SiGe).
  • the second spacers can then be selective removed after the source/drain formation.
  • the surface of chemically converted layer remains intact after the selective etching, as does the first dielectric material protected by the surface converted layer.
  • FIG. 1 is a flow chart that shows steps in an example method for fabricating an integrated circuit (IC) device having MOS transistors that include surface converted sidewall spacers, according to an example embodiment.
  • FIG. 2A-2F are cross-sectional diagrams depicting processing progression for an example method of forming an IC device having MOS transistors that include surface converted sidewall spacers, according to an example embodiment, while FIG. 2G shows the resulting spacer structure after a known spacer process showing the results from the inadvertent removal of the nitride offset spacer.
  • FIG. 3 is a cross-sectional view of a portion of an IC device including MOS transistors having sidewall spacers comprising a second dielectric material on a first dielectric material, wherein the second dielectric material is chemically bonded across a transition region to the first dielectric material, according to an example embodiment.
  • FIG. 4 shows the composition as a function of thickness for an example surface converted sidewall spacer, including a highly simplified depiction of the chemical bonding provided across the thickness of the surface converted sidewall spacer, according to an example embodiment.
  • FIG. 1 is a flow chart that shows steps in an example method 100 for fabricating an IC device having MOS transistors that include surface converted sidewall spacers, according to an example embodiment.
  • Step 101 comprises depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon comprising a gate electrode on a gate dielectric.
  • Step 102 comprises etching the first dielectric material to form sidewall spacers on sidewalls of the gate stack, such as using RIE.
  • Step 103 comprises chemically converting a top surface of the first dielectric material to a second dielectric material by adding at least one element to provide surface converted sidewall spacers.
  • the second dielectric material is chemically bonded across a transition region to the first dielectric material.
  • the chemically converted top surface of the sidewall spacer becomes an etch stop by adding at least one element to form a second dielectric material, that substantially increases the wet etch resistance of the film as compared to the unconverted first dielectric material, such as to a hot phosphoric acid (HP A) etch.
  • the added element is carbon. In another embodiment both carbon and oxygen are added.
  • the first dielectric material comprises BTBAS- derived silicon nitride, and carbon is added to the top surface of the silicon nitride forming a thin layer, typically 10 to 20 Angstroms thick, of a second dielectric material comprising a silicon carbide (SiC), silicon carbonitride (SiCN) and/or silicon oxy-carbonitride (SiOCN) film.
  • SiC silicon carbide
  • SiCN silicon carbonitride
  • SiOCN silicon oxy-carbonitride
  • SiC, SiCN, or SiOCN were formed, which were all found to be are largely impervious to HPA etch at temperatures below 215 °C. Since HPA is generally used at temperatures between 120 and 180 °C, the underlying silicon nitride sidewall spacer is protected by the second dielectric material.
  • the relationship of the second dielectric material to the first dielectric material for disclosed surface converted sidewall spacers being chemically bonded together is distinct from known arrangements resulting from the vapor deposition (e.g., chemical vapor deposition) of a second dielectric material on a first dielectric material, where the second dielectric material becomes attached to the first dielectric material by comparatively weak Vander walls forces.
  • the area of the second dielectric material matches the area of the first dielectric material.
  • the area of the second dielectric material will be different as compared to the area of the first dielectric material due to the etching process required for spacer formation.
  • Step 104 comprises ion implanting to form lightly doped drains (LDDs) in the semiconductor surface lateral to the gate stack.
  • LDDs lightly doped drains
  • the PMOS transistors and NMOS transistors generally each receive separate LDD implants.
  • Step 105 comprises forming second spacers on the surface converted sidewall spacers.
  • Step 106 comprises forming sources and drains lateral to the gate stack. Ion implanting can be used to form sources and drains in the semiconductor surface lateral to the gate stack after forming the second spacers.
  • the PMOS transistors and NMOS transistors each receive separate source/drain implants.
  • Step 107 comprises selectively removing the second spacers after the source/drain formation (step 106).
  • the surface of chemically converted layer remains intact after the selective etching, as does the first dielectric material protected by the surface converted layer.
  • FIG. 2A-2F are cross-sectional diagrams showing processing progression for an example method of fabricating an IC device having surface converted sidewall spacers, according to an example embodiment, while FIG. 2G shows the resulting spacer structure after a known spacer process showing inadvertent removal of the sidewall spacer.
  • FIG. 2A shows a gate stack comprising a gate electrode 211 on a gate dielectric 212 before any sidewall spacer is formed on a substrate 305.
  • Substrate 305 can comprise any substrate material, such as silicon, silicon-germanium, as well as II-VI and III-V substrates, as well as SOI substrates.
  • the gate electrode 211 can comprise polysilicon, or a variety of other gate electrode materials.
  • the gate dielectric 212 can comprise a variety of gate dielectrics, including optional high-k dielectrics defined hereon as having k >3.9, typically a k > 7. In one particular embodiment, the high-k dielectric comprises silicon oxynitride.
  • FIG. 2B shows the gate stack after a sidewall spacer (e.g., a nitride offset spacer) 215 is formed, such as a silicon nitride offset spacer by a RIE process.
  • a sidewall spacer e.g., a nitride offset spacer
  • FIG. 2C shows the results after an ion implantation process, such as LDD ion implantation to form LDD regions 225, that utilized implant blocking provided by the sidewall spacer 215.
  • FIG. 2D shows the resulting structure after disclosed chemical surface conversion step comprising flowing a hydrocarbon gas that forms the surface converted layer 216 shown.
  • FIG. 2E shows the gate stack 211/212 after a subsequent disposable second spacer 235 is formed, such as by chemical deposition followed by RIE. For a typical CMOS process the PMOS transistors and NMOS transistors each then receive separate source/drain implants.
  • FIG. 2F shows the gate stack 212/211 after the disposable second spacer 235 has been selectively removed, such as by a hot (e.g., 120 to 180 °C) HPA etch. Note the surface converted layer 216 remains intact after the etch, as does the sidewall spacer 215 protected by the surface converted layer 216. Without a disclosed surface converted layer, the sidewall spacer 215, such as it comprises silicon nitride, is subject to removal using the process used to remove the disposable second spacer 235.
  • FIG. 2G shows the resulting spacer structure after a known spacer process showing the results after inadvertent complete removal of the sidewall spacer 215. [0021] FIG.
  • IC 300 includes MOS transistors having surface converted sidewall spacers comprising a second dielectric material on a first dielectric material, wherein the second dielectric material is chemically bonded across a transition region to the first dielectric material, according to an example embodiment.
  • BEOL Back end of the line
  • IC 300 includes a substrate 305, such as a p-type silicon or p-type silicon-germanium substrate, having a semiconductor surface 306.
  • Optional trench isolation 308 is shown, such as shallow trench isolation (STI).
  • An n-channel MOS (NMOS) transistor 310 is shown, along with a p-channel MOS (PMOS) transistor 320 that is within an n-well 307.
  • NMOS transistor 310 includes a gate stack including a gate electrode 311 on a gate dielectric 312 having sidewall spacers on sidewalls of the gate stack.
  • the sidewall spacers comprise a second dielectric material 315a on a first dielectric material 315b, wherein the second dielectric material 315a is chemically bonded across a transition region 315c to the first dielectric material 315b.
  • the second dielectric material 315a comprises carbon and the first dielectric material does not comprise carbon, wherein "not comprising carbon” as used herein refers to a wt. % of C ⁇ 3 %.
  • NMOS transistor 310 includes source 321 and drain 322 regions lateral to the sidewall spacers, and include lightly doped extensions 321a and 322a.
  • a silicide layer 316 is shown on the gate electrode 311 and the source 321 and drain 322.
  • PMOS transistor 320 includes a gate stack including a gate electrode 331 on a gate dielectric 332 (which can be the same material as gate dielectric 312 under gate electrode 311) having sidewall spacers on sidewalls of the gate stack, comprising the second dielectric material 315a on a first dielectric material 315b, wherein the second dielectric material 315a is chemically bonded across a transition region 315c to the first dielectric material 315b.
  • the second dielectric material 315a comprises carbon and the first dielectric material does not comprise carbon.
  • PMOS transistor 320 includes source 341 and drain 342 regions lateral to the sidewall spacers, and include lightly doped extensions 341a and 342a.
  • Silicide layer 316 is shown on the gate electrode 331 and on the source 341 and drain 342.
  • the total thickness of the sidewall spacer 315a/315c/315b at its widest point at its base is generally ⁇ 100 Angstroms, such as 40 to 70 Angstroms thick.
  • second dielectric material 315a is about 5 to 10 angstroms thick
  • transition region 315c is 15 to 25 Angstroms thick
  • the first dielectric material 315b is 20 to 30 Angstroms thick.
  • FIG. 4 shows the composition as a function of thickness for an example surface converted sidewall spacer 400, including a highly simplified depiction of the chemical bonding provided across the thickness of the surface converted sidewall spacer 400, according to an example embodiment.
  • the surface converted sidewall spacer 400 includes a non-constant chemical composition profile across its thickness comprising a first dielectric material 315b on the sidewall of a gate stack material and a chemically converted top (outer) surface comprising a second dielectric material 315a chemically bonded across a transition region 315c to the first dielectric material 315b.
  • the first dielectric material 315b comprises silicon nitride (roughly Si 3 N 4 )
  • the second dielectric material 315a comprises silicon carbide (SiC)
  • the transition region 315c includes a material comprising Si, N and C, where the C content decreases and the N content increases as the distance to the second dielectric material 315a /gate stack is reduced.
  • Disclosed semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc.
  • the semiconductor die can be formed from a variety of processes including bipolar, CMOS, BiCMOS and MEMS.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

L'invention concerne un procédé (100) de fabrication d'un circuit intégré qui consiste à déposer (101) un premier matériau diélectrique sur une surface semi-conductrice d'un substrat recouvert d'un empilement de grille comprenant une électrode de grille sur un diélectrique de grille. Le premier matériau diélectrique est gravé (102) pour former des entretoises latérales sur les parois latérales de l'empilement de grille. La surface supérieure du premier matériau diélectrique est transformée chimiquement (103) en un deuxième matériau diélectrique en ajoutant au moins un élément pour obtenir des entretoises latérales à surface transformée. Le deuxième matériau diélectrique est lié chimiquement à travers une région de transition au premier matériau diélectrique.
PCT/US2012/030977 2011-03-28 2012-03-28 Circuit intégré comportant une surface d'entretoise modifiée chimiquement Ceased WO2012135363A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2014502758A JP2014514757A (ja) 2011-03-28 2012-03-28 化学的に改変されたスペーサ表面を有する集積回路

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201161468308P 2011-03-28 2011-03-28
US61/468,308 2011-03-28
US13/427,062 2012-03-22
US13/427,062 US9496359B2 (en) 2011-03-28 2012-03-22 Integrated circuit having chemically modified spacer surface

Publications (2)

Publication Number Publication Date
WO2012135363A2 true WO2012135363A2 (fr) 2012-10-04
WO2012135363A3 WO2012135363A3 (fr) 2012-12-06

Family

ID=46932319

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2012/030977 Ceased WO2012135363A2 (fr) 2011-03-28 2012-03-28 Circuit intégré comportant une surface d'entretoise modifiée chimiquement

Country Status (2)

Country Link
JP (4) JP2014514757A (fr)
WO (1) WO2012135363A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104952725A (zh) * 2014-03-24 2015-09-30 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7019085B1 (ja) 2021-04-26 2022-02-14 Dmg森精機株式会社 工作機械

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3811518B2 (ja) * 1995-01-12 2006-08-23 松下電器産業株式会社 半導体装置およびその製造方法
JP2002246463A (ja) * 2001-02-13 2002-08-30 Sony Corp 半導体装置の製造方法及び半導体装置
KR100416628B1 (ko) * 2002-06-22 2004-01-31 삼성전자주식회사 게이트 스페이서를 포함하는 반도체 소자 제조 방법
US6806149B2 (en) * 2002-09-26 2004-10-19 Texas Instruments Incorporated Sidewall processes using alkylsilane precursors for MOS transistor fabrication
JP2004134687A (ja) * 2002-10-15 2004-04-30 Toshiba Corp 半導体装置及びその製造方法
US6812073B2 (en) * 2002-12-10 2004-11-02 Texas Instrument Incorporated Source drain and extension dopant concentration
KR20040051696A (ko) * 2002-12-11 2004-06-19 주식회사 하이닉스반도체 반도체소자의 스페이서 형성방법
JP2004200550A (ja) * 2002-12-20 2004-07-15 Renesas Technology Corp 半導体装置の製造方法
JP4193638B2 (ja) * 2003-08-20 2008-12-10 ソニー株式会社 半導体装置の製造方法および半導体装置
US6991979B2 (en) * 2003-09-22 2006-01-31 International Business Machines Corporation Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs
US7229869B2 (en) * 2005-03-08 2007-06-12 Texas Instruments Incorporated Method for manufacturing a semiconductor device using a sidewall spacer etchback
JP2007053296A (ja) * 2005-08-19 2007-03-01 Elpida Memory Inc 半導体装置及びその製造方法
US7371649B2 (en) * 2005-09-13 2008-05-13 United Microelectronics Corp. Method of forming carbon-containing silicon nitride layer
JP2007157870A (ja) * 2005-12-02 2007-06-21 Renesas Technology Corp 半導体装置及びその製造方法
JP2008047820A (ja) * 2006-08-21 2008-02-28 Toshiba Corp 半導体装置の製造方法および半導体装置
JP2008117848A (ja) * 2006-11-01 2008-05-22 Nec Electronics Corp 半導体装置の製造方法
JP2009140967A (ja) * 2007-12-03 2009-06-25 Panasonic Corp 半導体装置の製造方法
JP2009170751A (ja) * 2008-01-18 2009-07-30 Fujitsu Ltd 半導体装置の製造方法
US8138045B2 (en) * 2008-05-19 2012-03-20 Texas Instruments Incorporated Method of forming sidewall spacers to reduce formation of recesses in the substrate and increase dopant retention in a semiconductor device
JP2010118500A (ja) * 2008-11-13 2010-05-27 Toshiba Corp 半導体装置及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104952725A (zh) * 2014-03-24 2015-09-30 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法

Also Published As

Publication number Publication date
JP2014514757A (ja) 2014-06-19
JP6534163B2 (ja) 2019-06-26
JP2019145825A (ja) 2019-08-29
JP2021073735A (ja) 2021-05-13
JP7157835B2 (ja) 2022-10-20
JP2017143302A (ja) 2017-08-17
JP6916430B2 (ja) 2021-08-11
WO2012135363A3 (fr) 2012-12-06

Similar Documents

Publication Publication Date Title
US10483261B2 (en) Integrated circuit having chemically modified spacer surface
CN102549755B (zh) 具有氧扩散阻挡层的半导体器件及其制造方法
US8450834B2 (en) Spacer structure of a field effect transistor with an oxygen-containing layer between two oxygen-sealing layers
US8237231B2 (en) Device with aluminum surface protection
US8258587B2 (en) Transistor performance with metal gate
US8659089B2 (en) Nitrogen passivation of source and drain recesses
US8324090B2 (en) Method to improve dielectric quality in high-k metal gate technology
US20120025323A1 (en) Spacer structures of a semiconductor device
US8802523B2 (en) CMOS device and fabrication method
US9748235B2 (en) Gate stack for integrated circuit structure and method of forming same
JP5569173B2 (ja) 半導体装置の製造方法及び半導体装置
CN101388399A (zh) 混合取向技术互补金属氧化物半导体结构及其制造方法
US9595585B2 (en) Methods for high-k metal gate CMOS with SiC and SiGe source/drain regions
US8569185B2 (en) Method of fabricating gate electrode using a treated hard mask
US7190033B2 (en) CMOS device and method of manufacture
US20140015063A1 (en) Method for Forming Gate Structure, Method for Forming Semiconductor Device, and Semiconductor Device
US20060166457A1 (en) Method of making transistors and non-silicided polysilicon resistors for mixed signal circuits
US7741168B2 (en) Systems and methods for fabricating nanometric-scale semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks
JP7157835B2 (ja) 化学的に改変されたスペーサ表面を有する集積回路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12763401

Country of ref document: EP

Kind code of ref document: A2

ENP Entry into the national phase

Ref document number: 2014502758

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12763401

Country of ref document: EP

Kind code of ref document: A2