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WO2012132064A1 - Élément photovoltaïque - Google Patents

Élément photovoltaïque Download PDF

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Publication number
WO2012132064A1
WO2012132064A1 PCT/JP2011/072452 JP2011072452W WO2012132064A1 WO 2012132064 A1 WO2012132064 A1 WO 2012132064A1 JP 2011072452 W JP2011072452 W JP 2011072452W WO 2012132064 A1 WO2012132064 A1 WO 2012132064A1
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WIPO (PCT)
Prior art keywords
layer
amorphous silicon
type amorphous
transparent conductive
silicon layer
Prior art date
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Ceased
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PCT/JP2011/072452
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English (en)
Japanese (ja)
Inventor
豊 桐畑
藤田　和範
嶋田　聡
三島　孝博
仁 坂田
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Publication date
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H10F77/219—Arrangements for electrodes of back-contact photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H10F10/166—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a photovoltaic device.
  • Patent Document 1 discloses a semiconductor substrate having a light receiving surface and a back surface provided on the opposite side of the light receiving surface, a first semiconductor layer formed along a predetermined direction on the back surface, and a back surface.
  • a pair of second semiconductor layers formed along a predetermined direction and disposed on both sides of the first semiconductor layer, and from one second semiconductor layer to the first semiconductor layer of the pair of second semiconductor layers
  • a photovoltaic device comprising a transparent electrode layer covering a second semiconductor layer and a collecting electrode layer formed on the transparent electrode layer is disclosed.
  • an insulating layer or the like may be stacked on a semiconductor layer formed on a semiconductor substrate.
  • residues such as the insulating layer may adhere to the semiconductor layer.
  • the residue of the insulating layer may increase the series resistance between the semiconductor layer and the collecting electrode portion.
  • a photovoltaic element includes a crystalline semiconductor substrate and a first conductivity type layer, and is laminated on the surface in a first region of one surface of the crystalline semiconductor substrate.
  • a second amorphous semiconductor layer that includes a semiconductor layer portion and a second conductivity type layer and is stacked over the second region on one surface and a part of the first amorphous semiconductor layer portion And a conductive layer disposed between a part of the first amorphous semiconductor layer portion and the second amorphous semiconductor layer portion.
  • the power generation characteristics of the photovoltaic element can be improved.
  • 1st Embodiment of this invention it is sectional drawing of a photovoltaic device.
  • 1st Embodiment of this invention it is a flowchart which shows the procedure of the manufacturing method of a photovoltaic device.
  • 1st Embodiment of this invention it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device.
  • 1st Embodiment of this invention it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device.
  • 1st Embodiment of this invention it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. In 1st Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. In 1st Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. In 1st Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. In 1st Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device.
  • 2nd Embodiment of this invention it is sectional drawing of a photovoltaic device.
  • 2nd Embodiment of this invention it is a flowchart which shows the procedure of the manufacturing method of a photovoltaic device.
  • 2nd Embodiment of this invention it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device.
  • 2nd Embodiment of this invention it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device.
  • 2nd Embodiment of this invention it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. In 2nd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. In 2nd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. In 2nd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. In 2nd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device.
  • FIG. 1 is a cross-sectional view of the photovoltaic element 10.
  • the photovoltaic device 10 includes an antireflection layer 12, an n-type amorphous silicon layer 14, an i-type amorphous silicon layer 16, an n-type single crystal silicon substrate 18, an in-layer stack portion 21, An ip laminated portion 31, a transparent conductive layer 20, an n-side electrode portion 25, and a p-side electrode portion 35 are provided.
  • an arrow A shown in FIG. 1 indicates a direction in which light such as sunlight is incident on the photovoltaic element 10.
  • the “light receiving surface” means a surface on which light such as sunlight is mainly incident.
  • the “back surface” means a surface opposite to the light receiving surface.
  • the n-type single crystal silicon substrate 18 is a power generation layer that receives light incident from the light receiving surface side and generates carriers.
  • the n-type single crystal silicon substrate 18 is used.
  • the present invention is not limited to this, and a wafer-like semiconductor substrate made of a crystalline semiconductor material of n-type or p-type conductivity is used. be able to.
  • a polycrystalline silicon substrate, a gallium arsenide substrate (GaAs), an indium phosphorus substrate (InP), or the like can be used.
  • the i-type amorphous silicon layer 16 is formed on the light-receiving surface of the n-type single crystal silicon substrate 18.
  • the i-type amorphous silicon layer 16 is a passivation layer containing hydrogen.
  • the n-type amorphous silicon layer 14 is formed on the i-type amorphous silicon layer 16.
  • the i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 constitute an amorphous semiconductor layer portion formed on the light receiving surface.
  • the i-type amorphous silicon layer 16 is a layer made of an intrinsic amorphous semiconductor film.
  • the i-type amorphous silicon layer 16 has a lower dopant concentration in the film than the n-type amorphous silicon layer 14.
  • the i-type amorphous silicon layer 16 preferably has a low n-type or p-type dopant concentration and a dark conductivity of 10 ⁇ 9 S / cm or less.
  • the n-type amorphous silicon layer 14 is a layer made of an amorphous semiconductor film containing an n-type conductive dopant.
  • the n-type amorphous silicon layer 14 has a higher n-type dopant concentration in the film than the i-type amorphous silicon layer 16.
  • the n-type amorphous silicon layer 14 preferably has a dark conductivity of 10 ⁇ 5 S / cm or more.
  • the amorphous silicon layer may include a microcrystalline structure.
  • the microcrystalline structure is a structure in which crystal grains are precipitated in an amorphous semiconductor.
  • the average grain size of the crystal grains is not limited to this, but is estimated to be about 1 nm to 80 nm.
  • the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 and reduces reflection of light incident from the light receiving surface side of the photovoltaic element 10.
  • the antireflection layer 12 also functions as a protective layer that protects the surface of the n-type amorphous silicon layer 14.
  • the antireflection layer 12 is made of a material having translucency for light in a wavelength range that can be absorbed by the n-type single crystal silicon substrate 18. Further, it is preferable to use a material having a refractive index and a film thickness that reduce reflection of light incident from the light receiving surface of the photovoltaic element 10 in relation to the refractive index of the layer covered by the antireflection layer 12. .
  • the antireflection layer 12 includes, for example, aluminum nitride, silicon nitride, silicon oxide, silicon oxynitride, and the like.
  • the photovoltaic element 10 can receive light over substantially the entire light receiving surface of the n-type single crystal silicon substrate 18.
  • the i-n laminated portion 21 is formed on the back surface of the n-type single crystal silicon substrate 18. It is preferable that the i-n laminated portion 21 is arranged so that current can be collected evenly from the surface of the photovoltaic element 10 in an n-side electrode portion 25 described later.
  • the i-n stacked portion 21 preferably has a comb-teeth shape in which a plurality of finger portions extend in parallel.
  • the i-n stacked unit 21 includes an i-type amorphous silicon layer 22 and an n-type amorphous silicon layer 23.
  • the i-type amorphous silicon layer 22 is a passivation layer formed on the back surface of the n-type single crystal silicon substrate 18.
  • the n-type amorphous silicon layer 23 is formed on the i-type amorphous silicon layer 22.
  • the i-n stacked portion 21 constitutes a first amorphous semiconductor layer portion formed on the back surface.
  • the i-type amorphous silicon layer 22 is a layer made of an intrinsic amorphous semiconductor film.
  • the i-type amorphous silicon layer 22 has a lower dopant concentration in the film than the n-type amorphous silicon layer 23.
  • the i-type amorphous silicon layer 22 preferably has a low n-type or p-type dopant concentration and a dark conductivity of 10 ⁇ 9 S / cm or less.
  • the n-type amorphous silicon layer 23 is a layer made of an amorphous semiconductor film containing an n-type conductive dopant.
  • the n-type amorphous silicon layer 23 has a higher n-type dopant concentration in the film than the i-type amorphous silicon layer 22.
  • the n-type amorphous silicon layer 23 preferably has a dark conductivity of 10 ⁇ 5 S / cm or more.
  • the transparent conductive layer 20 is formed on the n-type amorphous silicon layer 23.
  • the transparent conductive layer 20 includes at least one of metal oxides such as indium oxide (In 2 O 3 ), zinc oxide (ZnO), tin oxide (SnO 2 ), and titanium oxide (TiO 2 ).
  • ITO indium tin oxide
  • the n-side electrode part 25 is an electrode part provided for collecting and taking out the electricity generated in the photovoltaic element 10.
  • the n-side electrode unit 25 includes a transparent conductive layer 26, a metal layer 27, a first electrode unit 28, and a second electrode unit 29.
  • the transparent conductive layer 26 is formed on the transparent conductive layer 20.
  • the transparent conductive layer 26 includes at least one of metal oxides such as indium oxide (In 2 O 3 ), zinc oxide (ZnO), tin oxide (SnO 2 ), and titanium oxide (TiO 2 ).
  • ITO indium tin oxide
  • the metal layer 27 is formed on the transparent conductive layer 26.
  • the metal layer 27 is a seed layer including a metal such as copper (Cu) or an alloy, for example.
  • the “seed layer” refers to a layer that is a starting point for plating growth.
  • the first electrode portion 28 is an electrode formed on the metal layer 27 by plating growth.
  • the first electrode unit 28 includes, for example, copper (Cu).
  • the second electrode part 29 is an electrode formed on the first electrode part 28 by plating growth.
  • the second electrode unit 29 includes tin (Sn).
  • the i-p stacked portion 31 is formed on the back surface of the n-type single crystal silicon substrate 18 so as to be inserted into the i-n stacked portion 21.
  • the ip laminated portion 31 is formed from the back surface of the n-type single crystal silicon substrate 18 to the edge of the i-n laminated portion 21. That is, in the photovoltaic element 10, a part of the laminated structure of the ip laminated part 31 and the in laminated part 21 exists.
  • the ip stacked portion 31 is arranged so that current can be collected evenly from within the surface of the photovoltaic element 10.
  • the ip laminated portion 31 is preferably, for example, in a comb-teeth shape in which a plurality of finger portions extend in parallel.
  • the ip laminated portion 31 includes an i-type amorphous silicon layer 32 and a p-type amorphous silicon layer 33.
  • the i-type amorphous silicon layer 32 is a passivation layer formed on the back surface of the n-type single crystal silicon substrate 18.
  • the p-type amorphous silicon layer 33 is formed on the i-type amorphous silicon layer 32.
  • the ip stacked portion 31 constitutes a second amorphous semiconductor layer portion formed on the back surface.
  • the i-type amorphous silicon layer 32 is a layer made of an intrinsic amorphous semiconductor film.
  • the i-type amorphous silicon layer 32 has a lower dopant concentration in the film than the p-type amorphous silicon layer 33.
  • the i-type amorphous silicon layer 32 preferably has a low n-type or p-type dopant concentration and a dark conductivity of 10 ⁇ 9 S / cm or less.
  • the p-type amorphous silicon layer 33 is a layer made of an amorphous semiconductor film containing a p-type conductive dopant.
  • the p-type amorphous silicon layer 33 has a higher p-type dopant concentration in the film than the i-type amorphous silicon layer 32.
  • the p-type amorphous silicon layer 33 preferably has a dark conductivity of 10 ⁇ 8 s / cm or more.
  • the p-side electrode part 35 is an electrode part provided for collecting and taking out the electricity generated in the photovoltaic element 10.
  • the p-side electrode part 35 includes a transparent conductive layer 36, a metal layer 37, a first electrode part 38, and a second electrode part 39.
  • the transparent conductive layer 36 is formed on the p-type amorphous silicon layer 33.
  • the metal layer 37 is formed on the transparent conductive layer 36.
  • the first electrode portion 38 is formed on the metal layer 37 by plating growth.
  • the second electrode portion 39 is formed on the first electrode portion 38 by plating growth.
  • the material and the like of the second electrode portion 39 are the same as those of the second electrode portion 29, detailed description thereof is omitted.
  • FIG. 2 is a flowchart showing the procedure of the method for manufacturing the photovoltaic element 10.
  • the manufacturing method of the photovoltaic element 10 is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, or a plating method can be appropriately used for forming each layer.
  • an n-type single crystal silicon substrate 18 is prepared, and the light receiving surface and the back surface of the n-type single crystal silicon substrate 18 are cleaned (S2).
  • the n-type single crystal silicon substrate 18 can be cleaned using, for example, an HF aqueous solution.
  • a texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18 (S4).
  • the texture structure can be performed using anisotropic etching or isotropic etching.
  • an i-type amorphous silicon layer 22a and an n-type amorphous silicon layer 23a are formed on the back surface of the n-type single crystal silicon substrate 18, and thereafter, an n-type single crystal silicon layer 23a is formed.
  • the i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 are formed on the light receiving surface of the crystalline silicon substrate 18 (S6).
  • a transparent conductive layer 20a is formed on the n-type amorphous silicon layer 23a (S8).
  • the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 (S10).
  • a part of the transparent conductive layer 20a is etched (S12). Specifically, the transparent conductive layer 20 is formed by removing a portion of the transparent conductive layer 20a located on a region where the ip stacked portion 31 is bonded to the n-type single crystal silicon substrate 18 in a later step.
  • the etching of the transparent conductive layer 20a uses, for example, an acidic etching solution such as hydrochloric acid (HCl).
  • the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a are etched (S14). Specifically, portions of the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a other than the portion covered with the transparent conductive layer 20 are removed. As a result, the portion of the back surface of the n-type single crystal silicon substrate 18 where the transparent conductive layer 20 is not located is exposed, and the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23 are formed. Form.
  • an alkaline etching solution such as an aqueous solution containing sodium hydroxide (NaOH) is used.
  • the transparent conductive layer 20, the i-type amorphous silicon layer 22, the n-type amorphous silicon layer 23 and the exposed back surface of the n-type single crystal silicon substrate 18 are covered.
  • the i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a are formed (S16).
  • a portion of the i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a located on the transparent conductive layer 20 is etched (S18). . Thereby, the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 are formed.
  • the transparent conductive layer 26a and the metal layer 27a are formed (S20).
  • the transparent conductive layers 26 and 36 and the metal layers 27 and 37 are separated by dividing a portion of the transparent conductive layer 26 a and the metal layer 27 a located on the transparent conductive layer 20. Is formed (S22).
  • the transparent conductive layer 26a and the metal layer 27a are divided by, for example, a lithography method.
  • the first electrode portion 28 and the second electrode portion 29 are sequentially formed on the metal layer 27 by electrolytic plating, and the first electrode portion 38 and the second electrode portion 29 are formed on the metal layer 37.
  • the electrode portions 39 are sequentially formed (S24). Thereby, the n-side electrode part 25 and the p-side electrode part 35 are formed.
  • the carrier mobility is low in the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23.
  • the carrier mobility is higher in the transparent conductive layer 20 than in the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23.
  • carriers are preferably discharged from the n-side electrode portion 25 by compensating for the low carrier mobility in the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23. It can be taken out.
  • the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23, and the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 are electrically connected via the transparent conductive layer 20.
  • the n-side electrode since the carrier mobility is low in the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33, the n-side electrode has a high carrier mobility. Since the carrier can be suitably taken out from the portion 25, the electrical connection as described above does not cause a significant problem.
  • an insulating layer is not formed on the in laminated portion 21 on the back surface side. Therefore, there is no step of etching the insulating layer, and the residue of the insulating layer does not adhere to the transparent conductive layer 20, the i-type amorphous silicon layer 22, or the n-type amorphous silicon layer 23. Thereby, it is possible to prevent the series resistance between the in-stacked portion 21 and the n-side electrode portion 25 of the photovoltaic element 10 from increasing due to the presence of the insulating layer residue. Therefore, the power generation characteristics of the photovoltaic element 10 can be improved.
  • FIG. 11 is a cross-sectional view of a photovoltaic element 11 according to the second embodiment of the present invention.
  • the photovoltaic device 11 includes an antireflection layer 12, an n-type amorphous silicon layer 14, an i-type amorphous silicon layer 16, an n-type single crystal silicon substrate 18, an in-layer stack portion 21, It includes an ip laminated portion 31, a transparent conductive layer 20, an insulating layer 24, an n-side electrode portion 25, and a p-side electrode portion 35.
  • an arrow A shown in FIG. 11 indicates a direction in which light such as sunlight is incident on the photovoltaic element 11.
  • the insulating layer 24 is formed to electrically insulate the i-n laminated portion 21 and the ip laminated portion 31.
  • the insulating layer 24 also functions as a protective layer formed on the transparent conductive layer 20.
  • the insulating layer 24 may be any material having electrical insulation properties, and preferably includes, for example, aluminum nitride, silicon nitride, silicon oxide, silicon oxynitride, and the like.
  • FIG. 12 is a flowchart showing the procedure of the method for manufacturing the photovoltaic element 11.
  • the manufacturing method of the photovoltaic element 11 is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, a plating method, or the like can be used as appropriate.
  • the manufacturing method of the photovoltaic element 11 and the manufacturing method of the photovoltaic element 10 are the same in the steps S2 to S8. And since the difference between the manufacturing method of the photovoltaic element 11 and the manufacturing method of the photovoltaic element 10 is a process after S8, it demonstrates centering on the difference.
  • steps S2 to S8 are performed.
  • the insulating layer 24a is formed on the transparent conductive layer 20a, and the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 (S30).
  • the insulating layer 24a is etched to remove a part of the insulating layer 24a (S32). Specifically, the insulating layer 24b is formed by removing a portion of the insulating layer 24a located above a region for bonding the ip stacked portion 31 to the n-type single crystal silicon substrate 18 in a later step.
  • an acidic etching solution such as an HF aqueous solution is used for the etching of the insulating layer 24a.
  • the transparent conductive layer 20a is etched using the insulating layer 24b patterned in S32 as a mask (S34). Thereby, the patterned transparent conductive layer 20 is formed.
  • the same steps as S14, S16, and S18 of the first embodiment are performed except that the insulating layer 24b is present on the transparent conductive layer 20.
  • the transparent conductive layer 20 patterned in S34 as a mask
  • the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a are used. Is etched (S36).
  • An i-type amorphous silicon layer 32a and a p-type amorphous silicon layer 33a are formed so as to cover the back surface of the silicon substrate 18 (S38). Thereafter, as shown in FIG. 18, as in S18, a part of the portion of the i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a located on the insulating layer 24b is etched. (S40).
  • a part of the insulating layer 24b is further removed by etching the insulating layer 24b (S42).
  • the insulating layer 24 is formed by removing the exposed portion of the insulating layer 24b by etching using the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 as a mask.
  • the exposed surface of the transparent conductive layer 20 is cleaned (S44). Thereby, even if it is a case where the residue of the insulating layer 24a has adhered to the transparent conductive layer 20, in S42, it can remove suitably.
  • the cleaning of the exposed surface of the transparent conductive layer 20 can be performed using, for example, an HF aqueous solution.
  • the transparent conductive layer 26a and the metal layer 27a are formed (S46). Subsequently, as shown in FIG. 20, similarly to S22, the transparent conductive layers 26 and 36 and the metal layer 27a and the metal layer 27a are separated from each other by dividing a part located on the insulating layer 24. Layers 27 and 37 are formed (S48). After that, as shown in FIG. 21, the first electrode portion 28 and the second electrode portion 29 are sequentially formed on the metal layer 27 by electrolytic plating as in S24, and the first electrode is formed on the metal layer 37. The part 38 and the second electrode part 39 are formed (S50). Thereby, the n-side electrode part 25 and the p-side electrode part 35 are formed.
  • the carrier mobility is low in the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23.
  • the carrier mobility is higher in the transparent conductive layer 20 than in the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23.
  • carriers are preferably discharged from the n-side electrode portion 25 by compensating for the low carrier mobility in the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23. It can be taken out.
  • the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23, and the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 are electrically connected via the transparent conductive layer 20.
  • the n-side electrode since the carrier mobility is low in the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33, the n-side electrode has a high carrier mobility. Since the carrier can be suitably taken out from the portion 25, the electrical connection as described above is not particularly problematic.
  • an insulating layer 24 is formed on the transparent conductive layer 20 on the back side of the photovoltaic element 11. That is, the transparent conductive layer 20 is interposed between the n-type amorphous silicon layer 23 and the insulating layer 24.
  • the transparent conductive layer 20 has higher HF resistance than the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23. For this reason, even if the residue of the insulating layer 24 remains on the transparent conductive layer 20 by etching the insulating layer 24, the residue is removed by the process of S44. Further, even when the transparent conductive layer 20 is washed using an HF aqueous solution, the transparent conductive layer 20 is hardly damaged by the HF aqueous solution.
  • the residue can be eliminated by appropriately selecting a cleaning solution that can remove the residue of the insulating layer 24.
  • a cleaning solution that can remove the residue of the insulating layer 24.
  • the insulating layer 24 is formed on the transparent conductive layer 20 on the back surface side of the photovoltaic element 11, the insulating performance between the in laminated portion 21 and the ip laminated portion 31 is improved. be able to.
  • FIG. 22 is a cross-sectional view of a photovoltaic element 11a according to the third embodiment of the present invention.
  • the photovoltaic element 11a includes an antireflection layer 12, an n-type amorphous silicon layer 14, an i-type amorphous silicon layer 16, an n-type single crystal silicon substrate 18, an i-n stacked portion 21, It includes an ip laminated portion 31, a transparent conductive layer 20, an insulating layer 40, an n-side electrode portion 25 and a p-side electrode portion 35.
  • an arrow A shown in FIG. 22 indicates a direction in which light such as sunlight is incident on the photovoltaic element 11a.
  • the insulating layer 40 is formed to electrically insulate the i-n laminated portion 21 and the i-p laminated portion 31.
  • the insulating layer 40 also functions as a protective layer formed on the transparent conductive layer 20.
  • the insulating layer 40 is formed so that the back surface and side surface of the transparent conductive layer 20 may be covered so that the back surface and side surface of the transparent conductive layer 20 may not be exposed, as FIG. 22 shows.
  • the “side surface” means a surface along the thickness direction of the transparent conductive layer 20.
  • the insulating layer 40 may be any material having electrical insulating properties, but preferably includes, for example, aluminum nitride, silicon nitride, silicon oxide, silicon oxynitride, and the like.
  • FIG. 23 is a flowchart showing a procedure of a manufacturing method of the photovoltaic element 11a.
  • the manufacturing method of the photovoltaic element 11a is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, or a plating method can be appropriately used for forming each layer.
  • the manufacturing method of the photovoltaic element 11a and the manufacturing method of the photovoltaic element 11 are the same in the steps S2 to S8. And since the difference between the manufacturing method of the photovoltaic element 11a and the manufacturing method of the photovoltaic element 11 is the process after S8, it demonstrates centering on the difference.
  • steps S2 to S8 are performed.
  • the transparent conductive layer 20a is etched using a patterning mask as shown in FIG. 24 (S30a).
  • the insulating layer 40a is formed on the transparent conductive layer 20, and the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 (S32a).
  • the insulating layer 40a is etched by using a patterning mask designed in advance so as to leave a portion where the side surface of the transparent conductive layer 20 is covered with the insulating layer 40a. Is removed (S34a).
  • the insulating layer 40b is formed by removing a portion of the insulating layer 40a located on a region where the ip stacked portion 31 is bonded to the n-type single crystal silicon substrate 18 in a later step.
  • step S34a since the mask used in step S34a is designed in advance so that the width of the insulating layer 40b is larger than the width of the transparent conductive layer 20, the insulating layer 40b is transparent conductive as shown in FIG. The back surface and side surface of the transparent conductive layer 20 are covered so that the back surface and side surface of the layer 20 are not exposed.
  • an acidic etching solution such as an HF aqueous solution is used for the etching of the insulating layer 40a.
  • the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a are etched (S36a). Specifically, portions of the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a other than the portions covered by the transparent conductive layer 20 and the insulating layer 40b are removed. As a result, the portion of the back surface of the n-type single crystal silicon substrate 18 where the transparent conductive layer 20 and the insulating layer 40b are not located is exposed, so that the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer are exposed. A silicon layer 23 is formed.
  • steps S38 to S40 are performed in the same manner as in the method of manufacturing the photovoltaic element 11.
  • the insulating layer 40b is etched to further remove a part of the insulating layer 40b (S42a).
  • steps S44 to S50 are performed in the same manner as in the method of manufacturing the photovoltaic element 11.
  • the photovoltaic element 11a shown in FIG. 27 is formed.
  • the photovoltaic element 11a has the transparent conductive layer 20 with high carrier mobility, it is possible to suitably take out carriers from the n-side electrode portion 25 as in the photovoltaic elements 10 and 11.
  • the residue of the insulating layer 40 can be removed using an HF aqueous solution in the same manner as the photovoltaic element 11. Thereby, it is possible to prevent an increase in series resistance between the i-n stacked portion 21 and the n-side electrode portion 25 of the photovoltaic element 11a.
  • the photovoltaic element 11a not only the back surface of the transparent conductive layer 20 but also the side surfaces thereof are covered with the insulating layer 40, so that the insulating performance between the in laminated portion 21 and the ip laminated portion 31 is improved. Further improvement can be achieved.
  • the ip stack part 31 is stacked on a part of the in stack part 21, but the present invention is not limited to this.
  • the i-n laminated part 21 may be laminated on a part of the ip laminated part 31 by forming the ip laminated part 31 first and then forming the i-n laminated part 21.
  • the i-n laminated portion 21 may be formed of only an n-type amorphous layer. May be composed of only a p-type amorphous layer.
  • the transparent conductive layer 20 instead of the transparent conductive layer 20, using a metal layer with high electroconductivity and high HF resistance, for example, copper (Cu), silver (Ag), etc. Also good.
  • a metal layer with high electroconductivity and high HF resistance for example, copper (Cu), silver (Ag), etc. Also good.
  • n-type amorphous silicon layer 16 i-type amorphous silicon layer, 18 n-type single crystal silicon substrate, 20, 20a transparent conductive layer, 21 i -N stacked portion, 22, 22a i-type amorphous silicon layer, 23, 23a n-type amorphous silicon layer, 24, 24a, 24b insulating layer, 25 n-side electrode portion, 26, 26a, 36 transparent conductive layer, 27, 27a, 37 metal layer, 28, 38 first electrode part, 29, 39 second electrode part, 31 ip stacked part, 32, 32a i-type amorphous silicon layer, 33, 33a p-type amorphous Silicon layer, 35 p-side electrode part, 40a, 40b insulating layer.

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  • Photovoltaic Devices (AREA)

Abstract

L'invention concerne un élément photovoltaïque (10) comprenant un stratifié i-n (21) stratifié sur la surface d'une première région de surface d'un substrat de silicium monocristallin de type n (18) ; un stratifié i-p (31) stratifié chevauchant une seconde région de la surface et une partie du stratifié i-n (21) ; et une couche conductrice transparente (20) disposée entre une partie du stratifié i-n (21) et le stratifié in-n (21).
PCT/JP2011/072452 2011-03-25 2011-09-29 Élément photovoltaïque Ceased WO2012132064A1 (fr)

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JP2011067832 2011-03-25
JP2011-067832 2011-03-25

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018168180A1 (fr) * 2017-03-17 2018-09-20 株式会社カネカ Cellule solaire et son procédé de fabrication

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009096539A1 (fr) * 2008-01-30 2009-08-06 Kyocera Corporation Élément de batterie solaire et procédé de fabrication d'élément de batterie solaire
JP2009200267A (ja) * 2008-02-21 2009-09-03 Sanyo Electric Co Ltd 太陽電池
WO2010113750A1 (fr) * 2009-03-30 2010-10-07 三洋電機株式会社 Pile solaire
JP2010258043A (ja) * 2009-04-21 2010-11-11 Sanyo Electric Co Ltd 太陽電池

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009096539A1 (fr) * 2008-01-30 2009-08-06 Kyocera Corporation Élément de batterie solaire et procédé de fabrication d'élément de batterie solaire
JP2009200267A (ja) * 2008-02-21 2009-09-03 Sanyo Electric Co Ltd 太陽電池
WO2010113750A1 (fr) * 2009-03-30 2010-10-07 三洋電機株式会社 Pile solaire
JP2010258043A (ja) * 2009-04-21 2010-11-11 Sanyo Electric Co Ltd 太陽電池

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018168180A1 (fr) * 2017-03-17 2018-09-20 株式会社カネカ Cellule solaire et son procédé de fabrication

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