WO2012118177A1 - Synchronization device, time management method, and computer program - Google Patents

Abstract

A synchronization device that synchronizes the time with another device by transmitting and receiving a synchronization packet to and from the other device in accordance with a synchronization protocol, the synchronization device including: a transmit/receive unit that transmits and receives the synchronization packet; a clock signal acquisition unit that acquires a clock signal flowing over a communication channel; a synchronization control unit that acquires the difference between the time of the device itself and the time of the other device on the basis of the synchronization packet; and a time management unit that corrects the time of the device itself on the basis of said difference, and that manages the time of the device itself on the basis of the corrected time and the clock signal.

Description

Synchronization device, time management method, and computer program

The present invention relates to a technique for synchronizing time between devices that perform communication.

Conventionally, a technique for synchronizing time between communication devices located at physically separated positions has been proposed (see Patent Document 1). As an example of such a technique, there is a technique using a packet for synchronization processing (synchronization packet). FIG. 7 is a diagram illustrating a configuration example of the time synchronization apparatus 90 related to the above technique. The time synchronization apparatus 90 includes a synchronization packet transmission / reception unit 901, a synchronization control unit 902, a clock oscillator 904, and a time management unit 905. The time synchronization device 90 keeps the time counted by the time management unit 905 with a certain accuracy by the clock oscillator 904 provided in the time synchronization device 90. That is, the time synchronization is maintained only by the clock signal of the clock oscillator 904 during the interval (time synchronization interval) at which the phase signal is generated in response to reception of the synchronization packet.

JP 2010-062992 A

There is a request to keep the time accuracy of the own device managed by the time management unit 905 higher. As a method for solving such a requirement, there is a method including a clock oscillator 904 with higher accuracy. There is also a method of shortening the time synchronization interval by frequently transmitting and receiving synchronization packets. However, there was a problem with either method. In the former case, an increase in cost due to the provision of the clock oscillator 904 with high accuracy in each time synchronization device 90 becomes a problem. In the latter case, high performance is required from the master device that is the communication partner of the synchronization packet. In the latter case, the bandwidth of the communication path between the master device and the time synchronization device 90 is further consumed by the synchronization packet.
In view of the above circumstances, an object of the present invention is to provide a technique that can increase the accuracy of time synchronization between communication devices without significantly increasing the device cost and the communication frequency of synchronization packets.

One aspect of the present invention is a synchronization device that synchronizes time with the other device by transmitting and receiving a synchronization packet according to a synchronization protocol with another device, and a transmission and reception unit that transmits and receives the synchronization packet; Based on the clock signal acquisition unit that acquires the clock signal flowing through the communication path, the synchronization control unit that acquires the difference between the time of its own device and the time of the other device, based on the synchronization packet, and the difference A time management unit that corrects the time of the own device and manages the time of the own device based on the corrected time and the clock signal.

One aspect of the present invention is a time management method performed by a synchronization device that synchronizes time with another device by transmitting and receiving a synchronization packet with the other device according to a synchronization protocol, and transmits and receives the synchronization packet. A transmission / reception step, a clock signal acquisition step of acquiring a clock signal flowing through the communication path, a synchronization control step of acquiring a difference between the time of the own device and the time of the other device based on the synchronization packet, A time management step of correcting the time of the own device based on the difference and managing the time of the own device based on the corrected time and the clock signal.

One aspect of the present invention is a computer program for operating a computer as a synchronization device that synchronizes time with the other device by transmitting and receiving a synchronization packet with the other device according to a synchronization protocol. A transmission / reception step for transmitting and receiving a packet, a clock signal acquisition step for acquiring a clock signal flowing through a communication path, and a synchronization for acquiring a difference between the time of the own device and the time of the other device based on the synchronization packet A computer for causing the computer to execute a control step and a time management step of correcting the time of the own device based on the difference and managing the time of the own device based on the corrected time and the clock signal It is a program.

According to the present invention, it is possible to increase the accuracy of time synchronization between communication devices without significantly increasing the device cost and the communication frequency of synchronization packets.

It is a system configuration figure showing the system configuration of a first embodiment of a synchronous system. FIG. 3 is a sequence diagram showing a communication sequence by an IEEE 1588 time synchronization algorithm. It is a functional block diagram showing the structure of a time synchronous slave apparatus. It is a flowchart showing the flow of operation | movement of a time synchronous slave apparatus. It is a system configuration figure showing the system configuration of a second embodiment of a synchronous system. It is a functional block diagram showing the structure of the time synchronous slave apparatus in 2nd embodiment. It is a figure which shows the structural example of the time synchronization apparatus of related technology.

[First embodiment]
FIG. 1 is a system configuration diagram showing a system configuration of the first embodiment (synchronization system 100) of the synchronization system. The synchronization system 100 includes a clock generator 10, a time synchronization master device 20 (corresponding to “another device” of the present invention), a relay device 30, and a time synchronization slave device 40 (corresponding to “a synchronization device” of the present invention). . In FIG. 1, the synchronization system 100 includes one device, but the number of devices included in the synchronization system 100 is not limited to one. Further, the number of relay devices 30 provided between the time synchronization master device 20 and the time synchronization slave device 40 is not limited to one, and may be two or more.

First, an outline of the synchronization system 100 will be described. The time synchronization master device 20 and the time synchronization slave device 40 transmit and receive synchronization packets according to a predetermined protocol. The time synchronization master device 20 and the time synchronization slave device 40 perform time synchronization by transmitting and receiving synchronization packets. The predetermined protocol may be any protocol as long as time synchronization is possible. Specific examples of the predetermined protocol include IEEE 1588, IEEE 1588 version 2, and the like.
The time synchronization slave device 40 counts the time based on the clock signal between the time synchronization and the next time synchronization. The time synchronization slave device 40 outputs a time synchronization signal every time a predetermined time is reached. The clock signal used by the time synchronization slave device 40 to count the time is a clock signal that flows through the communication path between the relay device 30 and the time synchronization slave device 40. Therefore, the time synchronization slave device 40 does not need to include a clock signal generation device (for example, a clock oscillator) that outputs a clock signal for generating a time synchronization signal, and can maintain high time accuracy.

Next, IEEE1588 will be described as one specific example of the above-described time synchronization protocols.
FIG. 2 is a sequence diagram showing a communication sequence based on the IEEE 1588 time synchronization algorithm. In FIG. 2, a clock master (corresponding to a time synchronization master device) and a clock slave (corresponding to a time synchronization slave device) perform bidirectional communication, and the clock slave periodically synchronizes the time with the clock master. In FIG. 2, each message (Sync message, Follow_up message, Delay_Request message, Delay_Response message) transmitted from the clock master or clock slave corresponds to a synchronization packet.

The clock master periodically sends a Sync message to the clock slave (step S900). The clock master records the transmission time of the Sync message (hereinafter referred to as “Sync transmission time”) Tm (0) (step S901). Next, the clock master transmits a Follow_up message to the clock slave (step S903). At this time, the clock master stores the Sync transmission time Tm (0) in the Follow_up message.

Upon receiving the Sync message, the clock slave records the reception time of the Sync message (hereinafter referred to as “Sync reception time”) Ts (0) using this reception process as a trigger (step S902). Next, the clock slave receives the Follow_up message and extracts and records the Sync transmission time Tm (0) stored in the Follow_up message. Next, the clock slave transmits a Delay_Request message to the clock master (step S904). Then, the clock slave records the transmission time of the Delay_Request message (hereinafter referred to as “Delay transmission time”) Ts (1) (step S905).

Upon receiving the Delay_Request message, the clock master records the reception time of the Delay_Request message (hereinafter referred to as “Delay reception time”) Tm (1) using this reception process as a trigger (step S906). Next, the clock master transmits a Delay_Response message to the clock slave (step S907). At this time, the clock master stores the Delay reception time Tm (1) in the Delay_Response message.

When receiving the Delay_Response message, the clock slave extracts and records the Delay reception time Tm (1) stored in the Delay_Response message.
Based on the Sync transmission time Tm (0) and the Sync reception time Ts (0), the clock slave calculates the time at the clock master (hereinafter referred to as “master time”) and the time at the clock slave (hereinafter referred to as “master time”). MS_Diff with “slave time”).
MS_Diff = Ts (0)-Tm (0) = MS_Delay + Offset ・ ・ ・ Equation 1

Further, the clock slave obtains the difference between the slave time and the master time from the following equation 2 based on the Delay transmission time Ts (1) and the Delay reception time Tm (1).
SM_Diff = Tm (1)-Ts (1) = SM_Delay-Offset ・ ・ ・ Equation 2

Here, MS_Delay represents the transmission delay from the clock master to the clock slave, SM_Delay represents the transmission delay from the clock slave to the clock master, and Offset represents the time offset (advance) of the clock slave with respect to the clock master. The transmission delays MS_Delay and SM_Delay are composed of a propagation delay between the clock master and the clock slave and a queuing delay that occurs at a relay node on the network between the clock master and the clock slave.

As described above, two formulas of Formula 1 and Formula 2 are obtained with respect to Offset, which is a time lag of the clock slave with respect to the clock master. However, these two equations include unknown parameters MS_Delay and SM_Delay in addition to Offset. Therefore, since there are only two equations for the three unknown parameters, Offset cannot be calculated. Therefore, in IEEE1588, assuming that the transmission delay MS_Delay from the clock master to the clock slave is equal to the transmission delay SM_Delay from the clock slave to the clock master, and both values are delays, the above equations 1 and 2 Is transformed into the following equations 3 and 4.

MS_Diff = Delay + Offset ・ ・ ・ Equation 3
SM_Diff = Delay-Offset ・ ・ ・ Equation 4
By solving the simultaneous equations of Equation 3 and Equation 4, the following Equation 5 is derived.
Offset = (MS_Diff-SM_Diff) / 2 ... Formula 5

The clock slave calculates the offset based on Equation 5 and corrects the slave time based on the offset to synchronize the slave time with the master time. The above is the time synchronization algorithm defined in IEEE1588.

Next, details of the synchronization system 100 will be described. The clock generator 10 supplies a clock signal to the time synchronization master device 20 and the relay device 30. The clock generator 10 is preferably a high-accuracy clock generator that generates a clock signal with high accuracy. The clock generator 10 may be a GPS (Global Positioning System) receiver, for example, or may be configured using a high-performance oscillator.
The time synchronization master device 20 operates in synchronization with the clock signal output from the clock generator 10. The time synchronization master device 20 operates according to a predetermined protocol, and performs time synchronization with the time synchronization slave device 40 by transmitting and receiving synchronization packets. The time synchronization processing synchronizes the time in the time synchronization master device 20 (hereinafter referred to as “master device time”) and the time in the time synchronization slave device 40 (hereinafter referred to as “slave device time”). .

The relay device 30 is a clock synchronous communication device, and performs packet relay processing in synchronization with the clock signal output from the clock generator 10. For example, the relay device 30 relays packets according to a synchronous communication method such as SDH (Synchronous Digital Hierarchy) or Synchronous Ethernet (registered trademark). More specifically, the relay device 30 synchronizes its own clock with the clock signal received from the communication path, and transmits the signal to the communication path at the same frequency. The communication path between the relay device 30 and the time synchronization slave device 40 is clock-synchronized according to the clock signal output by the clock generator 10, and a clock signal having a predetermined cycle is propagated. For example, in the case of an Ethernet (registered trademark) 100BASE-TX interface, a clock signal flows through the communication path at 125 MHz.
The relay device 30 relays the synchronization packet received from the time synchronization master device 20 to the time synchronization slave device 40. The relay device 30 relays the synchronization packet received from the time synchronization slave device 40 to the time synchronization master device 20.

The time synchronization slave device 40 transmits / receives a synchronization packet to / from the time synchronization master device 20 via the relay device 30 and performs time synchronization with the time synchronization master device 20. In addition, the time synchronization slave device 40 acquires a synchronized clock signal from the communication path with the relay device 30. The time synchronization slave device 40 outputs a time synchronization signal synchronized with the time synchronization master device 20 based on the result of the time synchronization and the clock signal acquired from the communication path. The destination to which the time synchronization slave device 40 outputs the time synchronization signal may be a network to which the time synchronization slave device 40 is connected, or may be a device to which the time synchronization slave device 40 is connected. Further, the time synchronization slave device 40 may be incorporated in the device as one component. In this case, the time synchronization slave device 40 outputs a time synchronization signal to other parts of the device in which the device is incorporated.

FIG. 3 is a functional block diagram showing the configuration of the time synchronization slave device 40. The time synchronization slave device 40 includes a CPU (Central Processing Unit) connected via a bus, a memory, an auxiliary storage device, and the like, and executes a time synchronization program. By executing the time synchronization program, the time synchronization slave device 40 includes a synchronization packet transmission / reception unit 401 (corresponding to “transmission / reception unit” of the present invention), a synchronization control unit 402, a first clock signal extraction unit 403 (“clock signal of the present invention” It corresponds to an apparatus provided with a second clock signal generation unit 404 and a time management unit 405. All or some of the functions of the time synchronization slave device 40 may be realized using hardware such as ASIC (Application Specific Integrated Circuit), PLD (Programmable Logic Device), and FPGA (Field Programmable Gate Array). good. The time synchronization program may be recorded on a computer-readable recording medium. The computer-readable recording medium is, for example, a portable medium such as a flexible disk, a magneto-optical disk, a ROM, a CD-ROM, or a storage device such as a hard disk built in the computer system.

The synchronization packet transmission / reception unit 401 receives the synchronization packet from the communication path with the relay device 30 and transfers the synchronization packet to the synchronization control unit 402. In addition, the synchronization packet transmission / reception unit 401 sends the synchronization packet received from the synchronization control unit 402 to the communication path. The synchronization packet sent to the communication path by the synchronization packet transmitting / receiving unit 401 is relayed by the relay device 30 and received by the time synchronization master device 20.

The synchronization control unit 402 synchronizes the slave device time with the master device time by exchanging synchronization packets with the time synchronization master device 20 at the end of the communication path. The synchronization control unit 402 outputs a phase signal representing the difference between the slave device time before synchronization and the master device time to the time management unit 405 as a result of the time synchronization.

The first clock signal extraction unit 403 extracts a clock signal from the physical layer signal received from the communication path. The first clock signal extraction unit 403 outputs the extracted clock signal to the second clock signal generation unit 404 as the first clock signal.
The second clock signal generation unit 404 generates a second clock signal synchronized with the first clock signal output from the first clock signal extraction unit 403. The second clock signal generation unit 404 generates the second clock signal by multiplying or dividing the first clock signal. The second clock signal is a clock signal used by the time management unit 405 to count the slave device time.

The time management unit 405 manages the slave device time. Specifically, the time management unit 405 counts the slave device time based on the second clock signal received from the second clock signal generation unit 404. The time management unit 405 generates and outputs a time synchronization signal at a predetermined time. When receiving the phase signal from the synchronization control unit 402, the time management unit 405 corrects the slave device time based on the received phase signal. By correcting the slave device time, the output timing of the time synchronization signal is corrected. The time management unit 405 corrects the slave device time based on the phase signal, and then receives the phase signal until the next time the phase signal is received, the slave device based on the second clock signal received from the second clock signal generation unit 404 Count the time. For this reason, if a shift occurs in the second clock signal, the slave device time being counted also shifts, and the timing at which the time synchronization signal is output shifts. This deviation is corrected based on the next phase signal.

Next, the operation flow of the time synchronization slave device 40 will be described. FIG. 4 is a flowchart showing an operation flow of the time synchronization slave device 40. The synchronization control unit 402 performs time synchronization by transmitting and receiving a synchronization packet to and from the time synchronization master device 20 at a predetermined timing. The synchronization control unit 402 outputs a phase signal representing a difference between the slave device time and the master device time to the time management unit 405 as a result of the time synchronization (step S101). The time management unit 405 corrects the slave device time based on the phase signal (step S102).

The second clock signal generation unit 404 continues to output the second clock signal to the time management unit 405 (steps S103, S105, S109). The time management unit 405 determines the output timing of the time synchronization signal based on the corrected slave device time and the second clock signal. Then, the time management unit 405 outputs a time synchronization signal at the determined output timing (steps S104, S106, S110).

When a new phase signal is output from the synchronization control unit 402 (step S107), the time management unit 405 performs time correction based on the new phase signal (step S108). Thereafter, the time management unit 405 counts the slave device time based on the slave device time corrected in step S108 and the second clock signal (step S109) output from the second clock signal generation unit 404. When a predetermined time comes, a time synchronization signal is output (step S110).

In the above synchronization system 100, the second clock signal used by the time management unit 405 to count the slave device time is synchronized with the clock signal (first clock signal) extracted from the communication path. Therefore, by making the clock signal flowing in the communication path into a high-accuracy clock signal, each time synchronization slave device 40 does not have a high-accuracy clock signal generator, and the slave is based on the high-accuracy clock signal. The device time can be counted. Therefore, in order to maintain highly accurate time synchronization, it is not necessary to shorten the interval between transmission and reception of synchronization packets.

The clock signal flowing in the communication path is synchronized with the clock signal input to the time synchronization master device 20. Therefore, once the time synchronization by the transmission / reception of the synchronization packet is performed once, the time synchronization master device 20 and the time synchronization slave device are not newly transmitted / received unless the clock signal flowing through the communication path is shifted. It is possible to maintain a synchronization state with 40.

<Modification>
The clock signal flowing through the communication path need not be limited to a clock signal as a synchronization signal used for transmission / reception of the relay device 30. For example, even if the relay device 30 is not a clock synchronous communication device, it may be configured so that a clock signal flows through the communication path. Therefore, in this case, the relay device 30 is not necessarily a clock synchronous communication device.

[Second Embodiment]
FIG. 5 is a system configuration diagram showing a system configuration of the second embodiment (synchronization system 100a) of the synchronization system. In the synchronization system 100a, the clock signal used by the time synchronization slave device 40a is not the clock signal extracted from the communication path between the relay device 30 and the time synchronization slave device 40a, but the clock synchronization to which the clock generator 10 is connected. It differs from the synchronization system 100 of the first embodiment in that it is extracted from the network 50. Hereinafter, the synchronization system 100a of the second embodiment will be described in detail.
The clock generator 10 is connected to the clock synchronization network 50 and supplies a clock signal to the clock synchronization network 50.
The relay device 30a is a general packet transmission device, and relays synchronous packets without clock synchronization.

FIG. 6 is a functional block diagram showing the configuration of the time synchronization slave device 40a in the second embodiment. The time synchronization slave device 40a is different from the time synchronization slave device 40 of the first embodiment in that a first clock signal extraction unit 403a is provided instead of the first clock signal extraction unit 403. The remaining configuration of the time synchronization slave device 40a is the same as that of the time synchronization slave device 40 of the first embodiment.

The first clock signal extraction unit 403a extracts the first clock signal based on the signal received from the clock synchronization network 50, not the communication path through which the synchronization packet is transmitted and received.
In the second embodiment, the first clock signal for generating the second clock signal is extracted from the clock synchronization network 50 instead of the communication path through which the synchronization packet is transmitted and received. Therefore, even when a failure occurs in the communication path through which the synchronization packet is transmitted and received, the time synchronization slave device 40 is counted by counting the time based on the first clock signal extracted from the clock synchronization network 50. It is possible to prevent the time of the time from deviating significantly.

<Modification>
In the synchronization system 100 a of the second embodiment, the clock synchronization network 50 may be configured by a clock synchronization type transmission network that can operate in synchronization with the clock generator 10.
The relay device 30a of the second embodiment may perform synchronization packet relay by clock synchronization.
The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.
This application claims priority on March 3, 2011 based on Japanese Patent Application No. 2011-046155 for which it applied to Japan, and uses the content here.

The present invention can be applied to a system or a device that synchronizes time between devices that perform communication.

100, 100a ... synchronization system 10 ... clock generator 20 ... time synchronization master device (other device)
30, 30a ... Relay device 40, 40a ... Time synchronization slave device (synchronization device)
401... Synchronous packet transmission / reception unit (transmission / reception unit)
402: Synchronization control units 403, 403a ... First clock signal extraction unit (clock signal acquisition unit)
404 ... Second clock signal generation unit 405 ... Time management unit

Claims (6)

A synchronization device that synchronizes time with the other device by transmitting and receiving a synchronization packet according to a synchronization protocol with the other device,
A transmission / reception unit for transmitting / receiving the synchronization packet;
A clock signal acquisition unit for acquiring a clock signal flowing through the communication path;
Based on the synchronization packet, a synchronization control unit that acquires a difference between the time of its own device and the time of the other device;
A time management unit that corrects the time of the own device based on the difference, and manages the time of the own device based on the corrected time and the clock signal;
A synchronization device comprising: The synchronization device according to claim 1, wherein the time management unit determines a predetermined timing based on the time of the own device and outputs a signal at the predetermined timing. The synchronization device according to claim 1 or 2, wherein the clock signal acquisition unit acquires the clock signal based on an electrical signal flowing through the communication network. The synchronization device according to any one of claims 1 to 3, wherein the clock signal acquisition unit acquires a clock signal flowing through a communication path through which the synchronization packet is transmitted. A time management method performed by a synchronization device that synchronizes time with the other device by transmitting and receiving a synchronization packet according to a synchronization protocol with the other device,
A transmission / reception step of transmitting / receiving the synchronization packet;
A clock signal acquisition step for acquiring a clock signal flowing through the communication path;
Based on the synchronization packet, a synchronization control step for obtaining a difference between the time of the own device and the time of the other device;
A time management step of correcting the time of the own device based on the difference and managing the time of the own device based on the corrected time and the clock signal;
A time management method. A computer program for operating a computer as a synchronization device that synchronizes time with the other device by transmitting and receiving a synchronization packet with the other device according to a synchronization protocol,
A transmission / reception step of transmitting / receiving the synchronization packet;
A clock signal acquisition step for acquiring a clock signal flowing through the communication path;
Based on the synchronization packet, a synchronization control step for obtaining a difference between the time of the own device and the time of the other device;
A time management step of correcting the time of the own device based on the difference and managing the time of the own device based on the corrected time and the clock signal;
A computer program for causing the computer to execute.

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