WO2012032613A1

WO2012032613A1 - Design aiding apparatus for semiconductor device

Info

Publication number: WO2012032613A1
Application number: PCT/JP2010/065381
Authority: WO
Inventors: 明広後藤; 松嶋　弘倫; 裕史堀部; 萩原　靖久; 紘宇下川; 義雄松田; 一欽岡留
Original assignee: ルネサスエレクトロニクス株式会社
Priority date: 2010-09-08
Filing date: 2010-09-08
Publication date: 2012-03-15

Abstract

A design aiding apparatus (100) is provided with an input unit (10), a generating unit (20), and a detection unit (30). The input unit (10) receives a first data (CAD model (11)) for expressing a three-dimensional shape of a semiconductor device, and a second data (resin injection position (12) and wire drifting rate (13)) for expressing deformation of a plurality of wires that are deformed due to resin that are injected into a mold to seal a semiconductor chip and the wires. The generating unit (20) generates a third data (wire drifting model (21)) for expressing the three-dimensional shape of the semiconductor device after the wires have been deformed, by updating shape data of the plurality of wires contained in the first data, on the basis of the second data. The detection unit (30) detects, on the basis of the third data, whether first and second wires that come in contact with each other are included in the plurality of wires.

Description

Design support equipment for semiconductor devices

The present invention relates to a semiconductor device design support device, and more particularly to a technique for designing bonding of a plurality of wires connected to a semiconductor chip and a substrate frame.

Generally, a semiconductor device includes a semiconductor chip, a substrate frame (also referred to as a lead frame), a bonding wire (hereinafter simply referred to as “wire”), and a sealing resin. The assembly process of the semiconductor device mainly includes a die bonding process, a wire bonding process, and a sealing process.

In the die bonding process, the semiconductor chip is mounted on the substrate frame and fixed to the substrate frame. In the wire bonding step, the bonding pads formed on the semiconductor chip and the bonding pads formed on the substrate frame are connected by wires. In the sealing step, the semiconductor chip and the wire are sealed with resin.

In the sealing step, generally, a substrate frame on which a semiconductor chip is mounted is mounted on a mold, and then liquefied resin is injected into the mold from the mold inlet. In some cases, a phenomenon occurs in which the wire is stretched along the resin flow direction. This phenomenon is called wire sweep (or wire deformation).

When a wire flow occurs, for example, two adjacent wires come into contact with each other, thereby causing a problem such as an electrical short. For this reason, in the design of a semiconductor device, in order to avoid contact between wires due to wire flow, measures are taken such as increasing the spacing between the wires. However, on the other hand, such a measure is a factor that hinders downsizing of the semiconductor device.

For example, Japanese Patent Laying-Open No. 2004-363439 (Patent Document 1) discloses a technique related to the arrangement of bonding pads of a semiconductor chip. Specifically, the bonding pad spacing in the vicinity of the corner portion of the semiconductor chip is set in consideration of the amount of wire flow.

For example, Japanese Patent Laying-Open No. 2005-31159 (Patent Document 2) discloses a technique related to the shape of a wire. Specifically, two types of wires having different wire heights at the center of the semiconductor chip are alternately arranged.

For example, Japanese Patent Laying-Open No. 2005-101669 (Patent Document 3) discloses a technique related to the structure of a substrate frame. Specifically, the inner lead is fixed to the heat sink. This eliminates the need for a lead for supporting the tab on which the semiconductor chip is mounted, so that the tip of the inner lead can be brought closer to the semiconductor chip. Since the length of the wire can be shortened by bringing the tip of the inner lead close to the tip of the semiconductor chip, the wire flow can be suppressed.

For example, Japanese Patent Application Laid-Open No. 10-95899 (Patent Document 4) and Japanese Patent Application Laid-Open No. 2000-26708 (Patent Document 5) disclose a sealing resin (epoxy resin composition) excellent in moldability. By using such a resin, it is possible to suppress the wire flow.

For example, Japanese Patent Laying-Open No. 2004-93279 (Patent Document 6) discloses a technique related to inspection of a semiconductor device after a sealing process. Specifically, a solder ball image is extracted from an X-ray fluoroscopic image of an IC (integrated circuit). Next, a composite image in which the solder ball image portion is masked from the original X-ray fluoroscopic image is generated. A wire image is extracted from the synthesized image. Thereby, even if a solder ball image is included in the X-ray fluoroscopic image, the state of the wire can be inspected.

For example, Japanese Patent Application Laid-Open No. 2006-107105 (Patent Document 7), Japanese Patent Application Laid-Open No. 2007-94511 (Patent Document 8), and Japanese Patent Application Laid-Open No. 2003-297870 (Patent Document 9) disclose semiconductor device design support devices. To do. Specifically, Patent Document 7 discloses a method for determining an optimum wiring position from each pad on a semiconductor substrate to a corresponding via portion. Patent Document 8 describes a connection relationship between a plurality of first electrodes included in a package substrate and a plurality of second electrodes formed on a semiconductor substrate, as well as a relative position between the plurality of first electrodes and a plurality of second electrodes. Disclosed is a method for determining based on the relative position between the second electrodes. Patent Document 9 discloses a design support apparatus including a verification unit that verifies whether a designed wire satisfies a predetermined condition.

JP 2004-363439 A JP 2005-31159 A JP 2005-101669 A Japanese Patent Laid-Open No. 10-95899 JP 2000-26708 A JP 2004-93279 A JP 2006-107105 A JP 2007-94511 A JP 2003-297870 A

As described above, regarding the technique for suppressing the flow of the wire, the structure of the substrate frame or the shape of the wire has been proposed so far. However, according to the prior art, in order to confirm whether or not the contact between the wires occurs due to the wire flow, the semiconductor device must be manufactured (including trial manufacture). Furthermore, when contact between wires due to wire flow is confirmed, it is necessary to redesign the semiconductor device. In the design stage of a semiconductor device, a technique for confirming contact between wires due to wire flow has not been proposed so far.

The present invention is for solving the above-described problems, and an object of the present invention is to provide a technique for verifying the possibility of adjacent wires coming into contact with each other by wire flow in the design stage of a semiconductor device. .

In one aspect, the present invention is a design support device for a semiconductor device including a semiconductor chip and a plurality of wires connected between the semiconductor chip and the substrate frame. The design support apparatus includes an input unit, a generation unit, and a detection unit. The input unit includes first data for expressing the three-dimensional shape of the semiconductor device, and first data for expressing the deformation of the wire due to the resin injected into the mold for sealing the semiconductor chip and the plurality of wires. 2 data is received. The generation unit generates third data for expressing the three-dimensional shape of the semiconductor device after the wire deformation has occurred based on the first and second data. The detection unit detects whether or not the plurality of wires include the first and second wires that are in contact with each other based on the third data.

In another aspect, the present invention is a design support method for a semiconductor device including a semiconductor chip and a plurality of wires connected between the semiconductor chip and the substrate frame. A design support method is for expressing first data for expressing a three-dimensional shape of a semiconductor device and deformation of a wire due to a resin injected into a mold for sealing a semiconductor chip and a plurality of wires. Receiving the second data; generating third data for expressing a three-dimensional shape of the semiconductor device after the deformation of the wire based on the first and second data; Detecting whether or not the first and second wires that are in contact with each other are included in the plurality of wires based on the third data.

According to the present invention, the possibility that two adjacent wires come into contact with each other by the wire flow can be verified at the design stage of the semiconductor device.

It is sectional drawing of the semiconductor device which can apply the design assistance apparatus which concerns on embodiment of this invention. It is a schematic diagram for demonstrating the sealing process of the semiconductor device 1 shown in FIG. 2 is a functional block diagram of the design support apparatus according to Embodiment 1. FIG. It is a top view which shows an example of the CAD model of the semiconductor device input into an input part. FIG. 5 is a perspective view of the semiconductor device shown in FIG. 4. It is the figure which showed the several candidate of the resin injection position. It is a figure for demonstrating the deformation | transformation of the wire by a wire flow. It is a side view of the wire before the wire flow occurs. It is the perspective view which showed the change of the shape of the wire by a wire flow. It is the figure which showed the example of the group as a unit by which a flow rate is set. It is a top view which shows an example of the CAD model (wire flow model) of the semiconductor device produced | generated by the production | generation part. FIG. 12 is a perspective view of the semiconductor device shown in FIG. 11. It is a figure for demonstrating schematically the 1st output processing by an output part. It is a figure for demonstrating schematically the 2nd output processing by an output part. It is a figure for demonstrating schematically the 3rd output processing by an output part. 4 is a flowchart for explaining wire flow verification processing by the design support apparatus according to the first embodiment. 6 is a functional block diagram of a design support apparatus according to Embodiment 2. FIG. 10 is a flowchart for explaining wire flow verification processing by the design support apparatus according to the second embodiment. 19 is a flowchart for explaining an example of a flow rate update process (step S44) illustrated in FIG. 18; 6 is a functional block diagram of a design support apparatus according to Embodiment 3. FIG. 10 is a flowchart for explaining wire flow verification processing by the design support apparatus according to the third embodiment. It is the figure which showed the structural example of the hardware for implement | achieving the design support apparatus according to embodiment of this invention. It is a schematic block diagram of the design support apparatus shown in FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

[Configuration of semiconductor device]
FIG. 1 is a cross-sectional view of a semiconductor device to which a design support apparatus according to an embodiment of the present invention can be applied. Referring to FIG. 1, a semiconductor device 1 includes a semiconductor chip 2, a die pad 3 A, a lead 3 B, a wire 4, a die bonding material 5, and a resin 6. The semiconductor chip 2 is fixed to the die pad 3 A by the die bonding material 5. The wire 4 connects the semiconductor chip 2 and the lead 3B. The resin 6 seals the semiconductor chip 2, the wire 4, the die pad 3A, and a part of the lead 3B.

FIG. 2 is a schematic diagram for explaining a sealing process of the semiconductor device 1 shown in FIG. Referring to FIG. 2, molds 7A1, 7A2, and 7B are prepared for sealing semiconductor chip 2 and the like with resin 6. The cavity 8A is formed by the molds 7A1 and 7B, and the cavity 8B is formed by the molds 7A2 and 7B. The semiconductor chip 2, the die pad 3A (and the die bonding material 5), the wire 4, and a part of the lead 3B are disposed in the cavity 8A (8B). The resin 6 becomes liquid when heated. The liquid resin 6 is pressed into the

cavities

8A and 8B by the plunger 9. Thereby, the semiconductor chip 2, the wire 4, the die pad 3 A, and a part of the lead 3 B are sealed with the resin 6.

The die pad 3A and the lead 3B are part of the substrate frame (lead frame). Although not shown in FIG. 2, after the sealing step, the lead tip portion of the substrate frame is cut from the connection portion of the substrate frame by lead cutting. Thereby, the individual semiconductor devices 1 are separated from the substrate frame.

When the resin 6 flows into the

cavities

8A and 8B, the wire 4 may be stretched along the direction in which the resin 6 flows. For this reason, there is a possibility that two wires arranged adjacent to each other come into contact with each other. When these wires come into contact with each other, an electrical short circuit occurs. Such an electrical short becomes a cause of the malfunction of the semiconductor device.

In the embodiment of the present invention, it is detected whether or not two adjacent wires are in contact with each other by the wire flow at the stage of designing the semiconductor device. Each embodiment will be described in detail below.

[Embodiment 1]
FIG. 3 is a functional block diagram of the design support apparatus according to the first embodiment. With reference to FIG. 3, the design support apparatus 100 includes an input unit 10, a generation unit 20, a detection unit 30, and an output unit 40.

The input unit 10 receives a CAD (Computer Aided Design) model 11, a resin injection position 12, and a wire flow rate 13. The CAD model 11 (CAD data) is design data for the semiconductor device 1. As will be described later, the CAD model 11 is data for representing the three-dimensional shape of the semiconductor device 1.

The resin injection position 12 is an injection position of the resin 6 injected into a resin sealing mold (corresponding to the molds 7A1, 7A2, and 7B in FIG. 2). The flow rate 13 is a value indicating the degree of deformation of the wire 4 due to the resin 6 flowing. The resin injection position 12 and the flow rate 13 are data for expressing the deformation of the wire due to the resin injected into the mold.

The generation unit 20 generates data representing the three-dimensional shape of the semiconductor device after the wire flow has occurred based on the data input to the input unit 10 (that is, the CAD model 11, the resin injection position 12, and the flow rate 13). Generate. This data is a wire flow model 21, specifically a CAD model. In the first embodiment, the generation unit 20 generates the wire flow model 21 by simulating the wire flow. The generation unit 20 generates the wire flow model 21 by updating the data on the shapes of the plurality of wires included in the CAD model 11 based on the resin injection position 12 and the flow rate 13.

Based on the wire flow model 21, the detection unit 30 detects whether or not the first and second wires that are in contact with each other are included in the plurality of wires. For example, the detection unit 30 selects two wires arranged next to each other and detects whether the two wires are in contact with each other.

The detection unit 30 includes a shortest distance measurement unit 31, a contact location detection unit 32, and an interference location detection unit 33.

The shortest distance measuring unit 31 detects the shortest distance between the two selected wires. Further, the shortest distance measuring unit 31 detects a place where the wires may contact each other when manufacturing variation is taken into consideration. Specifically, the shortest distance measuring unit 31 detects a place where the shortest distance is less than a reference value. This reference value is a value determined in advance based on manufacturing variations, for example, several μm. However, the reference value may be zero.

The contact location detector 32 detects whether or not the two selected wires are in contact with each other. The contact location detector 32 detects the shortest distance between the two selected wires. When the shortest distance between the two wires is 0, the contact location detection unit 32 detects that the two wires are in contact with each other. On the other hand, when the shortest distance between the two selected wires is greater than 0, the contact location detection unit 32 detects that the two wires are not in contact.

Interference location detector 33 detects whether or not the two selected wires interfere with each other. In the present invention, “interference” corresponds to a state in which one of the two wires is sunk into the other. In order to detect interference, a predetermined operation, for example, a Boolean operation is used.

The output unit 40 outputs the detection result of the detection unit 30. The output unit 40 includes a shortest distance output unit 41, a contact location output unit 42, and an interference location output unit 43.

The shortest distance output unit 41 outputs the shortest distance detected by the shortest distance measurement unit 31. Further, the shortest distance output unit 41 outputs information indicating a location where the shortest distance is less than the reference value.

The contact location output unit 42 outputs information indicating the contact location detected by the contact location detection unit 32. The interference location output unit 43 outputs information indicating the interference location detected by the interference location detection unit 33.

The output unit 40 is realized by a display device, for example. Specifically, the output unit 40 outputs the CAD model (wire flow model 21) generated by the generation unit 20. When the model includes at least one of a location where the shortest distance between the two wires is less than the reference value, a contact location, and an interference location, the output unit displays the at least one location. Further, the output unit 40 outputs the shortest distance between the selected two wires, and information indicating whether or not the two wires are in contact with each other, and the two wires interfere with each other. Outputs information indicating whether or not there is.

The output unit 40 only needs to have a function of outputting information to the outside. Therefore, the output unit 40 is not limited to a display device, and may be realized by a printer, for example.

Next, the operation of the design support apparatus according to the first embodiment will be described in detail.
FIG. 4 is a plan view illustrating an example of a CAD model of the semiconductor device input to the input unit. FIG. 5 is a perspective view of the semiconductor device shown in FIG. With reference to FIGS. 4 and 5, the CAD model 11 represents the semiconductor chip 2 and the plurality of wires 4. Each wire 4 is connected between a bonding pad 15 provided on the semiconductor chip 2 and a bonding pad 16 provided on the substrate frame 3.

When the resin injection position 12 (see FIG. 3) is input to the input unit 10, one position is selected in advance from a plurality of positions. FIG. 6 is a diagram showing a plurality of candidates for resin injection positions. Referring to FIG. 6, implantation positions 12A to 12D are an upper left position, a lower left position, an upper right position, and a lower right position with respect to semiconductor chip 2, respectively. The arrows in the figure indicate the direction of resin flow from the selected injection position.

The resin injection position 12 is selected in advance by the user from the injection positions 12A to 12D. However, the input unit 10 may have a function of allowing the user to select the resin injection position 12 from a plurality of injection positions.

In the present embodiment, the direction in which the wire flows can be estimated only by designating the resin injection position. Therefore, in the present embodiment, only the resin injection position 12 is input to the input unit 10 as information for simulating the resin flow. However, in order to express the flow of the resin, not only the injection position of the resin but also other information, for example, the direction in which the resin flows may be input to the input unit 10.

FIG. 7 is a diagram for explaining the deformation of the wire due to the wire flow. Referring to FIG. 7, a wire image 4A is a projected image of the wire 4 (not shown) connected between the

bonding pads

15 and 16 onto the XY plane. The wire image 4B is a projection image of the wire 4 (not shown) onto the XY plane after the wire flow has occurred. The XY plane may be replaced with the surface of the semiconductor chip or the surface of the substrate frame.

The wire image 4A is a straight line. In the present embodiment, the wire is deformed so that the wire image after the wire flow becomes an arc. Therefore, the wire image 4A corresponds to the string of the arc. Assuming that the length of the string is L and the displacement amount (flow amount) of the wire 4 due to the wire flow is M, the flow rate N (%) is obtained by the equation N = M / L × 100.

FIG. 8 is a side view of the wire before the wire flow occurs. FIG. 9 is a perspective view showing a change in the shape of the wire due to the wire flow. 8 and 9 show the shape of the wire expressed by the CAD model.

8 and 9, in the CAD model, the wire is specified by the coordinates of the position (bond point) where the wire is connected and the wire shape. FIG. 8 shows an example of the wire shape in the CAD model. The wire 4 is expressed on the CAD model as, for example, a broken line connecting the points P1, P2, P3, and P4. The point P1 is a bond point on the bonding pad 15 on the semiconductor chip. The point P4 is a bond point on the bonding pad 16 on the substrate frame. Points P2 and P3 correspond to bending points of the wire 4. In the examples shown in FIGS. 8 and 9, the wire shape can be expressed by setting the coordinates of the points P1 to P4.

By changing the shape of the wire 4, the shape of the wire 4 after the wire flow is generated can be represented by a CAD model. The wire 4C shown in FIG. 9 represents an example of the shape of the wire 4 after the wire flow has occurred. The shape of the wire 4 shown in FIGS. 8 and 9 is an example. For example, the shape of the wire may be a curve.

In the present embodiment, the flow rate 13 can be set according to any one of the following three methods. According to the first method, the same flow rate is set for a plurality of wires. According to the second method, a predetermined number (two or more) of wires form one group. Thus, a plurality of groups are configured. A flow rate is set for each group. Accordingly, the same number of flow rates as the number of groups are input to the input unit 10. According to the third method, the flow rate is set for each wire. Therefore, the same flow rate as the number of wires is input to the input unit 10.

FIG. 10 is a diagram showing an example of a group as a unit in which the flow rate is set. Referring to FIG. 10, group G 1 is configured by a predetermined number of wires located at corner portions of semiconductor device 1 (semiconductor chip 2). The group G2 is configured by a predetermined number of wires located in the straight line portion of the semiconductor device 1 (semiconductor chip 2). For example, the flow rate of the group G1 is a first value, and the flow rate of the group G2 is a second value different from the first value.

The generation unit 20 simulates the wire flow based on the CAD model 11, the resin injection position 12, and the flow rate 13 input to the input unit 10. As illustrated in FIG. 7, the generation unit 20 deforms the wire shape so that the straight line (4A) obtained by projecting the wire onto the plane becomes an arc (4B). The generation unit 20 generates an arc (4B) based on the flow rate 13 input to the input unit 10. The generation unit 20 reflects the result of simulating the shape of the wire in the CAD model 11. Thereby, the wire flow model 21 is generated.

FIG. 11 is a plan view showing an example of a CAD model (wire flow model) of the semiconductor device generated by the generation unit. FIG. 12 is a perspective view of the semiconductor device shown in FIG. Referring to FIGS. 11 and 12, resin is injected from the lower right of semiconductor chip 2 as indicated by an arrow. In the example shown in FIGS. 11 and 12, wire contact or interference occurs in the upper left portion (region 19 in the drawing) of the semiconductor chip 2. The detection unit 30 detects that the contact or interference of the wire has occurred in the region 19.

The detection unit 30 selects the first wire on the CAD model. Next, the detection unit 30 selects a second wire adjacent to the first wire. The detection unit 30 detects the shortest distance between the first and second wires. The shortest distance is calculated based on the shape of each of the first and second wires.

Furthermore, the detection unit 30 detects whether or not the first and second wires are in contact with each other. When the shortest distance is 0, the detection unit 30 detects that the first and second wires are in contact with each other. Furthermore, the detection unit 30 detects whether or not the first and second wires interfere with each other.

In many cases, the number of wires adjacent to one selected wire is plural. For this reason, the detection unit 30 performs the above-described processing for all the wires arranged adjacent to the selected one wire.

The output unit 40 outputs the detection result of the detection unit 30. FIG. 13 is a diagram for schematically explaining the first output processing by the output unit. With reference to FIG. 13, the wire flow model 21 generated by the generation unit 20 is output. Of the plurality of wires in the region 19, two wires whose shortest distance is less than the reference value, two wires in which contact has occurred, or two wires in which interference has occurred are emphasized. In order to avoid complication of the figure, FIG. 13 shows an example in which only the

wires

4D and 4E in contact with each other are emphasized. For example, the width of the line representing the

wires

4D and 4E is increased so that the

wires

4D and 4E can be easily distinguished from the surrounding wires. The colors of the

wires

4D and 4E may be different from the colors of the surrounding wires.

FIG. 14 is a diagram for schematically explaining the second output processing by the output unit. Referring to FIG. 14, the broken line indicates the shape of the wire 4 included in the CAD model before the wire flow is simulated (that is, the CAD model 11 input to the input unit 10). The solid line indicates the shape of the wire 4 included in the CAD model after the wire flow is simulated (that is, the wire flow model 21 generated by the generation unit 20). The output unit performs processing for overlapping and outputting the original CAD model and the CAD model after the wire flow is simulated. In order to avoid the complexity of the figure, FIG. 14 shows only a part of the plurality of wires included in the region 19 of FIG.

FIG. 15 is a diagram for schematically explaining the third output processing by the output unit. Referring to FIG. 15, the wire number (for example, wire number 1) of a certain wire, the wire number of the other end of the wire (for example,

wire numbers

2, 3, and 4), the shortest distance between the two wires, 2 The presence / absence of contact between the wires and the presence / absence of interference between the two wires are output.

FIG. 16 is a flowchart for explaining wire flow detection processing by the design support apparatus according to the first embodiment. Referring to FIGS. 3 and 16, input unit 10 receives CAD model 11, resin injection position 12, and flow rate 13 (step S10). The generation unit 20 simulates the wire flow state based on the CAD model 11, the resin injection position 12, and the flow rate 13 (step S20). The generation unit 20 generates a wire flow model 21 (CAD model) based on the simulation result (step S30). The wire flow model 21 is generated separately from the CAD model 11. However, the wire flow model 21 may be generated by updating the CAD model 11. The detection unit 30 uses the wire flow model 21 to detect the shortest distance between two adjacent wires and the contact or interference between the two adjacent wires (step S40). The output unit 40 outputs the detection result (step S50).

As described above, according to the first embodiment, the wire flow can be simulated using data (CAD model) representing the three-dimensional shape of the semiconductor device. Thereby, it is possible to verify the presence or absence of an electrical short between the wires in the design stage of the semiconductor device. This verification result can be reflected in the design of the semiconductor device. Specifically, the position (bond point) for connecting the wire and the shape of the wire are determined. For example, when two wires are in contact with each other, the position of the pad is designed so that the distance between the two wires is increased.

When a defect due to a wire flow is found at the stage of manufacturing a semiconductor device, it is necessary to redesign the semiconductor device. On the other hand, according to the first embodiment, it is possible to verify the possibility that adjacent wires come into contact with each other by the wire flow in the design stage of the semiconductor device. Therefore, according to the first embodiment, the design efficiency of the semiconductor device can be increased.

Further, according to the first embodiment, it is possible to appropriately design the interval between the plurality of bonding pads of the semiconductor chip in the design stage. For example, the interval between bonding pads can be made smaller than the value determined by the conventional design rule. As a result, the semiconductor chip can be miniaturized, and the semiconductor device can be miniaturized.

[Embodiment 2]
FIG. 17 is a functional block diagram of the design support apparatus according to the second embodiment. 3 and 17, design support apparatus 100A is different from design support apparatus 100 in that update unit 50 is further provided. Furthermore, the design support apparatus 100A is different from the design support apparatus 100A in that an output unit 40A is provided instead of the output unit 40. The configuration and function of other parts of the design support apparatus 100A are the same as the configuration and function of the corresponding part of the design support apparatus 100.

In the second embodiment, the input unit 10 receives the CAD model 11, the resin injection position 12, the shortest distance 17 between the wires, and the flow rate 13. The shortest distance 17 is the minimum distance at which two wires should be separated. The shortest distance 17 is determined based on, for example, a design rule. The shortest distance 17 is, for example, several μm, but may be 0.

The generation unit 20 simulates the wire flow based on the CAD model 11 input to the input unit 10, the resin injection position 12, and the flow rate. The generation unit 20 generates a wire flow model 21 based on the simulation result. Based on the wire flow model 21, the detection unit 30 detects whether or not the first and second wires that are in contact with each other are included in the plurality of wires.

The update unit 50 updates the flow rate 13 input to the input unit 10 based on the detection result of the detection unit 30. The update unit 50 feeds back the updated flow rate (flow rate 51) to the generation unit 20. The generation unit 20 recreates the wire flow model 21 using the flow rate 51, the CAD model 11, and the resin injection position 12.

When the shortest distance detected by the detection unit 30 is less than the shortest distance 17 input to the input unit 10, the update unit 50 updates the flow rate. Similarly, the update unit 50 also updates the flow rate when the contact or interference between the wires is detected by the detection unit 30. Until the shortest distance detected by the detection unit 30 is equal to the value (shortest distance 17) input to the input unit 10 and both the contact and interference between the wires are not detected, the flow rate of the update unit 50 is The update, generation of the wire flow model 21 by the generation unit 20, and detection of the shortest distance, contact, and interference by the detection unit 30 are repeated. Thereby, the flow rate satisfying the shortest distance 17 input to the input unit 10, that is, the flow rate for avoiding the contact of the two wires is determined.

The output unit 40A outputs the flow rate finally determined by the above processing (flow rate 52). Note that the flow rate input to the input unit 10, the flow rate at the stage of feedback from the update unit 50 to the generation unit 20, and the flow rate output from the output unit 40A may be different from each other. For this reason, in FIG. 17, different signs are assigned to these flow rates.

As in the first embodiment, the output method of the flow rate 52 by the output unit 40A is not particularly limited. For example, the output unit 40A is realized by a display device. In this case, the value of the flow rate 52 is displayed on the screen of the display device. The output unit 40A may be realized by a printer.

FIG. 18 is a flowchart for explaining wire flow verification processing by the design support apparatus according to the second embodiment. The processing flow shown in FIG. 18 differs from the processing flow shown in FIG. 16 in the following points. First, the process of step S11 is executed instead of the process of step S10. Secondly, processing in steps S42 and S44 is added. Thirdly, the process of step S51 is executed instead of the process of step S50. Since the processing of the other steps shown in FIG. 18 is the same as the processing of the corresponding steps shown in FIG. 16, detailed description will not be repeated hereinafter.

Referring to FIGS. 17 and 18, in step S11, input unit 10 receives CAD model 11, resin injection position 12, flow rate 13, and shortest distance 17 (step S11). The generation unit 20 simulates the wire flow state based on the information input to the input unit 10 (step S20), and generates the wire flow model 21 based on the simulation result (step S30). The detection unit 30 uses the wire flow model 21 to detect the shortest distance between two adjacent wires and the contact or interference between the two adjacent wires (step S40).

The update unit 50 determines whether or not the flow rate needs to be updated based on the detection result of the detection unit 30 (step S42). If it is determined that the flow rate needs to be updated (YES in step S42), the process proceeds to step S44. When the shortest distance detected by the detection unit 30 is different from the reference value, the update unit 50 determines that the flow rate needs to be updated. Furthermore, also when the detection unit 30 detects contact or interference between two wires, the update unit 50 determines that the flow rate needs to be updated.

In step S44, the update unit 50 updates the flow rate. The update method of the flow rate by the update unit 50 is not particularly limited, and various methods such as a bisection method, a Monte Carlo method, a generation inspection method, a genetic algorithm, and the like can be used.

On the other hand, when it is determined that the flow rate need not be updated (NO in step S42), the process proceeds to step S51. For example, when the shortest distance detected by the detection unit 30 is equal to the reference value, the update unit 50 determines that the flow rate need not be updated. In step S51, the output unit 40A outputs the finally determined flow rate (flow rate 52).

FIG. 19 is a flowchart for explaining an example of the flow rate update process (step S44) shown in FIG. FIG. 19 shows an example of a flow rate update method according to the bisection method. Referring to FIG. 19, update unit 50 determines whether the shortest distance detected by detection unit 30 is greater than the reference value or whether the detected shortest distance is less than the reference value (step S441). The reference value is the shortest distance 17 input to the input unit 10. When the detected shortest distance is equal to the reference value, the process shown in FIG. 19 is not executed.

If it is determined that the detected shortest distance is greater than the reference value (YES in step S441), the process proceeds to step S442. In step S442, the update unit 50 increases the flow rate from the current value. Specifically, the update unit 50 sets a value that is ½ of the sum of the maximum value and the minimum value as a new flow rate. The current value of the flow rate is substituted for the minimum value, while the maximum value is not changed.

On the other hand, when it is determined that the detected shortest distance is smaller than the reference value (NO in step S441), the process proceeds to step S443. In step S443, the update unit 50 decreases the flow rate from the current value. Specifically, the current value of the flow rate is substituted for the maximum value. On the other hand, the minimum value is not changed. Similar to the processing in step S442, the updating unit 50 sets a value that is ½ of the sum of the maximum value and the minimum value as a new flow rate. When the process of step S442 or step S443 ends, the process of step S44 ends.

As described above, according to the second embodiment, the wire flow can be simulated using the CAD model of the semiconductor device as in the first embodiment. According to the second embodiment, the design efficiency of the semiconductor device can be increased as in the first embodiment, and the size of the semiconductor device can be reduced.

Furthermore, according to the second embodiment, it is possible to calculate a flow rate that avoids contact and interference between wires. The output flow rate 52 can be used, for example, for selection of the resin 6 and determination of conditions for the sealing process. Thereby, the design efficiency of the semiconductor design apparatus can be further enhanced.

[Embodiment 3]
FIG. 20 is a functional block diagram of the design support apparatus according to the third embodiment. Referring to FIGS. 3 and 20, design support apparatus 100 B is different from design support apparatus 100 in that it includes generation unit 20 B instead of generation unit 20. The configuration and function of other parts of the design support apparatus 100B are the same as the configuration and function of the corresponding part of the design support apparatus 100.

The input unit 10 receives the CAD model 11 and the wire shape data 18. The wire shape data 18 is data simulating a wire flow.

For example, the wire shape data 18 includes the coordinates of the bond point of the wire and the coordinates of the bending point of the wire (see FIG. 8). The coordinates are obtained by a method different from the method of approximating the wire shape according to the first embodiment, for example. Alternatively, based on an X-ray fluoroscopic image of the semiconductor device in which the wire flow has actually occurred, a numerical value of a parameter for specifying the shape of the wire (for example, coordinates of the bending point) is obtained, and the numerical value is input as the wire shape data 18 It may be input to the unit 10.

The wire shape data 18 may be a CAD model that simulates a wire flow instead of numerical data. For example, a wire flow is simulated using a flow analysis technique, and such a CAD model can be generated by reflecting the result in the CAD model. Alternatively, a CAD model simulating the wire flow may be generated by modeling the wire flow state using CAD.

The generation unit 20B generates a wire flow model 21 based on the CAD model 11 and the wire shape data 18.

FIG. 21 is a flowchart for explaining wire flow verification processing by the design support apparatus according to the third embodiment. The processing flow shown in FIG. 21 is different from the processing flow shown in FIG. 16 in the following points. First, the process of step S12 is executed instead of the process of step S10. Secondly, the process of step S20 is omitted. In step S12, the input unit 10 receives the CAD model 11 and the wire flow shape data. The generation unit 20 generates the wire flow model 21 based on the information input to the input unit 10 (step S30). Since the processes of steps S30, S40, and S50 are the same as the processes of the corresponding steps shown in FIG. 16, detailed description will not be repeated hereinafter.

According to the third embodiment, the wire flow can be simulated using the CAD model of the semiconductor device as in the first embodiment. Similar to the first embodiment, according to the third embodiment, the efficiency of the design of the semiconductor device can be improved. Furthermore, according to the third embodiment, it is possible to reduce the size of the semiconductor device.

[Hardware configuration of design support device]
FIG. 22 is a diagram showing a hardware configuration example for realizing the design support apparatus according to the embodiment of the present invention. The configuration described below can be applied to any of the

design support apparatuses

100, 100A, and 100B.

Referring to FIG. 22, the design support apparatus 100 (100A, 100B) includes a computer 101, a monitor 102, a keyboard 103, and a mouse 104. The computer 101 includes an FD (Flexible Disk) drive device 111 and a CD-ROM (Compact Disk-Read Only Memory) drive device 113. The FD driving device 111 reads information from the FD 112 and writes information to the FD 112. The CD-ROM driving device 113 reads information recorded on the CD-ROM 114.

FIG. 23 is a schematic configuration diagram of the design support apparatus shown in FIG. Referring to FIGS. 22 and 23, in addition to the FD driving device 111 and the CD-ROM driving device 113, the computer 101 includes a CPU (Central Processing Unit) 105, a memory 106, a fixed disk 107, and a communication interface 109. Including. The CPU 105, the memory 106, the fixed disk 107, and the like are connected to each other by a bus 108. The design support apparatus according to the embodiment of the present invention is realized by CPU 105 executing a program. For example, the program is provided by the FD 112 or the CD-ROM 114 as a recording medium. The program may be supplied to the computer 101 via the communication interface 109 and stored in the fixed disk 107. The program causes the computer to execute the processing shown in FIG. 16, FIG. 18, 19, or FIG.

The CPU 105 is an arithmetic processing unit that performs various numerical logic operations. The CPU 105 sequentially executes instructions according to the program. The memory 106 stores various types of information.

The monitor 102 displays information output by the CPU 105. As an example, the monitor 102 is configured by an LCD (Liquid Crystal Display) or a CRT (Cathode Ray Tube).

The keyboard 103 and the mouse 104 are operated by the user. The keyboard 103 and the mouse 104 accept commands from the user.

The communication interface 109 is a device for communication between the computer 101 and another device. For example, the communication interface 109 accepts data sent from the outside of the computer 101. The communication interface 109 further outputs data generated inside the computer 101 to the outside of the computer 101.

The “input unit” included in the design support apparatus according to the embodiment of the present invention is realized by, for example, the keyboard 103, the mouse 104, the communication interface 109, and the like. The “generation unit”, “detection unit”, and “update unit” included in the design support apparatus according to the embodiment of the present invention are mainly realized by the CPU 105. The “output unit” included in the design support apparatus according to the embodiment of the present invention is realized by the monitor 102, the communication interface 109, and the like. Note that the memory 106 and the fixed disk 107 are used as appropriate to constitute each element of the design support apparatus.

The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

The present invention can be used for designing a semiconductor device having a bonding wire and a sealing resin.

1 semiconductor device, 2 semiconductor chip, 3 substrate frame, 3A die pad, 3B lead, 4, 4C, 4D, 4E wire, 4A, 4B wire image, 5 die bonding material, 6 resin, 7A1, 7A2, 7B mold, 8A , 8B cavity, 9 plunger, 10 input unit, 11 CAD model, 12 resin injection position, 12A-12D injection position, 13, 51, 52 flow rate, 15, 16 bonding pad, 17 shortest distance, 18 wire shape data, 19 region, 20, 20B generation unit, 21 wire flow model, 30 detection unit, 31 shortest distance measurement unit, 32 contact location detection unit, 33 interference location detection unit, 40, 40A output unit, 41 shortest distance output unit, 42 contact Location output unit, 43 Interference location output unit, 50 Update unit, 100 100A, 100B design support device, 101 computer, 102 monitor, 103 keyboard, 104 mouse, 105 CPU, 106 memory, 107 fixed disk, 108 bus, 109 communication interface, 111 FD drive, 112 FD, 113 CD-ROM drive , 114 CD-ROM, G1, G2 group, P1-P4 points, S10-S51, S441-S443 steps.

Claims

A design support device for a semiconductor device, wherein the semiconductor device includes a semiconductor chip (2) and a plurality of wires (4) connected between the semiconductor chip (2) and a substrate frame (3), The design support apparatus includes:
The first data for expressing the three-dimensional shape of the semiconductor device, and the resin (6) injected into a mold for sealing the semiconductor chip (2) and the plurality of wires (4). An input unit (10) for receiving second data for expressing the deformation of the wire (4);
A generator (20, 20B) that generates third data for expressing a three-dimensional shape of the semiconductor device after the deformation of the wire (4) is generated based on the first and second data. )When,
A semiconductor comprising: a detection unit (30) configured to detect whether or not the plurality of wires (4) include first and second wires that are in contact with each other based on the third data; Device design support device.
The detection unit (30)
A first detector (31) for detecting the shortest distance between the first and second wires;
A second detector (32) for detecting whether or not the first and second wires are in contact with each other;
The design support apparatus for a semiconductor device according to claim 1, further comprising a third detection unit (33) configured to detect whether or not the first and second wires interfere with each other.
The output section (40) for outputting each detection result of the first to third detection sections (31-33) together with wire numbers for specifying the first and second wires. 3. A semiconductor device design support apparatus according to item 2.
Based on the detection results of the first to third detection units (31-33), an output unit configured to display a location where at least one of contact and interference has occurred in the semiconductor device ( 40) The semiconductor device design support apparatus according to claim 2, further comprising: 40).
The first detection unit (31) detects whether the shortest distance is less than a reference value,
The design support apparatus includes:
The semiconductor device design support according to claim 2, further comprising an output unit (40) configured to display a location of the semiconductor device detected as the shortest distance being less than the reference value. apparatus.
An output unit configured to superimpose and display the three-dimensional shape of the semiconductor device expressed by the first data (11) and the three-dimensional shape of the semiconductor device expressed by the third data The design support apparatus for a semiconductor device according to claim 1, further comprising (40).
The second data is:
An injection position of the resin to be injected into the mold;
A flow rate (13) of the wire (4),
The design support apparatus for a semiconductor device according to claim 1, wherein the implantation position (12) is selected in advance from a plurality of positions.
The generation unit (20) generates the third data by simulating the deformation of the wire (4) according to the injection position and the flow rate,
8. The semiconductor device design support apparatus according to claim 7, wherein the first and third data are CAD (Computer Aided Design) data.
The flow rate is
Pre-selected from among a common value among the plurality of wires, a plurality of values assigned to each group composed of at least two wires, and a plurality of values respectively associated with the plurality of wires A design support apparatus for a semiconductor device according to claim 7, wherein
Based on the detection result of each of the first to third detection units, the value of the flow rate is determined from the value input to the input unit (10), and the contact between the first and second wires. The design support apparatus for a semiconductor device according to claim 7, further comprising an update unit (50) that updates the value to a value for preventing the failure.
The first and third data are CAD (Computer Aided Design) data,
The design support apparatus for a semiconductor device according to claim 1, wherein the second data is any one of CAD data and numerical data.
A design support method for a semiconductor device, wherein the semiconductor device includes a semiconductor chip (2) and a plurality of wires (4) connected between the semiconductor chip (2) and a substrate frame (3), The design support method includes:
The first data for expressing the three-dimensional shape of the semiconductor device, and the resin (6) injected into a mold for sealing the semiconductor chip (2) and the plurality of wires (4). Receiving the second data for expressing the deformation of the wire (4) (S10, S11, S12);
Steps of generating third data for expressing the three-dimensional shape of the semiconductor device after the deformation of the wire (4) is generated based on the first and second data (S20, S30). When,
A step (S40) of detecting whether or not the plurality of wires (4) include first and second wires that are in contact with each other based on the third data. Design support method.