WO2012025140A1

WO2012025140A1 - Method of measuring the phase of a clock signal and clock signal phase measurement apparatus

Info

Publication number: WO2012025140A1
Application number: PCT/EP2010/062258
Authority: WO
Inventors: David Linney
Original assignee: Telefonaktiebolaget LM Ericsson AB
Current assignee: Telefonaktiebolaget LM Ericsson AB
Priority date: 2010-08-23
Filing date: 2010-08-23
Publication date: 2012-03-01
Anticipated expiration: 2013-02-23

Abstract

A method (10) of measuring the phase of a clock signal, the method comprising: a) receiving a clock signal comprising clock cycles having a clock frequency and a clock period, T_Clock (12); b) providing a reference clock signal comprising reference clock cycles having a reference clock period, T_Ref, and a reference clock frequency different to the clock frequency (14); c) for each of a plurality, N, of reference clock cycles, comparing the clock signal to the reference clock signal and determining a phase difference between said signals (16); d) obtaining a sum of the phase differences for a said plurality of reference clock cycles (18); e) for each of the plurality of reference clock cycles, subtracting an oldest phase difference from the sum and adding the phase difference for the said reference clock cycle to the sum to provide a new sum, the new sum being indicative of the phase of the clock signal at the said reference clock cycle (20); and f) generating and transmitting a clock phase signal indicative of the new sum (22).

Description

Method of measuring the phase of a clock signal and clock signal phase measurement apparatus.

Technical Field

The invention relates to a method of measuring the phase of a clock signal. The invention further relates to clock signal phase measurement apparatus. The invention further relates to a communications network switch comprising the clock signal phase measurement apparatus. Background

In communications networks it is necessary to synchronise egress traffic to ingress traffic across a multiplexer, router or switch. In synchronous digital hierarchy (SDH) communications systems a synchronous equipment timing generator (SETG) is used to route clock signals, representative of the ingress traffic across a multiplexer and phase-lock the egress clocks to one of them. In optical transport network (OTN) communications systems traffic is routed to an egress fir st-in- first-out (FIFO) queue buffer and phase- locked loops are used to phase lock the egress clocks to their respective data rates according to the FIFO fill state. These approaches have worked well enough in

multiplexer, routers and switches aimed solely at one specific type of traffic.

The next generation multiplexers will contain a mix of traffic types, including packet-switched traffic, synchronous SDH traffic and asynchronous OTN traffic, each of which has its own synchronisation requirements. It will not be economical to provision synchronisation source paths through the equipment to support non-blocking port-port synchronisation. Synchronisation will have to be carried with the traffic through the switch, requiring measurement of the phase of the traffic's clock signal.

There are two techniques which have commonly been used to achieve a high resolution measurement of a clock's phase. The first samples the client clock with a very high frequency reference clock to yield a high resolution measurement. In order to achieve bit-resolution measurement of an optical transport unit (OUT) client clock, a reference of at least the client data rate's frequency would be required. That is 2.5GHz for OTU1 and 40GHz for OTU3. There is no affordable technology which can perform sufficient processing at these frequencies at present. The second uses a reference clock similar to the data rate, with multiple phases of the reference clock being generated. The closest phase to the ideal sampling point on the eye diagram is continuously selected to generate a recovered clock. For an OTU3 client using a 167MHz reference clock, 256 phases would be required, which is not practical. In addition, this approach works only for very close frequency relationships, therefore there would need to be a specific reference clock frequency for each type of traffic signal.

Summary

i t is an object to provide an improved .method of measuring the phase of a clock signal. It is a further object to provide an improved clock signal phase measurement apparatus. It is a further object to provide an improved communications network switch.

A first aspect of the invention provides a method of measuring the phase of a clock signal. The method comprises steps a. to f. Step a. comprises receiving a clock signal. The clock signal comprises clock cycles having a clock frequency and a clock period, T_Ci_0Ck. Step b. comprises providing a reference clock signal. The reference clock signal comprises reference clock cycles having a reference clock period, TR^ and a reference clock frequency. The reference clock frequency is different to the clock frequency. Step c.

comprises, for each of a plurality, N, of reference clock cycles, comparing the clock signal to the reference clock signal and determining a phase difference between said signals. Step d. comprises obtaining a sum of the phase differences for a said plurality of reference clock cycles. Step e. comprises, for each of the plurality of reference clock cycles, subtracting an oldest phase difference from the sum and adding the phase difference for the said reference clock cycle to the sum to provide a new sum. The new sum is indicative of the phase of the clock signal at the said reference clock cycle. Step f. comprises generating and transmitting a clock phase signal indicative of the new sum.

The method may enable a high resolution measurement of the phase of the clock signal to be made for a wide range of clock frequencies using a single reference clock frequency. The method may enable the phase of a clock signal to be measured and may be used to measure the phase of synchronous SDH traffic, asynchronous OTN traffic and packet-switched traffic. The method may enable the ingress phase of traffic to be digitized to a high resolution on a per port basis. A higher phase measurement resolution may be achieved using the method than using the prior art methods of measuring the phase of a clock signal. The new sum may provide a measure of the relative phase of the clock signal and the reference clock signal, with a change, M, in the new sum being indicative of a relative phase advancement or retardation. The method may be implemented in existing application specific integrated circuits (ASICs) and Field-Programmable Gate Arrays (FPGAs) in installed communications networks. The method may enable a packet switch to be operated such that it emulates an SDH switch or an OTN switch and may enable legacy time division multiplexed (TDM) services to be supported by a packet switch.

In an embodiment, the reference clock frequency is selected such that the said plurality of reference clock cycles in a repetition period, TR_ep, at which the clock signal and

T

the reference clock signal synchronize is given by N =—— . N is greater than 200. In an

^Re /

embodiment, N is between 250 and 500. A large number of reference clock cycles may therefore pass before the clock signal and the reference clock signal come into

synchronisation, that is to say before the total period of N reference clock cycles is equal to the total period of N clock cycles, and the pattern between the clock signal and the reference clock signal begins to repeat. This may enable the method to be used to make a very high resolution measurement of the phase of the clock signal.

In an embodiment, the method further comprises determining a time period for the total period of N reference clock cycles when the reference clock cycles and the clock cycles come into synchronisation and comparing the time period to a threshold value given T

by ^clock , where TR_es is a measurement resolution for the clock period. If the time period is less than the threshold value the method comprises rejecting the reference clock frequency and selecting a further reference clock frequency.

In an embodiment, the clock frequency comprises one of a plurality of candidate clock frequencies. The reference clock signal is provided with a reference clock frequency which enables a minimum measurement resolution, TR_es, for the clock period to be provided for each candidate clock frequency. The minimum measurement resolution is

T

given by the relationship T_Res = ^C^^{l k} . The method may enable a single reference clock signal to be used to measure the phase of clock signals having a range of different clock frequencies. In an embodiment, step c. comprises generating a clock count running on the clock signal and providing a mimic clock count. The method further comprises determining a difference between respective pairs of the clock count and the mimic clock count. Step d. comprises summing the differences between the pairs. The method may therefore provide a digitized measurement of the phase of the clock signal.

In an embodiment, the difference is determined by incrementing the clock count on a clock counter and incrementing the mimic clock count on a mimic counter and comparing the clock count and the mimic clock count of each respective pair. In an alternative embodiment, the difference is determined by incrementing the clock count and the mimic clock count on a shared counter, the clock count being incremented one of positively and negatively and the mimic clock count being incremented the other of positively and negatively. The shared counter therefore increments only by a difference between each clock count and mimic clock count. The method may enable a single counter to be used the difference between each clock count and the mimic count being determined in a single step.

In an embodiment, the clock count is generated by edge detecting the clock signal using the reference clock signal and incrementing the clock count by a Clock-Rate for each

T

detected clock cycle of the clock signal. The Clock-Rate is given by Clock - Rate = ^{clo k} , where T_Res is a required measurement resolution for the clock period. Edge detecting the clock signal with the reference clock signal may minimise or prevent distortion of the clock signal.

In an embodiment, the mimic clock count mimics a count progression of the clock count for a clock signal having an idealised phase progression. The phase of the clock signal may therefore be measured relative to its idealised phase progression, so that only phase differences in addition to an expected phase progression are measured.

In an embodiment, the mimic clock count is based on the reference clock signal. The mimic clock count is incremented by a Mimic-Rate for each reference clock cycle.

T Re f

The Mimic-Rate is given by Mimic - Rate = Clock - Rate * — .

^ Clock

In an embodiment, the mimic-rate comprises a non-integer number, Base. Fraction. The mimic clock count is incremented by a Base-Rate for each reference clock cycle. The mimic clock count is additionally incremented by a Fraction-Rate for each of a fraction of the reference clock cycles. The mimic clock count may therefore mimic the clock signal's idealised phase progression by incrementing by a non- integer number. Incrementing the mimic clock count by the Base-Rate and additionally by the Fraction-Rate for a fraction of the reference clock cycles enables an effective mimic-rate of Base.Fraction to be achieved, enabling phase progression of the clock signal to be mimicked.

In an embodiment, the mimic clock count is additionally incremented by a

Justification-Rate for each of a second fraction of the reference clock cycles. This may enable a positive or negative justification of the mimic clock count to be performed.

In an embodiment, step d. comprises generating a sample of each difference. Step d. further comprises obtaining a sum of the samples for a said plurality, N, of mimic clock counts. Step e. comprises subtracting the oldest sample from the sum and adding the newest sample to the sum to provide a new sum. A running accumulation of N samples may therefore be provided for each reference clock cycle. Providing a sum of the samples for a said plurality, N, of mimic clock counts in step d. may ensure that the running accumulation generated in step e. represents the absolute phase of the clock signal. The accumulated value may provide a continuous measure of the relative phase of the clock signal and the reference clock signal. A change, M, in the accumulated value represents *T_Res seconds of phase advancement or retardation of the clock signal. Providing a sum

T

of N samples, where N =—— , may eliminate the effects of an interference pattern

^Re /

between the clock cycles of the clock signal and the reference clock cycles of the reference clock signal and may ensure that the accumulated value always contains a complete interference pattern. The new sample entering the sum may be the same as the oldest sample leaving the sum, therefore the sum may only change in response to a change in the phase of the clock signal.

In an embodiment, step d. comprises obtaining a sum of the samples for an integer multiple of said plurality, N, of mimic clock counts.

In an embodiment, the reference clock is arranged to have no systematic relationship to any other clock in a system in which the method is to be used.

In an embodiment, the reference clock signal is arranged to have a reproducible relationship to a clock signal available throughout a system in which the method is to be used. This may enable the reference clock signal to be easily generated from the clock signal available throughout the system, and may ensure that the same reference clock signal is available for use throughout a system.

A second aspect of the invention provides clock signal phase measurement apparatus comprising an input, a reference clock signal generator, a controller and an output. The input is arranged to receive a clock signal. The clock signal comprises clock cycles having a clock frequency and a clock period, T_Ci_0Ck. The reference clock signal generator is arranged to provide a reference clock signal. The reference clock signal comprises reference clock cycles having a reference clock period, T_Ref, and a reference clock frequency. The reference clock frequency is different to the clock frequency. The controller is arranged to receive the clock signal and the reference clock signal. For each of a plurality, N, of reference clock cycles, the controller is arranged to compare the clock signal to the reference clock signal and determine a phase difference between said signals. The controller is further arranged to obtain a sum of the phase differences for a said plurality of reference clock cycles. For each of the plurality of reference clock cycles, the controller is arranged to subtract an oldest phase difference from the sum and add the phase difference for the said reference clock cycle to the sum to provide a new sum. The new sum is indicative of the phase of the clock signal at the said reference clock cycle. The controller is further arranged to generate a clock phase signal indicative of the new sum. The output is arranged to deliver the clock phase signal.

The apparatus may used to perform a high resolution measurement of the phase of a wide range of clock frequencies using a single reference clock frequency. The apparatus may be used to measure the phase of a clock signal and may be used to measure the phase of synchronous SDH traffic, asynchronous OTN traffic and packet-switched traffic. The apparatus may be used to digitize the phase of ingress phase of traffic to a high resolution on a per port basis. A higher phase measurement resolution may be achieved using the apparatus than using the prior art arrangements for measuring the phase of a clock signal. The new sum may provide a measure of the relative phase of the clock signal and the reference clock signal, with a change, M, in the new sum being indicative of a relative phase advancement or retardation. The apparatus may be provided in existing application specific integrated circuits (ASICs) and Field-Programmable Gate Arrays (FPGAs) in installed communications networks. The apparatus may be used in a packet switch to enable the packet switch to be operated such that it emulates an SDH switch or an OTN switch and may enable legacy time division multiplexed (TDM) services to be supported by the packet switch.

In an embodiment, the reference clock signal generator is arranged to generate a reference clock signal having a reference clock frequency for which the said plurality of reference clock cycles in a repetition period, TR_ep, at which the clock signal and the

T

reference clock signal synchronize is given by N =—— . N is greater than 200. In an

^Re /

synchronisation, that is to say before the total period of N reference clock cycles is equal to the total period of N clock cycles, and the pattern between the clock signal and the reference clock signal begins to repeat. This may enable the apparatus to be used to make a very high resolution measurement of the phase of the clock signal.

In an embodiment, the clock frequency comprises one of a plurality of candidate clock frequencies. The reference clock signal generator is arranged to generate a reference clock signal having a reference clock frequency which enables a minimum measurement resolution, T_Res, for the clock period to be provided for each candidate clock frequency.

T

The minimum measurement resolution is given by the relationship T_Res = ^C^^{l k} . A single reference clock signal may be used to measure the phase of clock signals having a range of different clock frequencies.

In an embodiment, the controller is arranged to generate a clock count running on the clock signal and provide a mimic clock count. The controller is further arranged to determine a difference between respective pairs of the clock count and the mimic clock count. The controller is arranged to sum the differences. The apparatus may therefore provide a digitized measurement of the phase of the clock signal.

In an embodiment, the controller comprises and edge detector and a clock counter.

The edge detector is arranged to edge detect the clock signal using the reference clock signal to generate the clock count. The clock counter is arranged to generate and increment the clock count by a Clock-Rate for each detected clock cycle of the clock signal. The

T

Clock-Rate is given by Clock - Rate = ^{clo k} , where T_Res is a required measurement resolution for the clock period. Edge detecting the clock signal with the reference clock signal may minimise or prevent distortion of the clock signal.

In an embodiment, the controller is arranged to provide a mimic clock count which mimics a count progression of the clock count for a clock signal having an idealised phase progression. The phase of the clock signal may therefore be measured relative to its idealised phase progression, so that only phase differences in addition to an expected phase progression are measured.

In an embodiment, the controller is arranged to base the mimic clock count on the reference clock signal. The controller is further arranged to increment the mimic clock count by a Mimic-Rate for each reference clock cycle. The Mimic-Rate is given by

T Re f

Mimic - Rate = Clock - Rate * .

T Clock

In an embodiment, the mimic-rate comprises a non-integer number, Base. Fraction. The controller comprises an incrementation signal generator. The incrementation signal generator is arranged to generate a Base-Rate incrementation signal arranged to cause the mimic clock count to increment by a Base-Rate for each reference clock cycle. The incrementation signal generator is further arranged to generate a Fraction-Rate

incrementation signal arranged to additionally cause the mimic clock count to increment by a Fraction-Rate for each of a fraction of the reference clock cycles. The mimic clock count may therefore mimic the clock signal's idealised phase progression by incrementing by a non-integer number. Incrementing the mimic clock count by the Base-Rate and

additionally by the Fraction-Rate for a fraction of the reference clock cycles enables an effective mimic-rate of Base.Fraction to be achieved, enabling phase progression of the clock signal to be mimicked.

In an embodiment, the controller further comprises a justification signal generator. The justification signal generator is arranged to generate a Justification-Rate

incrementation signal arrange to cause the mimic clock count to increment by a

In an embodiment, the controller further comprises a mimic clock counter arranged to generate and increment the mimic clock count by the Mimic-Rate for each reference clock cycle and the difference is determined by comparing the clock count and the mimic clock count for each reference clock cycle. In an alternative embodiment, the clock counter is arranged to increment the clock count and the mimic clock count, the clock counter being arranged to increment the clock count one of positively and negatively and to increment the mimic clock count the other of positively and negatively. The shared counter therefore increments only by a difference between each clock count and mimic clock count. A single counter may therefore be used to determine the difference between each clock count and the mimic count in a single step.

In an embodiment, the controller comprises a sample generator, a sample accumulator and a running accumulator. The sample generator is arranged to generate a sample of each difference. The sample accumulator is arranged to generate a sum of the samples for a said plurality, N, of mimic clock counts. The running accumulator is arranged to receive the sum of samples from the sample accumulator and to subtract the oldest sample from the sum and add the newest sample to the sum to provide a new sum. A running accumulation of N samples may therefore be provided for each reference clock cycle. Providing a sum of the samples for a said plurality, N, of mimic clock counts in step d. may ensure that the running accumulation generated in step e. represents the absolute phase of the clock signal. The accumulated value may provide a continuous measure of the relative phase of the clock signal and the reference clock signal. A change, M, in the accumulated value represents M*T_Res seconds of phase advancement or retardation of the

T

clock signal. Providing a sum of N samples, where N =—— , may eliminate the effects of

^Re /

an interference pattern between the clock cycles of the clock signal and the reference clock cycles of the reference clock signal and may ensure that the accumulated value always contains a complete interference pattern. The new sample entering the sum may be the same as the oldest sample leaving the sum, therefore the sum may only change in response to a change in the phase of the clock signal.

In an embodiment, the sample accumulator is arranged to generate a sum of the samples for an integer multiple of said plurality, N, of mimic clock counts.

In an embodiment, the reference clock is arranged to have no systematic relationship to any other clock in a system in which the apparatus is to be used.

In an embodiment, the reference clock is arranged to have a reproducible relationship to a clock available throughout a system in which the apparatus is to be used. This may enable the reference clock signal to be easily generated from the clock signal available throughout the system, and may ensure that the same reference clock signal is available for use throughout a system.

A third aspect of the invention provides a communications network switch comprising an input, clock-recovery apparatus and clock signal phase measurement apparatus. The input is arranged to receive a traffic carrying signal. The clock-recovery apparatus is arranged to recover a clock signal from the traffic carrying signal. The clock signal phase measurement apparatus is as described above.

A fourth aspect of the invention provides a data carrier having computer readable instructions embodied therein. The said computer readable instructions are for providing access to resources available on a processor. The computer readable instructions comprise instructions to cause the processor to perform any of the above steps of the method of measuring the phase of a clock signal.

Brief description of the drawings

Figure 1 shows the steps of a method of providing the phase of a clock signal according to a first embodiment of the invention;

Figure 2 shows the steps of a method of providing the phase of a clock signal according to a second embodiment of the invention;

Figure 3 shows the steps of a method of providing the phase of a clock signal according to a third embodiment of the invention;

Figure 4 is a diagrammatic representation of (a) a clock signal and a reference clock signal and (b) an interference pattern generated between the clock signal and reference clock signal in (a), for any of the methods of Figures 1 to 3;

Figure 5 shows the steps of a method of providing the phase of a clock signal according to a fourth embodiment of the invention;

Figure 6 shows the steps of a method of providing the phase of a clock signal according to a fifth embodiment of the invention;

Figure 7 shows the steps of a method of providing the phase of a clock signal according to a sixth embodiment of the invention;

Figure 8 shows the steps of a method of providing the phase of a clock signal according to a seventh embodiment of the invention; Figure 9 is a schematic representation of clock signal phase measurement apparatus according to an eighth embodiment of the invention;

Figure 10 is a schematic representation of clock signal phase measurement apparatus according to a ninth embodiment of the invention; and

Figure 11 is a schematic representation of a communications network switch according to a tenth embodiment of the invention.

Detailed description

Referring to Figure 1, a first embodiment of the invention provides a method 10 of measuring the phase of a clock signal. The method 10 comprises:

a. receiving a clock signal comprising clock cycles having a clock frequency and a clock period, T_Ci₀ck 12;

b. providing a reference clock signal comprising reference clock cycles having a

reference clock period, T_Ref, and a reference clock frequency different to the clock frequency 14;

c. for each of a plurality, N, of reference clock cycles, comparing the clock signal to the reference clock signal and determining a phase difference between said signals 16; d. obtaining a sum of the phase differences for a said plurality of reference clock cycles 18;

e. for each of the plurality of reference clock cycles, subtracting an oldest phase

difference from the sum and adding the phase difference for the said reference clock cycle to the sum to provide a new sum, the new sum being indicative of the phase of the clock signal at the said reference clock cycle 20; and

f. generating and transmitting a clock phase signal indicative of the new sum 22.

A second embodiment of the invention provides a method 30 of measuring the phase of a clock signal, as shown in Figure 2. The method 30 is substantially the same as the method 10 of Figure 1, with the following modifications. The same reference numbers are retained for corresponding steps.

In this embodiment, in step b. the reference clock frequency is selected 32 such that the said plurality of reference clock cycles in a repetition period, T_Rep, at which the clock

T

signal and the reference clock signal synchronize is given by N =—— , where T_Ref is the

^Re / reference clock period. The reference clock frequency is selected such that N is greater than 200, in this example 250. A large number of reference clock cycles therefore elapse before the clock signal and the reference clock signal come into synchronisation. Due to the difference between the clock frequency and the reference clock frequency there is a varying time offset between each cycle of the two signals, which results in a pattern between the signals in the time domain, as will be described in more detail below with reference to Figure 4. The reference clock frequency is selected so that N, being the number of reference clock cycles before the pattern between the clock signal and the reference clock signal begins to repeat, is greater than 200. Ensuring that a large number of reference clock cycles pass before the pattern repeats may allow a very high resolution measurement of the phase of the clock signal to be made.

A reference clock signal is then provided at the selected reference clock frequency

34.

The steps of a method 40 of measuring the phase of a clock signal according to a third embodiment of the invention are shown in Figure 3. The method 40 is substantially the same as the method 30 of Figure 2, with the following modifications. The same reference numbers are retained for corresponding steps.

In this embodiment, the clock frequency comprises one of a plurality of candidate clock frequencies. The reference clock frequency is further selected 42 to enable a minimum measurement resolution, TR_es, for the clock period to be provided for each

T

candidate clock frequency. The measurement resolution is given by: T_Res = ^C^^{l k} .

The reference clock signal is provided at the selected reference clock frequency 44. The method 40 of this embodiment may therefore be used to measure the phase of clock signals having a range of clock frequencies using a single reference clock signal.

Referring to Figure 4(a), in each of the described embodiments the difference between the clock frequency and the reference clock frequency, and thus between the clock period (T_Ci_0Ck) and the reference clock period (T_Ref), means that each cycle of the clock signal is offset in time in phase (0) from the corresponding cycle of the reference clock signal. Comparing the differing period/frequency signals therefore forms an effective Vernier scale measurement 50 of the phase of the clock signal relative to the reference clock signal. As in a Vernier ruler, each pair of clock cycles has a different phase offset (0i , 0₂ , etc), and the phase offsets repeat after the clock signal and the reference clock signal come into synchronisation, i.e. when the total period of the clock signal and the total period of the reference clock signal match, which is referred to here as the repetition period. This results in a pattern 60 of phase differences 62, as shown in Figure 4(b), which repeats on the same time scale. The reference clock frequency is selected 32, 43 such that the number,

T

N, given by N =—— , of reference clock cycles in the repetition period, T_Rep, is greater

^Re /

than 200, such that there are at least 200 phase differences in the pattern. The greater the number of phase differences, the higher the measurement resolution of the phase of the clock signal relative to the reference clock signal. The N phase differences in the repetition period are here referred to as a sample set.

A fourth embodiment of the invention provides a method 70 of measuring the phase of a clock signal comprising the steps shown in Figure 5. The method 70 of this embodiment is similar to the method 10 of the first embodiment, with the following modifications.

In this embodiment, step c. comprises generating a clock count running on the clock signal and providing a mimic clock count 72. Step c. further comprises, for each of the N reference clock cycles in a sample set, determining a difference between respective pairs of the clock count and the mimic clock count 74.

Step d. comprises obtaining a sum of the differences for a said N pairs 76 of reference clock cycles. Step e. comprises, for each mimic clock count, and thus each pair of clock counts, subtracting the oldest difference from the sum and adding the difference for the current pair to the sum to provide a new sum 78. The new sum is indicative of the phase of the clock signal relative to the reference clock signal.

The new sum comprises a running accumulation of N differences for each reference clock cycle. Providing a sum of the differences for a said plurality, N, of mimic clock counts in step d. may ensure that the running accumulation generated in step e. represents the absolute phase of the clock signal. The accumulated value may provide a continuous measure of the relative phase of the clock signal and the reference clock signal. A change, M, in the accumulated value represents M*T_Res seconds of phase advancement or retardation of the clock signal. Providing a sum of N samples, that is a sum of the samples in a complete sample set, may eliminate the effects of the interference pattern, since the newest difference added should be the same as the oldest difference subtracted and the sum will therefore only change if there has been a change in the relative phase of the clock signal.

Referring to Figure 6, a fifth embodiment of the invention provides a method 80 of measuring the phase of a clock signal. The method 80 of this embodiment is similar to the method 70 of the previous embodiment, with the following modifications.

In this embodiment, the clock count running on the clock signal is generated by edge detecting the clock signal using the reference clock signal 82. The clock count is incremented by a Clock-Rate for each detected clock cycle of the clock signal 84. The

T

Clock-Rate is given by Clock - Rate = ^{clo k} , where T_Res is a required measurement resolution for the clock period.

The reference clock signal is used to provide the mimic clock count which mimics an idealised phase progression of the clock signal. The mimic clock count is based on the reference clock signal and is incremented by a Mimic-Rate for each reference clock cycle

T Re f

84. The Mimic-Rate is given by Mimic - Rate = Clock - Rate * — .

^ Clock

Referring to Figure 7, a sixth embodiment of the invention provides a method 90 of measuring the phase of a clock signal. The method 90 of this embodiment is similar to the method 80 of the previous embodiment, with the following modifications.

In this embodiment, the mimic clock count must on average be incremented by a Mimic-Rate which is a non-integer number, Base. Fraction, in order to mimic the idealized phase progression of the clock signal. The mimic clock is therefore incremented by a Base- Rate for each reference clock cycle and additionally by a Fraction-Rate for each of a fraction of the reference clock cycles 92.

A seventh embodiment of the invention provides a method 100 of measuring the phase of a clock signal comprising the steps shown in Figure 8. The method 100 of this embodiment is similar to the method 70 of Figure 5, with the following modifications. In this embodiment, the sum of the differences between N pairs of clock counts is obtained by generating a sample of each difference 102 and obtaining a sum of the samples for N mimic clock counts, i.e. for a complete sample set.

For each sample, N, in a sample set, the oldest sample is subtracted from the existing sum and the current sample is added to the sum. The new sum obtained is indicative of the phase of the clock signal relevant to the reference clock signal.

An eighth embodiment of the invention provides clock signal phase measurement apparatus 110 comprising an input 112, a reference clock signal generator 116, a controller 120 and an output 124.

The input 112 is arranged to receive a clock signal 114. The clock signal 114 comprises clock cycles having a clock frequency and a clock period, T_Ci_0Ck. The reference clock signal generator 116 is arranged to provide a reference clock signal 118. The reference clock signal 118 comprises reference clock cycles having a reference clock period, T_Ref, and a reference clock frequency. The reference clock frequency is different to the clock frequency.

The controller 120 is arranged to:

i. receive the clock signal and the reference clock signal;

ii. for each of a plurality, N, of reference clock cycles, compare the clock signal to the reference clock signal and determine a phase difference between said signals;

iii. obtain a sum of the phase differences for a said plurality of reference clock cycles; iv. for each of the plurality of reference clock cycles, subtracting an oldest phase

difference from the sum and adding the phase difference for the said reference clock cycle to the sum to provide a new sum, the new sum being indicative of the phase of the clock signal at the said reference clock cycle; and

v. generate a clock phase signal 122 indicative of the new sum.

The output 124 is arranged to deliver the clock phase signal.

Clock signal phase measurement apparatus 130 according to a ninth embodiment of the invention is shown in Figure 10. The apparatus 130 of this embodiment is similar to the apparatus 110 of Figure 9, with the following modifications. The same reference numbers are retained for corresponding elements.

In this embodiment, the controller 120 is arranged in step ii. to generate a clock count running on the clock signal and provide a mimic clock count. The controller is further arranged to determine a difference between respective pairs of the clock count and the mimic clock count. The controller is further arranged in step iii. to sum the differences.

The controller 120 comprises an edge detector 132 and a clock counter 134. The edge detector 132 is arranged to edge detect the clock signal using the reference clock signal, to thereby generate the clock count. The clock counter 134 is arranged to increment the clock count by a Clock-Rate for each detected clock cycle of the clock signal. The

T

Clock-Rate is given by: Clock - Rate = ^{clo k} , where T_Res is a required measurement resolution for the clock period. The controller 120 further comprises a clock

incrementation signal generator arranged to generate a clock incrementation signal arranged to cause the clock counter 134 to increment by the Clock-Rate for each detected clock cycle.

The controller 120 is arranged to provide a mimic clock count which mimics a count progression of the clock count for a clock signal having an idealised phase progression. The controller 120 further comprises a mimic counter 136 and a mimic incrementation signal generator 140. The controller 120 is arranged to base the mimic clock count on the reference clock signal 118. The mimic incrementation signal generator 140 is arranged to receive the reference clock signal 118 and is arranged to cause the mimic counter to increment the mimic clock count. The mimic clock count is incremented by a Mimic-Rate for each reference clock cycle. The Mimic-Rate is given by:

T Re f

Mimic - Rate = Clock - Rate * — .

T Clock

In this example, the mimic-rate comprises a non-integer number, Base. Fraction, in order to generate a mimic clock count which mimics an idealised phase progression of the clock signal. The incrementation signal generator 140 is arranged to generate a Base-Rate incrementation signal 152 arranged to cause the mimic clock count to increment by a Base- Rate for each reference clock cycle. The incrementation signal generator 140 is further arranged to generate a Fraction-Rate incrementation signal 154 arranged to additionally cause the mimic clock count to increment by a Fraction-Rate for each of a fraction of the reference clock cycles. By incrementing by the Base-Rate and fractionally by the Fraction- Rate, the mimic clock counter is incremented by an effective non-integer mimic-rate.

The controller 120 of this example further comprises a justification signal generator

142. The justification signal generator 142 is arranged to generate a Justification-Rate incrementation signal 156 arrange to cause the mimic clock count to increment by a Justification-Rate 158 for each of a second fraction of the reference clock cycles. This may enable a positive or negative justification of the mimic clock count to be performed.

The controller further comprises a sample generator 144, a sample accumulator 146, a running accumulator 148 and a N-sample store 150. The sample generator 144 is arranged to compare respective counts on the clock counter 134 and the mimic counter 136 and to generate a sample of the difference 159 between the counts. The sample

accumulator 146 is arranged to generate a sum of the samples for each sample within a sample set (N samples). The running accumulator 148 is arranged to receive the sum of samples from the sample accumulator 146 and to subtract the oldest sample from the sum and add the newest sample, being the current sample, to the sum to provide a new sum.

The N-sample store 150 is arranged to receive and store each sample. The N- sample store 150 is further arranged to provide the oldest sample in the store to the running accumulator 146, for subtraction from the sum.

Providing the sum of the N samples in a sample set may ensure that the running accumulation represents the absolute phase of the clock signal. Providing the sum of the samples in a complete sample set may eliminate the effects of the interference pattern, since the newest sample added should be the same as the oldest sample subtracted and the sum will therefore only change if there has been a change in the relative phase of the clock signal. The accumulated value may thus provide a continuous measure of the relative phase of the clock signal and the reference clock signal. A change, M, in the accumulated value represents M*T_Res seconds of phase advancement or retardation of the clock signal.

Figure 11 shows a communications network switch 160 according to a tenth embodiment of the invention.

The switch 160 comprises an input 162, clock-recovery apparatus 166 and clock signal phase measurement apparatus 110. The input 162 is arranged to receive a traffic carrying signal 164. The clock-recovery apparatus 166 is arranged to recover a clock signal 114 from the traffic carrying signal. The clock signal phase measurement apparatus 110 is arranged to measure the phase of the recovered clock signal 114. The clock signal phase measurement apparatus 110 is as described above in Figure 9.

A twelfth embodiment of the invention provides a data carrier having computer readable instructions embodied therein. The said computer readable instructions are for providing access to resources available on a processor. The computer readable instructions comprise instructions to cause the processor to perform the steps of the method of measuring the phase of a clock signal of any of the above embodiments of the invention.

The data carrier may comprise a memory device, such a compact disc, digital versatile disc or electronic memory, or may comprise a communications signal.

Claims

1. A method of measuring the phase of a clock signal, the method comprising:

a) receiving a clock signal comprising clock cycles having a clock frequency and a clock period, T_Ci_0Ck;

b) providing a reference clock signal comprising reference clock cycles having a reference clock period, T_Ref, and a reference clock frequency different to the clock frequency;

c) for each of a plurality, N, of reference clock cycles, comparing the clock signal to the reference clock signal and determining a phase difference between said signals;

d) obtaining a sum of the phase differences for a said plurality of reference clock cycles;

e) for each of the plurality of reference clock cycles, subtracting an oldest phase difference from the sum and adding the phase difference for the said reference clock cycle to the sum to provide a new sum, the new sum being indicative of the phase of the clock signal at the said reference clock cycle; and

f) generating and transmitting a clock phase signal indicative of the new sum.

2. A method as claimed in claim 1, wherein the reference clock frequency is selected such that the said plurality of reference clock cycles in a repetition period, T_Rep, at which the

T

clock signal and the reference clock signal synchronize is given by N =—— and is

^Re / greater than 200.

3. A method as claimed in claim 1 or 2, wherein the clock frequency comprises one of a plurality of candidate clock frequencies and the reference clock signal is provided with a reference clock frequency which enables a minimum measurement resolution, T_Res,

T

for the clock period, given by the relationship T_Res = ^C^^{l k} , to be provided for each candidate clock frequency.

4. A method as claimed in any preceding claim, wherein step c. comprises generating a clock count running on the clock signal and providing a mimic clock count and determining a difference between respective pairs of the clock count and the mimic clock count, and step d. comprises summing the differences between the pairs.

5. A method as claimed in claim 4, wherein the clock count is generated by edge detecting the clock signal using the reference clock signal and incrementing the clock count by a Clock-Rate for each detected clock cycle of the clock signal, the Clock-Rate

T

being given by Clock - Rate = ^{clo k} , where T_Res is a required measurement resolution for the clock period.

6. A method as claimed in claim 4 or 5, wherein the mimic clock count mimics a count progression of the clock count for a clock signal having an idealised phase progression.

7. A method as claimed in claim 6, wherein the mimic clock count is based on the

reference clock signal and the mimic clock count is incremented by a Mimic-Rate for

T Re f

each reference clock cycle given by Mimic - Rate = Clock - Rate * — .

^ Clock

8. A method as claimed in claim 7, wherein the mimic-rate comprises a non- integer

number, Base. Fraction, and the mimic clock count is incremented by a Base-Rate for each reference clock cycle and is additionally incremented by a Fraction-Rate for each of a fraction of the reference clock cycles.

9. A method as claimed in any of claims 4 to 8, wherein step d. comprises generating a sample of each difference and obtaining a sum of the samples for a said plurality, N, of mimic clock counts and step e. comprises subtracting the oldest sample from the sum and adding the newest sample to the sum to provide a new sum.

10. Clock signal phase measurement apparatus comprising:

an input arranged to receive a clock signal comprising clock cycles having a clock frequency and a clock period, T_Ci_0Ck;

a reference clock signal generator arranged to provide a reference clock signal comprising reference clock cycles having a reference clock period, T_R^ and a reference clock frequency different to the clock frequency;

a controller arranged to:

i. receive the clock signal and the reference clock signal;

iii. obtain a sum of the phase differences for a said plurality of reference clock

cycles; iv. for each of the plurality of reference clock cycles, subtracting an oldest phase difference from the sum and adding the phase difference for the said reference clock cycle to the sum to provide a new sum, the new sum being indicative of the phase of the clock signal at the said reference clock cycle; and

v. generate a clock phase signal indicative of the new sum;

and,

an output arranged to deliver the clock phase signal.

11. Clock signal phase measurement apparatus as claimed in claim 10, wherein the

controller is arranged in step ii. to generate a clock count running on the clock signal and provide a mimic clock count and to determine a difference between respective pairs of the clock count and the mimic clock count, and the controller is arranged in step iii. to sum the differences.

12. Clock signal phase measurement apparatus as claimed in claim 11, wherein the

controller comprises: an edge detector arranged to edge detect the clock signal using the reference clock signal to generate the clock count; and a clock counter arranged to generate and increment the clock count by a Clock-Rate for each detected clock cycle of the clock signal, the Clock-Rate being given by Clock - Rate where T_Res is a required measurement resolution for the clock period.

13. Clock signal phase measurement apparatus as claimed in claim 11 or 12, wherein the controller is arranged to provide a mimic clock count which mimics a count progression of the clock count for a clock signal having an idealised phase progression.

14. Clock signal phase measurement apparatus as claimed in claim 13, wherein the

controller is arranged to base the mimic clock count on the reference clock signal and the controller is arran ed to increment the mimic clock count by a Mimic-Rate for each

15. Clock signal phase measurement apparatus as claimed in claim 14, wherein the mimic- rate comprises a non-integer number, Base. Fraction, and the controller comprises an incrementation signal generator arranged to generate a Base-Rate incrementation signal arranged to cause the mimic clock count to increment by a Base-Rate for each reference clock cycle and to generate a Fraction-Rate incrementation signal arranged to additionally cause the mimic clock count to increment by a Fraction-Rate for each of a fraction of the reference clock cycles.

16. Clock signal phase measurement apparatus as claimed in any of claims 10 to 15,

wherein the controller comprises: a sample generator arranged to generate a sample of each difference; a sample accumulator arranged to generate a sum of the samples for a said plurality, N, of mimic clock counts; and a running accumulator arranged to receive the sum of samples from the sample accumulator and to subtract the oldest sample from the sum and adding the newest sample to the sum to provide a new sum.

17. A communications network switch comprising:

an input arranged to receive a traffic carrying signal;

clock-recovery apparatus arranged to recover a clock signal from the traffic carrying signal; and

clock signal phase measurement apparatus as claimed any of claims 10 to 16.