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WO2012018119A1 - Cellule solaire et procédé de fabrication de cellule solaire - Google Patents

Cellule solaire et procédé de fabrication de cellule solaire Download PDF

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Publication number
WO2012018119A1
WO2012018119A1 PCT/JP2011/067961 JP2011067961W WO2012018119A1 WO 2012018119 A1 WO2012018119 A1 WO 2012018119A1 JP 2011067961 W JP2011067961 W JP 2011067961W WO 2012018119 A1 WO2012018119 A1 WO 2012018119A1
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Prior art keywords
semiconductor layer
solar cell
conductivity type
insulating layer
layer
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PCT/JP2011/067961
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English (en)
Japanese (ja)
Inventor
有二 菱田
利夫 浅海
森上　光章
仁 坂田
豊 桐畑
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H10F77/219—Arrangements for electrodes of back-contact photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H10F10/166—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Definitions

  • the present invention relates to a solar cell and a method for manufacturing a solar cell.
  • Patent Document 1 a so-called back junction type solar cell in which a plurality of types of semiconductor junctions are formed on the back side of the solar cell is known (for example, Patent Document 1 below).
  • this back junction solar cell it is not necessary to provide an electrode on the light receiving surface side. For this reason, in the back junction solar cell, the light receiving efficiency can be increased. Therefore, higher photoelectric conversion efficiency can be realized.
  • the present invention has been made in view of such a point, and an object thereof is to provide a solar cell having high photoelectric conversion efficiency.
  • the solar cell according to the present invention includes a crystalline semiconductor substrate, a first semiconductor layer, a first electrode, a second semiconductor layer, and a second electrode.
  • the crystalline semiconductor substrate has first and second main surfaces.
  • the crystalline semiconductor substrate has one of the first conductivity type of n-type and p-type.
  • the first semiconductor layer is formed on the first main surface.
  • the first semiconductor layer has the first conductivity type.
  • the first electrode is formed on the first semiconductor layer.
  • the second semiconductor layer is formed on the first main surface.
  • the second semiconductor layer has the other second conductivity type of n-type and p-type.
  • the second electrode is formed on the second semiconductor layer.
  • the first and second electrodes are formed in a region excluding the edge portion of the first main surface.
  • the solar cell according to the present invention further includes a third semiconductor layer.
  • the amorphous semiconductor layer is formed on at least a part of the edge portion of the first main surface where the first and second electrodes are not formed.
  • a method for manufacturing a solar cell according to the present invention includes a crystalline semiconductor substrate having first and second main surfaces and having one of n-type and p-type first conductivity types, and a first main surface.
  • a first semiconductor layer formed on the surface and having a first conductivity type; a first electrode formed on the first semiconductor layer; and formed on the first main surface.
  • a solar cell comprising: a second semiconductor layer having the second conductivity type of the other of n-type and p-type; and a second electrode formed on the second semiconductor layer It relates to a method for manufacturing.
  • the first and second electrodes are formed in a region excluding an edge portion of the first major surface. A first on at least a portion of the end edge of the main surface where the first and second electrode is not formed to form the third semiconductor layer.
  • a solar cell with high photoelectric conversion efficiency can be provided.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG.
  • FIG. 3 is a schematic cross-sectional view taken along line III-III in FIG. 1.
  • It is a flowchart showing the manufacturing process of the solar cell in 1st Embodiment.
  • It is schematic sectional drawing for demonstrating the manufacturing process of the solar cell in 1st Embodiment.
  • It is schematic sectional drawing for demonstrating the manufacturing process of the solar cell in 1st Embodiment.
  • It is schematic sectional drawing for demonstrating the manufacturing process of the solar cell in 1st Embodiment.
  • FIG. 1 is a plan view of the solar cell 1.
  • the IN stacked body 12 and the IP stacked body 13 are drawn.
  • the IN stacked body 12 and the IP stacked body 13 Since it is located under the electrode 15, it cannot be visually recognized.
  • the solar cell 1 is a back junction solar cell.
  • the solar cell 1 may be used as a solar cell module in which a plurality of solar cells 1 are connected by a wiring material. .
  • the solar cell 1 includes a semiconductor substrate 10.
  • the semiconductor substrate 10 has a light receiving surface 10a as a second main surface and a back surface 10b as a first main surface.
  • the semiconductor substrate 10 generates carriers by receiving the light 11 on the light receiving surface 10a.
  • the carriers are holes and electrons generated when light is absorbed by the semiconductor substrate 10.
  • the semiconductor substrate 10 is composed of a crystalline semiconductor substrate having n-type or p-type conductivity.
  • “Crystalline semiconductor substrate” means a single crystal semiconductor substrate or a polycrystalline semiconductor substrate. That is, the crystalline semiconductor substrate is not limited to a single crystal semiconductor substrate. Specific examples of the crystalline semiconductor substrate include a crystalline silicon substrate such as a single crystal silicon substrate and a polycrystalline silicon substrate.
  • the semiconductor substrate 10 is formed of an n-type crystalline silicon substrate will be described.
  • An i-type amorphous semiconductor layer 17 i is formed on the light receiving surface 10 a of the semiconductor substrate 10.
  • the i-type amorphous semiconductor layer 17i is made of an intrinsic amorphous semiconductor (hereinafter, the intrinsic semiconductor is referred to as an “i-type semiconductor”).
  • “Amorphous semiconductor” includes a microcrystalline semiconductor.
  • a microcrystalline semiconductor refers to a semiconductor in which the average particle diameter of semiconductor crystals precipitated in an amorphous semiconductor is in the range of 1 nm to 50 nm.
  • the semiconductor layer 17i is specifically formed of i-type amorphous silicon.
  • the thickness of the semiconductor layer 17i is not particularly limited as long as the thickness does not substantially contribute to power generation.
  • the thickness of the semiconductor layer 17i can be, for example, about several to 250 inches.
  • the n-type amorphous semiconductor layer 17n is formed on the semiconductor layer 17i.
  • the n-type amorphous semiconductor layer 17 n has the same conductivity type as that of the semiconductor substrate 10. That is, the semiconductor layer 17n is an amorphous semiconductor layer to which an n-type dopant is added and has an n-type conductivity type. Specifically, in the present embodiment, the semiconductor layer 17n is made of n-type amorphous silicon.
  • the thickness of the semiconductor layer 17n is not particularly limited. The thickness of the semiconductor layer 17n can be, for example, about 20 to 500 mm.
  • an insulating layer 16 having a function as an antireflection film and a function as a protective film is formed on the semiconductor layer 17n.
  • the insulating layer 16 can be formed of, for example, silicon oxide such as SiO2, silicon nitride such as SiN, or silicon oxynitride such as SiON.
  • the thickness of the insulating layer 16 can be appropriately set according to the antireflection characteristics of the antireflection film to be applied.
  • the thickness of the insulating layer 16 can be set to, for example, about 80 nm to 1 ⁇ m.
  • an IN stacked body 12 and an IP stacked body 13 are formed on the back surface 10b of the semiconductor substrate 10.
  • each of the IN laminated body 12 and the IP laminated body 13 is formed in a comb-tooth shape.
  • the IN stacked body 12 and the IP stacked body 13 are formed so as to be inserted into each other. For this reason, the IN stacked bodies 12 and the IP stacked bodies 13 are alternately arranged along the direction x perpendicular to the intersecting width direction y on the back surface 10b.
  • the adjacent IN stacked body 12 and the IP stacked body 13 are in contact with each other in the direction x.
  • the entire back surface 10 b is covered with the IN stacked body 12 and the IP stacked body 13.
  • Each of the width W1 (see FIG. 2) of the IN stacked body 12 and the interval W2 between the IN stacked bodies 12 in the direction x can be set to about 100 ⁇ m to 1.5 mm, for example.
  • the width W1 and the interval W2 may be equal to each other or may be different.
  • the IN stacked body 12 includes an i-type amorphous semiconductor layer 12i formed on the back surface 10b and an n-type amorphous semiconductor layer 12n formed on the i-type amorphous semiconductor layer 12i. It is constituted by the laminate.
  • the semiconductor layer 12i is made of an i-type semiconductor, like the semiconductor layer 17i.
  • the thickness of the semiconductor layer 12i is not particularly limited as long as the thickness does not substantially contribute to power generation.
  • the thickness of the semiconductor layer 12i can be, for example, about several to 250 inches.
  • the semiconductor layer 12n is doped with an n-type dopant similarly to the semiconductor layer 17n, and has an n-type conductivity type like the semiconductor substrate 10.
  • the semiconductor layer 12n is made of n-type amorphous silicon.
  • the thickness of the semiconductor layer 12n is not particularly limited. The thickness of the semiconductor layer 12n can be, for example, about 20 to 500 mm.
  • the insulating layer 18 is formed on both ends excluding the central portion in the direction x of the IN laminate 12.
  • the central portion in the direction x of the IN stacked body 12 is exposed from the insulating layer 18.
  • the width W3 in the direction x of the insulating layer 18 is not particularly limited, and can be, for example, about 1/3 of the width W1.
  • the interval W4 in the direction x between the insulating layers 18 is not particularly limited, and can be, for example, about 3 of the width W1.
  • the material of the insulating layer 18 is not particularly limited.
  • the insulating layer 18 can be formed of, for example, silicon oxide such as SiO 2, silicon nitride such as SiN, or silicon oxynitride such as SiON.
  • the insulating layer 18 can also be formed of a metal oxide such as titanium oxide or tantalum oxide.
  • the insulating layer 18 is formed of silicon nitride.
  • the insulating layer 18 improves the passivation of each of the semiconductor layers 12i, 12n, 13i, and 13p so that carriers generated in the semiconductor substrate 10 do not recombine in each of the semiconductor layers 12i, 12n, 13i, and 13p. Therefore, it is preferable that hydrogen is contained.
  • IP stack 13 has a portion exposed from the IN laminate 12 of the back surface 10b, it is formed on the end portion of the insulating layer 18. For this reason, both end portions of the IP stacked body 13 overlap with the IN stacked body 12 in the height direction z.
  • the IP stacked body 13 includes an i-type amorphous semiconductor layer 13i formed on the back surface 10b and a p-type amorphous semiconductor layer 13p formed on the i-type amorphous semiconductor layer 13i. It is constituted by the laminate.
  • the semiconductor layer 13i is made of an i-type semiconductor.
  • the thickness of the semiconductor layer 13i is not particularly limited as long as the thickness does not substantially contribute to power generation.
  • the thickness of the semiconductor layer 13i can be, for example, about several to 250 inches.
  • the semiconductor layer 13p is added p-type dopant, an amorphous semiconductor layer having p-type conductivity. Specifically, in the present embodiment, the semiconductor layer 13p is made of p-type amorphous silicon.
  • the thickness of the semiconductor layer 13p is not particularly limited. The thickness of the semiconductor layer 13p can be, for example, about 20 to 500 mm.
  • the semiconductor layer 13i having a thickness that does not substantially contribute to power generation is provided between the crystalline semiconductor substrate 10 and the semiconductor layer 13p.
  • each of the semiconductor layers 17n, 12n, 13p, 17i, 12i, and 13i contains hydrogen in order to improve the passivation property of each junction interface.
  • An electrode 14 for collecting holes is formed on the semiconductor layer 12n.
  • an electrode 15 for collecting electrons is formed on the semiconductor layer 13p.
  • the distance W5 between the electrodes 14 and 15 in the top of the insulating layer 18, for example, may be about 1/3 of the width W3.
  • each of the IN laminate 12 and the IP laminate 13 is formed in a comb shape.
  • the electrodes 14 and 15 are formed in a comb-tooth shape including a bus bar and a plurality of fingers.
  • the electrodes 14 and 15 may be so-called bus bar-less electrodes that are configured by only a plurality of fingers and do not have a bus bar.
  • the electrodes 14 and 15 are not particularly limited as long as they can collect carriers.
  • the electrodes 14 and 15 can be made of, for example, a metal such as Cu or Ag, or an alloy containing one or more of these metals.
  • the electrodes 14 and 15 can also be formed by, for example, TCO (Transparent Conductive Oxide) such as ITO (Indium Tin Oxide).
  • TCO Transparent Conductive Oxide
  • ITO Indium Tin Oxide
  • the electrodes 14 and 15 may be composed of a laminate of a plurality of conductive layers made of the above metal, alloy or TCO.
  • the electrodes 14 and 15 are formed in the central portion excluding the edge portion of the back surface 10b.
  • the central portion of the back surface 10b where the electrodes 14 and 15 are formed is defined as a region 10b1.
  • the edge part in which the electrodes 14 and 15 are not formed among the back surfaces 10b is set as the area
  • the amorphous semiconductor layer 32 is formed on at least a part of the region 10b2 where the back surface 10b is exposed. Specifically, in the present embodiment, substantially the entire region 10 b 2 is covered with the amorphous semiconductor layer 32.
  • the amorphous semiconductor layer 32 contains hydrogen in order to improve the passivation property of the amorphous semiconductor layer 32 so that carriers generated in the semiconductor substrate 10 do not recombine in the amorphous semiconductor layer 32. preferable.
  • the amorphous semiconductor layer 32 includes an i-type amorphous semiconductor layer 32i and an n-type amorphous semiconductor layer 32n.
  • the semiconductor layer 32i is formed on the region 10b2.
  • the semiconductor layer 32i is made of an intrinsic amorphous semiconductor.
  • the semiconductor layer 32i can be formed of, for example, i-type amorphous silicon.
  • the semiconductor layer 32i is preferably made of the same material as the semiconductor layer 12i.
  • the thickness of the semiconductor layer 32i is not particularly limited. The thickness of the semiconductor layer 32i can be, for example, about several to 250 inches.
  • the amorphous semiconductor layer 32n is formed on the semiconductor layer 32i.
  • the semiconductor layer 32 n has the same n-type conductivity as that of the semiconductor substrate 10.
  • the semiconductor layer 32n can be formed of, for example, n-type amorphous silicon.
  • the semiconductor layer 32n is preferably made of the same material as the semiconductor layer 12n.
  • the thickness of the semiconductor layer 32n is not particularly limited. The thickness of the semiconductor layer 32n can be, for example, about 20 to 500 mm.
  • An insulating layer 33 is formed on the amorphous semiconductor layer 32.
  • the insulating layer 33 covers substantially the entire amorphous semiconductor layer 32.
  • Insulating layer 33 is, for example, may be formed of a silicon oxide, silicon nitride, silicon oxynitride, a metal oxide such as titanium oxide or tantalum oxide.
  • the insulating layer 33 is preferably formed of silicon oxide, silicon nitride, or silicon oxynitride.
  • the insulating layer 33 is preferably made of the same material as the insulating layer 18.
  • the insulating layer 33 improves the passivation of each of the semiconductor layers 12i, 12n, 13i, and 13p so that carriers generated in the semiconductor substrate 10 do not recombine in each of the semiconductor layers 12i, 12n, 13i, and 13p. Therefore, it is preferable that hydrogen is contained.
  • the thickness of the insulating layer 33 is not particularly limited. The thickness of the insulating layer 33 can be, for example, about 10 nm to 1 ⁇ m.
  • An amorphous semiconductor layer 34 is formed on the insulating layer 33.
  • the amorphous semiconductor layer 34 substantially covers the entire insulating layer 33.
  • the amorphous semiconductor layer 34 includes an i-type amorphous semiconductor layer 34i and a p-type amorphous semiconductor layer 34p.
  • the semiconductor layer 34 i is formed on the insulating layer 33.
  • the semiconductor layer 34i is made of an intrinsic amorphous semiconductor.
  • the semiconductor layer 34i can be formed of, for example, i-type amorphous silicon. In the present embodiment, the semiconductor layer 34i is formed integrally with the semiconductor layer 13i located closest to the region 10b2.
  • the semiconductor layer 34p is formed on the semiconductor layer 34i.
  • the semiconductor layer 34p is made of a p-type amorphous semiconductor.
  • the semiconductor layer 34p can be formed of, for example, p-type amorphous silicon.
  • the semiconductor layer 34p is formed integrally with the semiconductor layer 13p.
  • the amorphous semiconductor layer 32 is formed on the region 10b2.
  • substantially the entire region 10 b 2 is covered with the amorphous semiconductor layer 32. Accordingly, recombination of minority carriers in the region 10b2 can be effectively suppressed. As a result, high photoelectric conversion efficiency can be realized.
  • the amorphous semiconductor layer 32 contains hydrogen, recombination of minority carriers in the region 10b2 can be more effectively suppressed. As a result, higher photoelectric conversion efficiency can be realized.
  • the semiconductor layer 32i in contact with the semiconductor substrate 10 is made of an intrinsic semiconductor. For this reason, the semiconductor layer 32i has few defects. Accordingly, recombination of minority carriers in the region 10b2 can be more effectively suppressed. As a result, higher photoelectric conversion efficiency can be realized.
  • the semiconductor layer 32n is formed having the same conductivity type as the semiconductor substrate 10. For this reason, a BSF (Back Surface Field) effect is produced by the stacked body of the semiconductor layers 32i and 32n. As a result, higher photoelectric conversion efficiency can be realized.
  • BSF Back Surface Field
  • the electrodes 14 and 15 are formed up to the edge of the back surface 10b and the region 10b2 is not provided. However, for example, when forming the electrodes 14 and 15 made of a plating film, a region for preventing the electrodes 14 and 15 from being formed beyond the edge is required on the back surface 10b. it is preferable to provide a.
  • the insulating layer 33 is formed on the amorphous semiconductor layer 32. For this reason, for example, it is possible to effectively suppress the occurrence of defects in the amorphous semiconductor layer 32 due to intrusion of heavy metal ions, alkali metal ions, transition metal ions, and the like into the amorphous semiconductor layer 32. As a result, high photoelectric conversion efficiency can be maintained over a long period of time. Insulating layer 33, silicon oxide, preferably formed of silicon nitride, the silicon oxynitride, and more preferably formed of silicon nitride. This is because the weather resistance and gas barrier properties of the insulating layer 33 can be improved, and the penetration of various ions into the amorphous semiconductor layer 32 can be more effectively suppressed.
  • the semiconductor substrate 10 is covered with the semiconductor layer 12i in a region where the electrodes 14 and 15 between the electrodes 14 and 15 in the region 10b1 are not formed. Therefore, recombination of minority carriers in a region where the electrode 14 and 15 between the electrodes 14 and 15 in the region 10b1 are not formed can be effectively suppressed. Therefore, higher photoelectric conversion efficiency can be realized.
  • FIGS. 7 to 13 are cross-sectional views of the portion including the edge portion, as in FIG.
  • a semiconductor substrate 10 (see FIG. 5) is prepared.
  • step S1 the light receiving surface 10a and the back surface 10b of the semiconductor substrate 10 are cleaned.
  • the semiconductor substrate 10 can be cleaned using, for example, an HF aqueous solution.
  • step S2 a semiconductor layer 17i and a semiconductor layer 17n are formed on the light receiving surface 10a of the semiconductor substrate 10, and an i-type amorphous material is formed on the back surface 10b.
  • each of the semiconductor layers 17i, 17n, 21, 22 is not particularly limited.
  • the semiconductor layers 17i, 17n, 21, and 22 can be formed by, for example, a CVD (Chemical Vapor Deposition) method such as a plasma CVD method or a thin film forming method such as a sputtering method.
  • CVD Chemical Vapor Deposition
  • the insulating layer 16 is formed on the semiconductor layer 17n, and the insulating layer 23 is formed on the semiconductor layer 22.
  • the formation method of the insulating layers 16 and 23 is not specifically limited.
  • the insulating layers 16 and 23 can be formed by, for example, a thin film forming method such as a sputtering method or a CVD method.
  • step S4 the insulating layer 23 is etched to remove a part of the insulating layer 23. Specifically, of the insulating layer 23, the portion located over the area which process bonding the p-type semiconductor layer on the semiconductor substrate 10 in a later removed. Thereby, the insulating layer 23a and the insulating layer 33 shown in FIG. 3 are formed.
  • the insulating layer 23 can be etched using an acidic etching solution such as an HF aqueous solution, for example, when the insulating layer 23 is made of silicon oxide, silicon nitride, or silicon oxynitride.
  • step S5 the semiconductor layers 21 and 22 are etched using an alkaline etchant using the insulating layers 23a and 33 as a mask. By this etching, portions other than the portions covered by the insulating layers 23a and 33 of the semiconductor layer 21 and the semiconductor layer 22 are removed. This exposes a portion of the back surface 10b where the insulating layer 23 is not located above, and forms the semiconductor layers 12i, 12n, 32i, and 32n from the semiconductor layers 21 and 22.
  • the insulating layers 23a and 33 are made of silicon oxide, silicon nitride, or silicon oxynitride. For this reason, although the etching rate of the insulating layers 23a and 33 by the acidic etching solution is high, the etching rate of the insulating layers 23a and 33 by the alkaline etching solution is low.
  • the semiconductor layers 21 and 22 are made of amorphous silicon. For this reason, the semiconductor layers 21 and 22 have a low etching rate with an acidic etching solution and a high etching rate with an alkaline etching solution.
  • the insulating layers 23a and 33 are etched by the acidic etching solution used in step S4, the semiconductor layers 21 and 22 are not substantially etched.
  • the semiconductor layers 21 and 22 are etched by the alkaline etching solution used in step S5, but the insulating layers 23a and 33 are not substantially etched. Therefore, in steps S4 and S5, the insulating layers 23a and 33 or the semiconductor layers 21 and 22 can be selectively etched.
  • step S6 the i-type amorphous semiconductor layer 24 and the p-type amorphous semiconductor layer 25 are sequentially formed in this order so as to cover the back surface 10b.
  • a method for forming the amorphous semiconductor layers 24 and 25 is not particularly limited.
  • the semiconductor layers 24 and 25 can be formed by, for example, a thin film forming method such as a sputtering method or a CVD method.
  • step S7 a part of the portion of the semiconductor layers 24 and 25 (see FIG. 9) located on the insulating layer 23a is etched. Thereby, the semiconductor layers 13i, 13p, 34i, and 34p are formed from the amorphous semiconductor layers 24 and 25.
  • step S7 a first etching agent having an etching rate for the amorphous semiconductor layers 24 and 25 (see FIG. 9) larger than that for the insulating layers 23a and 33 is used. Therefore, in the insulating layer 23a, 33 and the amorphous semiconductor layer 24, the amorphous semiconductor layers 24 and 25 are selectively etched.
  • a specific example of the first etching agent is an aqueous NaOH solution containing NaOH.
  • the insulating layer 23a is etched in step S8. Specifically, the exposed portion of the insulating layer 23 is removed from above the semiconductor layers 13i, 13p, 34i, and 34p by etching using a second etching agent. Thus, the semiconductor layer 12n is exposed and the insulating layer 18 is formed from the insulating layer 23a.
  • a second etching agent having an etching rate for the insulating layer 23a larger than that for the semiconductor layers 13i, 13p, 34i, and 34p is used. For this reason, the insulating layer 23a is selectively etched among the insulating layer 23a and the semiconductor layers 13i, 13p, 34i, and 34p.
  • a specific example of the second etching agent is an HF aqueous solution containing HF.
  • the solar cell 1 can be completed by performing the electrode formation process which forms the electrodes 14 and 15 on each of the semiconductor layer 12n and the semiconductor layer 13p in step S9. .
  • the formation method of the electrodes 14 and 15 can be suitably selected according to the material of the electrode. Specifically, in this embodiment, the electrodes 14 and 15 are formed as follows.
  • a conductive layer 26 made of TCO and a conductive layer 27 made of a metal or alloy such as Cu are formed into a thin film such as a CVD (Chemical Vapor Deposition) method such as a plasma CVD method or a sputtering method. by law they are formed in this order.
  • CVD Chemical Vapor Deposition
  • the portions of the conductive layers 26 and 27 located on the insulating layer 18 are divided by, for example, photolithography. At the same time, the portions of the conductive layers 26 and 27 located on the insulating layer 33 are also etched. Then, the semiconductor layers 13i, 13p, 34i, and 34p located on the insulating layer 18 are also divided at the same time. Next, the electrodes 14 and 15 can be completed by forming a plating film on the conductive layer 27.
  • the manufacturing method of the solar cell 1 is formed by an amorphous semiconductor layer 32 and the IN laminate 12 common process.
  • the insulating layer 33 is formed by a process common to the insulating layer 18. Therefore, the solar cell 1 can be easily manufactured with a small number of processes without complicating the manufacturing process.
  • the insulating layer 33 is damaged or removed, for example, in the step of forming the insulating layer 18 by etching the insulating layer 23a or the step of dividing the conductive layers 26 and 27. It may be done.
  • the insulating layer 33 is covered with the amorphous semiconductor layer 34. For this reason, it can suppress effectively that the insulating layer 33 is damaged or removed in the etching process of the insulating layer 23a, the dividing process of the conductive layers 26 and 27, and the like.
  • the amorphous semiconductor layer 34 is formed integrally with the IP stacked body 13 adjacent to the region 10b2. Therefore, the manufacturing process of the solar cell 1 can be simplified.
  • FIG. 14 is a schematic cross-sectional view of an edge portion of a solar cell according to a modification (first modification) of the first embodiment.
  • the i-type amorphous semiconductor layer 32i is formed on the back surface 10b of the semiconductor substrate 10, and the n-type amorphous semiconductor layer 32i has n.
  • the example in which the type amorphous semiconductor layer 32n is formed has been described.
  • an n-type amorphous semiconductor layer may be formed immediately above the back surface 10b of the semiconductor substrate 10 without interposing an i-type amorphous semiconductor layer.
  • an amorphous semiconductor layer 34 formed of a stacked body of an i-type amorphous semiconductor layer 34i and a p-type amorphous semiconductor layer 34p may be provided on the back surface 10b.
  • a p-type amorphous semiconductor layer may be formed immediately above the back surface 10b.
  • the insulating layer is not formed.
  • the amorphous semiconductor layer 34 is not electrically connected to any of the electrodes 14 and 15.
  • FIGS. 29 to 30 may be used. Specifically, this will be described with reference to FIGS.
  • FIG. 29 is a schematic cross-sectional view of a second modification corresponding to the schematic cross-sectional view (FIG. 3) of the first embodiment.
  • the second modification is different from the first embodiment in that the i-type amorphous semiconductor layer 34i and the p-type amorphous semiconductor layer 34p are formed on the back surface region 10b2 of the semiconductor substrate 10. It is a point provided with the IP laminated body 34 laminated
  • the stack position of the IP stacked body 34 in the region 10b1 of the first embodiment is the region.
  • the configuration is opposite to that formed on the semiconductor substrate 10 side of the stacking position of the 10b2 IP stack 34. That is, in the second modification, the stack position of the IP stacked body 34 in the region 10b2 is formed closer to the semiconductor substrate 10 than the stack position of the IP stacked body 34 in the region 10b1.
  • the conductive layers 26 and 27 on the region 10b2 are removed. Then, electrodes 14 and 15 made of a plating film are formed on the remaining conductive layers 26 and 27. Then, the solar cell 1 of FIG. 29 provided with the IP stacked body 34 in which the i-type amorphous semiconductor layer 34i and the p-type amorphous semiconductor layer 34p are stacked in this order is obtained in the region 10b1.
  • the IN stacked body 32 in which the i-type amorphous semiconductor layer 32i and the n-type amorphous semiconductor layer 32n are stacked in this order is etched, then the insulating layers 18 and 33 are etched, and then the i-type amorphous semiconductor layer 32n is etched.
  • the stacked structure of the solar cell 1 of FIG. 29 is obtained by etching the IP stacked body 34 in which the amorphous semiconductor layer 34i and the p-type amorphous semiconductor layer 34p are stacked in this order.
  • Figure 30 a schematic cross-sectional view of a third modified example corresponding to the schematic cross-sectional view of the first embodiment (FIG. 3).
  • the third modification is different from the first embodiment in that an i-type amorphous semiconductor layer 34i and a p-type amorphous semiconductor layer 34p are formed on a region 10b2 on the back surface side of the semiconductor substrate 10. It is a point provided with the IP laminated body 34 and the insulating layer 33 laminated
  • the region 10b2 When manufacturing the third modification, after forming the i-type amorphous semiconductor layer 34i and the p-type amorphous semiconductor layer 34p on the entire surface of the n-type semiconductor substrate 10, the region 10b2 The upper i-type amorphous semiconductor layer 34i and p-type amorphous semiconductor layer 34p are removed. Then, conductive layers 26 and 27 are formed only on the remaining i-type amorphous semiconductor layer 34 i and p-type amorphous semiconductor layer 34 p, and an electrode 14 made of a plating film is formed on the conductive layers 26 and 27. , to form a 15. As a result, the solar cell 1 of FIG. 30 including the IP stacked body 34 and the insulating layer 33 in which the i-type amorphous semiconductor layer 34i and the p-type amorphous semiconductor layer 34p are stacked in this order is obtained in the region 10b2. .
  • FIG. 15 is a schematic plan view of a solar cell in the second embodiment.
  • FIG. 16 is a schematic cross-sectional view of the central portion of the solar cell in the second embodiment.
  • FIG. 17 is a schematic cross-sectional view of an edge portion of the solar cell in the second embodiment.
  • the insulating layer 18 is formed on both ends in the x direction of the n-type amorphous semiconductor layer 12n, and the p-type amorphous is formed on the insulating layer 18.
  • An example in which a part of the semiconductor layer 13p is located has been described.
  • the insulating layer 18 is formed on the p-type amorphous semiconductor layer 13p, and a part of the n-type amorphous semiconductor layer 12n is formed on the insulating layer 18. positioned.
  • the solar cell 2 has substantially the same configuration as the solar cell 1 according to the first embodiment.
  • the minority carriers are holes. Accordingly, to suppress loss due to recombination of holes which are minority carriers is important from the viewpoint of enhancing the photoelectric conversion efficiency of the solar cell 1.
  • minority carriers (holes) generated below the p-type amorphous semiconductor layer 13p have a short moving distance until they are collected by the electrode 15. For this reason, minority carriers generated below the p-type amorphous semiconductor layer 13p are unlikely to disappear due to recombination before being collected by the electrode 15.
  • the minority carriers generated below the n-type amorphous semiconductor layer 12n have a long distance that must be moved before being collected by the electrode 15. For this reason, minority carriers generated below the n-type amorphous semiconductor layer 12 n are likely to disappear due to recombination before being collected by the electrode 15.
  • the widths of the n-type amorphous semiconductor layer 12n and the p-type amorphous semiconductor layer 13p are reduced and the width of the n-type amorphous semiconductor layer 12n is set to p. It is preferable to make it relatively small with respect to the type amorphous semiconductor layer 13p. By doing so, the distance that minority carriers must travel before being collected by the electrode 15 can be reduced.
  • the width of the semiconductor layer located under the insulating layer cannot be reduced so much. Therefore, when the n-type amorphous semiconductor layer 12n is located under the insulating layer 18 as in the solar cell 1 according to the first embodiment, the width of the n-type amorphous semiconductor layer 12n is sufficiently large. can not be reduced to.
  • the p-type amorphous semiconductor layer 13p is located under the insulating layer 18, and the insulating layer is formed on the n-type amorphous semiconductor layer 12n. It has not been. For this reason, it becomes easy to make the width of the n-type amorphous semiconductor layer 12n relatively smaller than the p-type amorphous semiconductor layer 13p. Accordingly, it is possible to reduce the distance that must be traveled before the holes generated below the n-type amorphous semiconductor layer 12n are collected by the electrode 15. As a result, recombination of minority carriers can be suppressed. Therefore, the photoelectric conversion efficiency of the solar cell 2 can be improved.
  • the width of the p-type amorphous semiconductor layer 13p along the x direction is 1.1 times or more than the width of the n-type amorphous semiconductor layer 12n along the x direction. Preferably, it is 1.5 times or more.
  • the semiconductor substrate 10 is n-type, it is preferable to make the semiconductor layer located under the insulating layer 18 p-type.
  • the insulating layer is preferably n-type. That is, it is preferable that the semiconductor layer located under the semiconductor layer has a conductivity type different from that of the semiconductor substrate so as to improve passivation properties so that carriers generated in the semiconductor substrate 10 do not recombine.
  • FIG. 18 is a flowchart showing the manufacturing process of the solar cell in the second embodiment.
  • 19 to 27 are schematic cross-sectional views for explaining a manufacturing process of the solar cell in the second embodiment. Next, an example of a method for manufacturing the solar cell 2 will be described with reference to FIGS. 19 to 27 are cross-sectional views of the portion including the edge portion, similarly to FIG.
  • step S11 the light receiving surface 10a and the back surface 10b of the semiconductor substrate 10 are cleaned in the same manner as in step S1 of the first embodiment.
  • step S12 the semiconductor layer 17i and the semiconductor layer 17n are formed on the light receiving surface 10a of the semiconductor substrate 10, and the i-type amorphous semiconductor layer 21 is formed on the back surface 10b.
  • a p-type amorphous semiconductor layer 40 is formed.
  • step S13 the insulating layer 16 is formed on the semiconductor layer 17n, and the insulating layer 23 is formed on the semiconductor layer 40.
  • step S14 the insulating layer 23 is etched to remove a part of the insulating layer 23. Specifically, of the insulating layer 23, the portion located over the area which process bonding the n-type semiconductor layer on the semiconductor substrate 10 in a later removed. Thereby, the insulating layer 23a and the insulating layer 33 are formed.
  • step S15 using the insulating layers 23a and 33 as a mask, the semiconductor layer 21 (see FIG. 21) and the semiconductor layer 40 (see FIG. 21) are mixed with an alkaline etching solution. Etching is used to remove portions of the semiconductor layer 21 and the semiconductor layer 40 other than the portions covered with the insulating layers 23a and 33. As a result, the portion of the back surface 10b where the insulating layer 23 is not located above is exposed, and the semiconductor layers 13i, 13p, 34i, and 34p are formed from the semiconductor layers 21 and 40.
  • step S16 the i-type amorphous semiconductor layer 24 and the n-type amorphous semiconductor layer 41 are sequentially formed in this order so as to cover the exposed portion of the back surface 10b.
  • step S17 etching the portion of the portion located on the insulating layer 23a of the semiconductor layer 24, 41.
  • the semiconductor layers 12i, 12n, 32i, and 32n are formed from the amorphous semiconductor layers 24 and 41.
  • step S18 the insulating layer 23a is etched. Specifically, the exposed portion of the insulating layer 23 is removed by etching from above the semiconductor layers 12i, 12n, 32i, and 32n using a second etching agent. Thereby, the semiconductor layer 13p is exposed and the insulating layer 18 is formed from the insulating layer 23a.
  • step S19 the solar cell 2 can be completed by performing an electrode formation process for forming the electrodes 14 and 15 on the semiconductor layer 12n and the semiconductor layer 13p, respectively. it can.
  • a conductive layer 26 made of TCO and a conductive layer 27 made of a metal or alloy such as Cu first, a CVD (Chemical Vapor Deposition) method such as a plasma CVD method, a sputtering method, or the like. These are formed in this order by the thin film forming method.
  • CVD Chemical Vapor Deposition
  • the portions of the conductive layers 26 and 27 located on the insulating layer 18 are divided by, for example, photolithography. At the same time, the portions of the conductive layers 26 and 27 located on the insulating layer 33 are also etched. Then, the semiconductor layers 12i, 12n, 32i, and 32n located on the insulating layer 18 are also divided at the same time. Next, the electrodes 14 and 15 can be completed by forming a plating film on the conductive layer 27.
  • the solar cell 2 can be easily manufactured by a small number of processes without complicating the manufacturing process. Moreover, since the insulating layer 33 is covered with the amorphous semiconductor layer 32, it is possible to effectively suppress the insulating layer 33 from being damaged or removed in the manufacturing process of the solar cell 2.
  • the amorphous semiconductor layer 32 is formed integrally with the IN stacked body 12 adjacent to the region 10b2. Therefore, the manufacturing process of the solar cell 2 can be simplified.
  • the p-type amorphous semiconductor layer 13p is formed before the n-type amorphous semiconductor layer 12n.
  • the semiconductor layers 13i and 13p are formed on the back surface 10b immediately after the substrate 10 is cleaned in step S1. For this reason, the cleanliness of the back surface 10b immediately before forming the semiconductor layers 13i and 13p can be further increased. Therefore, a higher quality pn junction can be formed. Therefore, higher photoelectric conversion efficiency can be obtained.
  • FIG. 28 is a schematic cross-sectional view of an edge portion of a solar cell according to a modification (second modification) of the second embodiment.
  • the i-type amorphous semiconductor layer 34i is formed on the back surface 10b of the semiconductor substrate 10, and the p-type amorphous semiconductor layer 34i has a p
  • the example in which the type amorphous semiconductor layer 34p is formed has been described.
  • a p-type amorphous semiconductor layer may be formed immediately above the back surface 10b of the semiconductor substrate 10 without using an i-type amorphous semiconductor layer.
  • an amorphous semiconductor layer 32 made of a stacked body of an i-type amorphous semiconductor layer 32i and an n-type amorphous semiconductor layer 32n may be provided on the back surface 10b.
  • an n-type amorphous semiconductor layer may be formed directly on the back surface 10b.
  • the amorphous semiconductor layer 32 is not electrically connected to any of the electrodes 14 and 15.
  • the present invention is not limited to this configuration.
  • a p-type amorphous semiconductor layer may be provided immediately above the back surface 10b without providing an i-type amorphous semiconductor layer.
  • n-type amorphous semiconductor layer 24 ... i-type amorphous semiconductor layer 25 ... p-type amorphous semiconductor layers 26, 27 ... conductive layer 32 ... amorphous Semiconductor layer 32i ... i-type amorphous semiconductor layer 32n ... n-type amorphous semiconductor layer 34 ... amorphous semiconductor layer 34i ... i-type amorphous semiconductor layer 34p ... p-type amorphous semiconductor layer

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Abstract

Le problème à résoudre est de produire une cellule solaire ayant un rendement de conversion photoélectrique élevé. A cet effet, l'invention porte sur une cellule solaire (1) qui comprend : un substrat semi-conducteur cristallin (10) qui possède un premier type de conductivité ; une première couche semi-conductrice (12n) qui possède le premier type de conductivité ; une première électrode (14) qui est formée sur la première couche semi-conductrice (12n) ; une deuxième couche semi-conductrice (13p) qui possède un second type de conductivité ; et une seconde électrode (15) qui est formée sur la deuxième couche semi-conductrice (13p). Les première et deuxième couches semi-conductrices (12n, 13p) sont formées sur une première surface principale (10a). Les première et seconde électrodes (14, 15) sont formées dans une région (10b1) de la première surface principale (10a) excluant une partie de bord d'extrémité (10b2). La cellule solaire (1) comprend de plus une troisième couche semi-conductrice (32). La couche semi-conductrice amorphe (32) est formée sur au moins une partie de la partie de bord d'extrémité (10b2).
PCT/JP2011/067961 2010-08-06 2011-08-05 Cellule solaire et procédé de fabrication de cellule solaire Ceased WO2012018119A1 (fr)

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JPWO2018037672A1 (ja) * 2016-08-22 2019-06-20 株式会社カネカ 太陽電池および太陽電池モジュール

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