WO2012008018A1 - Semiconductor device and method for manufacturing same - Google Patents

Abstract

Disclosed is a semiconductor device provided with: a semiconductor substrate (1) comprising an integrated circuit; a first wiring film (3A) provided above the semiconductor substrate; an insulating film (4) provided on the first wiring film and comprising a through hole (4A); a second wiring film (3B) provided on the insulating film; and a resistive element (2) provided in the through hole and connected to the integrated circuit by way of the first wiring film and the second wiring film.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof.

Conventionally, a polysilicon layer, a diffusion layer, or the like is used as a resistance element connected to an integrated circuit provided in a semiconductor device. These are called polysilicon resistors and diffused resistors.

JP 2005-158930 A Japanese Patent Laid-Open No. 10-308452

By the way, when the resistors such as the polysilicon resistor and the diffused resistor are provided above a semiconductor substrate (bulk) having an integrated circuit, they are formed to extend in a direction parallel to the surface of the semiconductor substrate (see FIG. 22). . For this reason, an area for providing these resistors is required.
In particular, as shown in FIG. 22, when a long resistor array in which a plurality of resistors 100 are connected in series via a metal wiring 101 is provided, the plurality of resistors 100 connected in series via the metal wiring 101 are connected to a semiconductor substrate. It is arranged two-dimensionally above 102. For this reason, a large area (bulk area) is required to provide the resistor string. This leads to an increase in chip area and leads to an increase in cost.

Therefore, when the resistance element connected to the integrated circuit is provided above the semiconductor substrate having the integrated circuit, it is desired to reduce the area for providing the resistance element.

Therefore, the semiconductor device includes a semiconductor substrate having an integrated circuit, a first wiring film provided above the semiconductor substrate, an insulating film provided on the first wiring film and having a through hole, and an insulating film on the insulating film. And a resistance element provided in the through hole and connected to the integrated circuit via the first wiring film and the second wiring film.
In this method of manufacturing a semiconductor device, a first wiring film is formed above a semiconductor substrate having an integrated circuit, an insulating film is formed on the first wiring film, a through hole is formed in the insulating film, and the insulating film is formed on the insulating film. In addition to forming the second wiring film, it is necessary to form a resistance element connected to the integrated circuit through the first wiring film and the second wiring film in the through hole.

Therefore, according to the semiconductor device and the manufacturing method thereof, when the resistance element connected to the integrated circuit is provided above the semiconductor substrate having the integrated circuit, the area for providing the resistance element can be reduced. There are advantages.

It is a schematic diagram which shows the structure of the resistive element with which the semiconductor device concerning one Embodiment is equipped. It is a schematic diagram which shows the structure of the resistive element with which the semiconductor device concerning one Embodiment is equipped. It is a schematic diagram which shows the structure of the resistive element with which the semiconductor device concerning one Embodiment is equipped. It is a schematic diagram which shows the structure of the resistive element with which the semiconductor device concerning one Embodiment is equipped. FIG. 5A to FIG. 5C are schematic views showing the configuration of the resistance element provided in the semiconductor device according to the embodiment. It is a schematic diagram which shows the structure of the resistive element with which the semiconductor device concerning one Embodiment is equipped. FIG. 7A and FIG. 7B are schematic views showing the configuration of the resistance element provided in the semiconductor device according to the embodiment. FIG. 8A to FIG. 8C are schematic views showing the configuration of the resistance element provided in the semiconductor device according to the embodiment. It is a figure which shows one structural example of R-DAC with which the semiconductor device concerning one Embodiment is equipped. It is a figure which shows one structural example of R-DAC with which the semiconductor device concerning one Embodiment is equipped. It is a figure which shows the other structural example of R-DAC with which the semiconductor device concerning one Embodiment is equipped. It is a figure which shows the other structural example of R-DAC with which the semiconductor device concerning one Embodiment is equipped. It is a figure which shows the other structural example of R-DAC with which the semiconductor device concerning one Embodiment is equipped. It is a figure which shows the relationship of the input code of another structure example of R-DAC with which the semiconductor device concerning one Embodiment is provided, the number of resistive elements, and an output voltage level. It is a figure which shows the voltage characteristic of the other structural example of R-DAC with which the semiconductor device concerning one Embodiment is equipped. It is a figure which shows the structure of the resistance string contained in the other structural example of R-DAC with which the semiconductor device concerning one Embodiment is equipped. It is a figure which shows the structure of the selector circuit contained in the other structural example of R-DAC with which the semiconductor device concerning one Embodiment is equipped. It is a figure which shows the structure of the voltage follower circuit contained in the other structural example of R-DAC with which the semiconductor device concerning one Embodiment is equipped. It is a figure which shows the structure of the band gap reference circuit with which the semiconductor device concerning other embodiment is equipped. 20A and 20B are diagrams showing the configuration of an I / O buffer circuit provided in a semiconductor device according to another embodiment. It is a figure which shows the structure of the cell of SRAM with which the semiconductor device concerning other embodiment is equipped. It is a schematic diagram which shows the conventional semiconductor device which uses a polysilicon resistance as a resistive element connected to an integrated circuit.

Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to FIGS. 1 to 18 with reference to the drawings.
As shown in FIG. 1, the semiconductor device according to the present embodiment includes a semiconductor substrate 1 having an integrated circuit, and a resistance element 2 provided above the semiconductor substrate 1 and connected to the integrated circuit. An integrated circuit provided on the semiconductor substrate 1 is referred to as a semiconductor integrated circuit.

Here, a wiring film (first wiring film; lower wiring film) 3A, an insulating film (interlayer insulating film) 4, and a wiring film (second wiring film; upper wiring film) 3B are sequentially stacked above the semiconductor substrate 1. The resistance element 2 is provided in the through hole 4A provided in the insulating film 4. The upper and lower wiring films 3A and 3B are connected to an integrated circuit (not shown). Further, since the resistance element 2 is in contact with the upper and lower wiring films 3A and 3B, the resistance element 2 is connected to the integrated circuit via the upper and lower wiring films 3A and 3B. Here, although the lower wiring film is indicated by reference numeral 3A and the upper wiring film is indicated by reference numeral 3B, the wiring film is indicated by reference numeral 3 when it is not necessary to distinguish the upper and lower sides.

That is, this semiconductor device includes a wiring film 3A provided above the semiconductor substrate 1, an insulating film 4 provided on the wiring film 3A and having a through hole 4A, and a wiring film 3B provided on the insulating film 4. And a resistance element 2 provided in the through hole 4A and connected to the integrated circuit via the wiring films 3A and 3B.
Here, the wiring films 3A and 3B are made of a metal material. This is also called a metal wiring film or a metal film.

The resistance element 2 is made of the same metal material as the wiring films 3A and 3B. This is also called a metal resistance element. The resistive element 2 is a via-shaped resistive element having an aspect ratio that can function as a resistive element in an integrated circuit. The via-shaped resistance element 2 has an aspect ratio defined by the shape of the through hole 4A provided in the insulating film 4, that is, the thickness of the insulating film 4 and the diameter of the through hole 4A. Can function as. Thereby, for example, the area for providing the resistance element can be reduced as compared with the case where a resistance element such as a polysilicon resistance or a diffusion resistance is provided.

The semiconductor device configured as described above can be manufactured as follows, as in the case of forming a multilayer wiring layer having vias.
First, the wiring film 3A is formed above the semiconductor substrate 1 having an integrated circuit.
Next, the insulating film 4 is formed on the wiring film 3A.
Next, a through hole 4 </ b> A is formed in the insulating film 4.

Then, a wiring film 3B is formed on the insulating film 4 so as to fill the through hole 4A. Thereby, the resistance element 2 in contact with the upper and lower wiring films 3A and 3B is formed in the through hole 4A. In this manner, the wiring film 3B is formed on the insulating film 4, and the resistance element 2 connected to the integrated circuit through the upper and lower wiring films 3A and 3B is formed in the through hole 4A.
When the resistance element 2 is formed in this way, the wiring film 3, the insulating film 4, and the wiring film 3 are repeatedly stacked in this order, and the resistance element 2 is provided in the through hole 4 </ b> A provided in each of the plurality of insulating films 4. Thus, as shown in FIGS. 2 to 6, a plurality of resistance elements 2 can be provided. 2 to 6, illustration of the semiconductor substrate 1 and the insulating film 4 is omitted.

In this case, the upper and lower resistance elements 2 are in contact with the same wiring film 3, that is, the wiring film 3 provided between the upper and lower resistance elements 2 is made common, and a plurality of resistance elements 2 are connected via the wiring film 3. Can be stacked.
In particular, a plurality of resistance elements 2 can be stacked in series in a direction perpendicular to the surface of the semiconductor substrate 1 via the wiring film 3 as shown in FIG. That is, a plurality of resistance elements 2 can be stacked in the vertical direction via the wiring film 3.

Further, as shown in FIG. 3, another resistive element 2B (second resistive element) is located at a position shifted in a direction parallel to the surface of the semiconductor substrate 1 with respect to the position of one resistive element 2A (first resistive element). Is provided. The one and other resistance elements 2A and 2B may be in contact with the lead wiring film 3X extending in a direction parallel to the surface of the semiconductor substrate 1. In this case, the single resistive element 2A may include a plurality of resistive elements 2A stacked in series in a direction perpendicular to the surface of the semiconductor substrate 1 with the wiring film 3 interposed therebetween. Further, as another resistive element 2B, a plurality of resistive elements 2B stacked in series in a direction perpendicular to the surface of the semiconductor substrate 1 via the wiring film 3 may be provided. Here, one resistance element is indicated by reference numeral 2A, and the other resistance element is indicated by reference numeral 2B. However, in the case where it is not necessary to distinguish these, the reference numeral 2 is used.

Further, as shown in FIG. 4, as the lead wiring film 3X extending in a direction parallel to the surface of the semiconductor substrate 1, a lead wiring film 3X extending in the front-rear direction or the left-right direction of the semiconductor substrate 1 can be provided. In other words, by providing the lead-out wiring film 3X extending in the front-rear direction or the left-right direction of the semiconductor substrate 1, another resistance element is located at a position shifted in the front-rear direction or the left-right direction of the semiconductor substrate 1 with respect to the position of one resistance element 2A. 2B can be provided.

In this case, not only may one resistive element 2A be in contact with the lower surface of the lead wiring film 3X and another resistive element 2B be in contact with the upper surface, but one resistive element 2A may be in contact with the upper surface of the leading wiring film 3X. In some cases, another resistive element 2B is in contact. In some cases, one resistive element 2A is in contact with one end of the lower surface of the lead wiring film 3X, and another resistive element 2B is in contact with the other end of the lower surface. There may be a case where the resistance element 2A is in contact and another resistance element 2B is in contact with the other end of the upper surface. That is, one resistive element 2A and another resistive element 2B provided at a position shifted in the front-rear direction or the left-right direction of the semiconductor substrate 1 with respect to the position of the one resistive element 2A are stacked in a vertical direction. Instead, it may be provided in the same layer. Here, one resistance element is indicated by reference numeral 2A, and the other resistance element is indicated by reference numeral 2B. However, in the case where it is not necessary to distinguish these, the reference numeral 2 is used. In FIG. 4, the plurality of resistance elements 2 are provided so as to be connected in a line. However, when actually manufactured, the resistance elements 2 in the same layer are formed at the same time.

As described above, the plurality of resistance elements 2 can be provided at positions shifted in the vertical direction, the horizontal direction, and the front-back direction via the wiring film 3. That is, the plurality of resistance elements 2 can be three-dimensionally arranged above the semiconductor substrate 1. In particular, the area for providing the plurality of resistance elements 2 can be reduced by devising how to shift in the vertical direction, the horizontal direction, and the front-back direction.
In addition, the plurality of resistance elements 2 can be arranged three-dimensionally via the wiring film 3 and the lead-out wiring film 3X, as shown in FIGS. 5A to 5C and FIG. 6, for example. it can.

By the way, in the present embodiment, as described above, the plurality of resistance elements 2 are electrically connected in series via the wiring film 3.
In this case, as shown in FIG. 7A, a number of resistance elements 2 corresponding to the resistance values required for use as resistance elements connected to the integrated elements provided in the semiconductor device are electrically connected in series. It ’s fine. That is, when a resistance value larger than the resistance value obtained by the one resistance element 2 described above is required, the number of resistance elements 2 corresponding to the required resistance value may be electrically connected in series. For example, when the resistance value of one resistance element 2 is R [Ω], a resistance value of 4R [Ω] can be obtained by electrically connecting the four resistance elements 2 in series.

On the other hand, as shown in FIG. 7B, when a resistance value smaller than the resistance value obtained by the one resistance element 2 described above is required, the number of resistance elements 2 corresponding to the required resistance value is electrically In parallel. That is, a plurality of resistance elements 2 may be provided in parallel by providing a plurality of through holes 4A in one insulating film 4 (not shown) and providing the resistance elements 2 in each of these through holes 4A. In this case, the same wiring film 3 is in contact with the upper and lower sides of the plurality of resistance elements 2, that is, the plurality of resistance elements 2 are provided in parallel between the upper and lower wiring films 3. 2, a resistance value smaller than the resistance value of one resistance element 2 can be obtained. For example, when the resistance value of one resistance element 2 is R [Ω], a resistance value of 0.5 R [Ω] can be obtained by providing two resistance elements 2 between the upper and lower wiring films 3. .

When high specific accuracy is not required, that is, when it is not necessary to consider variation in the resistance value of each resistance element 2 to be stacked, as shown in FIG. A corresponding number of resistance elements 2 may be stacked in series in a direction perpendicular to the surface of the semiconductor substrate 1 and electrically connected in series. For example, when the resistance value of one resistance element 2 is R [Ω], a resistance value of 4R [Ω] can be obtained by electrically connecting the four resistance elements 2 in series.

On the other hand, when high specific accuracy is required, that is, when it is necessary to consider the variation in resistance value of each resistance element 2 to be stacked, the plurality of resistance elements 2 are arranged in a direction perpendicular to the surface of the semiconductor substrate 1. The resistor units 2X may be stacked in series so as to obtain high specific accuracy among the plurality of resistor units 2X. In this case, as shown in FIGS. 8B and 8C, a number of resistance units 2X corresponding to the required resistance value are electrically connected by the lead wiring film 3X extending in a direction parallel to the surface of the semiconductor substrate 1. It may be connected in series. For example, as shown in FIG. 8B, when the resistance value of one resistance unit 2X is 4R [Ω], the resistance value of 8R [Ω] is obtained by connecting the two resistance units 2X by the lead wiring film 3X. A value can be obtained. Further, for example, as shown in FIG. 8C, a resistance value of 12R [Ω] can be obtained by connecting the three resistance units 2X by the lead wiring film 3X.

In addition, although the case where the plurality of resistance elements 2 are connected in a row is described as an example, the present invention is not limited to this, and the plurality of resistance elements 2 may be provided separately and independently. In other words, the wiring films 3 that are in contact with the upper and lower sides of each of the plurality of resistance elements 2 that are shifted in the direction perpendicular to the surface of the semiconductor substrate 1 may be provided independently. In addition, the wiring films 3 that are in contact with the upper and lower sides of each of the plurality of resistance elements 2 arranged so as to be shifted in a direction parallel to the surface of the semiconductor substrate 1 may be provided independently.

By the way, as described above, the resistance element 2 according to the present embodiment is electrically connected in series to form a resistor string, and is three-dimensionally arranged above the semiconductor substrate 1 including an integrated circuit to which the resistor string is connected. can do. Therefore, it is preferably applied to a semiconductor device including an integrated circuit having a long resistor string such as a resistor string digital-analog converter (R-DAC). Thereby, the area for providing the some resistive element 2 which comprises a resistance row | line can be made small. As a result, the chip area can be reduced, and the cost can be reduced.

Hereinafter, a semiconductor device including an R-DAC will be described as an example.
In this case, for example, as shown in FIGS. 9 and 11, the semiconductor device has a resistor string (resistor 2) configured by a plurality of resistor elements 2 electrically connected in series via the wiring film 3 as the resistor element 2. Column) 2Y. Further, the semiconductor substrate 1 includes a selector circuit 5 connected to the resistor string 2Y and a voltage follower circuit 6 connected to the selector circuit 5.

Here, the resistor string 2Y divides the reference voltage to generate different levels of output voltage.
The selector circuit 5 selects an output voltage corresponding to an input code (CODE). That is, the selector circuit 5 selects the output voltage from the resistor string 2Y according to the input code that has been input, and outputs it to the voltage follower circuit 6.

The voltage follower circuit 6 outputs the output voltage selected by the selector circuit 5 as a drive voltage for driving the load.
First, a configuration example of the R-DAC will be described with reference to FIGS.
In this one configuration example, as shown in FIG. 9, a resistor string 2Y is constituted by six resistor elements 2, and a reference voltage is divided to generate four output voltages at different levels. Any one of these output voltages is selected by the selector circuit 5 and output via the voltage follower circuit 6.

In this case, as shown in FIG. 10, on the wiring film 3 to be the first tap (Tap1), the resistance element 2, the wiring film 3, the resistance element 2, and the lead-out wiring film 3X to be the second tap (Tap2). Is provided. Further, the lead wiring film 3X serving as the second tap is extended in a direction parallel to the surface of the semiconductor substrate 1, on which the resistance element 2, the wiring film 3, the resistance element 2, and the third tap (Tap3). ) Are provided in this order. The lead wiring film 3X serving as the third tap is extended in a direction parallel to the surface of the semiconductor substrate 1, and below that, the resistance element 2, the wiring film 3, the resistance element 2, and the fourth tap (Tap4). ) Are provided in order. In actual production, the resistance element 2 in the same layer, the wiring film 3 in the same layer, and the lead-out wiring film 3X are formed at the same time. The first to fourth taps are also referred to as drawer taps.

Further, a via 7, a wiring layer 8, a via 7, a wiring layer 8, and a contact 9 are provided in this order under the lead wiring film 3 </ b> X serving as a second tap. The contact 9 is connected to the drain 5Xa of the transistor 5X constituting the selector circuit 5, that is, the drain diffusion region 5Xa of the transistor 5X formed on the semiconductor substrate 1. The source of the transistor 5X is connected to the drain of the other transistor 5Y, and the source of the other transistor 5Y constitutes the voltage follower circuit 6 through the contact 9A, the wiring layer 8A, and the contact 9B. The transistor 6X is connected to the gate 6Xa. Although not shown, similarly, the wiring film 3 serving as the first tap, the lead-out wiring film 3X serving as the third tap, and the wiring film 3 serving as the fourth tap are also connected to the drains of the transistors constituting the selector circuit 5, respectively. And is connected to the gates of the transistors constituting the voltage follower circuit 6 via two transistors.

Here, vias 7 are interposed in the wirings connecting the wiring films 3 and lead wiring films 3X serving as the taps and the transistors 5X constituting the selector circuit 5, and the vias 7 are the same as the resistance elements 2. It is formed and has the same configuration as the resistance element 2. However, this wiring is connected to the gate 6Xa of the transistor 6X constituting the voltage follower circuit 6. The gate 6Xa of the transistor 6X has a high input resistance. For this reason, the resistance value of the via 7 included in this wiring does not affect the voltage characteristics of the R-DAC.

With this configuration, four output voltages of different levels obtained by dividing the reference voltage are output from the first to fourth taps, respectively. Then, by selecting one of these output voltages by the selector circuit 5, it is possible to output the voltage via the voltage follower circuit 6.
Next, another configuration example of the R-DAC will be described with reference to FIGS.

Here, for example, a 4-bit R-DAC (VDD = 12 V) used for an LCD (Liquid Crystal Display) driver will be described as an example.
In this other configuration example, as shown in FIGS. 11 and 12, a resistor string 2Y is formed by a plurality of resistor elements 2, and a reference voltage is divided to generate 16 output voltages VL0 to VL15 of different levels. It is like that. These output voltages VL0 to VL15 are respectively output from the 16 taps of the first tap (Tap0) to the 15th tap (Tap15) of the resistor string 2Y, and one of them is selected by the selector circuit 5, and the voltage is selected. The signal is output via the follower circuit 6.

In this case, as shown in FIGS. 13 and 16, a plurality of resistance elements 2 may be electrically connected in series via the wiring film 3 and the lead wiring film 3X to form a resistance string 2Y.
Here, as shown in FIG. 12, a reference voltage (here, 6V) is applied to one terminal of the resistor string 2Y, and the other terminal is set to the ground potential (VL = 0V). As shown in FIG. 16, since one terminal of the resistor string 2Y is connected to the fifteenth tap, the output voltage VL15 output from the fifteenth tap is a reference voltage (here, 6V). Yes.

For example, in the case of an R-DAC having a linear voltage characteristic as shown by a solid line A in FIG. 15, the number of resistance elements 2 provided between the taps is made the same as shown in FIG. . As a result, the reference voltage is divided and the 16 output voltages VL0 to VL15 of different levels output from the respective taps change linearly.
On the other hand, for example, in the case of an R-DAC having a nonlinear voltage characteristic (γ curve characteristic) as shown by a solid line B in FIG. 15, the resistance element 2 provided between the taps as shown in FIG. Change the number. As a result, the reference voltage is divided and the 16 output voltages VL0 to VL15 of different levels output from the respective taps change nonlinearly.

As shown in FIG. 17, the selector circuit 5 includes 16 output voltage input terminals LV0 to LV15 to which 16 output voltages VL0 to VL15 of different levels obtained by dividing the reference voltage are input. The selector circuit 5 includes four code input terminals D0 to D3. Each of the code input terminals D0 to D3 has a bit of an input code represented by a 4-bit binary number as shown in FIG. A value is entered. Here, an input code corresponding to 0 to 15 in decimal notation, that is, any of 16 input codes is input. Then, the selector circuit 5 selects the output voltages VL0 to VL15 from any one of the first to fifteenth taps according to the input code input to the code input terminals D0 to D3, and outputs from the output terminal SOUT. It is designed to output.

Specifically, as shown in FIG. 17, the selector circuit 5 includes four transistors 5A to 5D between the output voltage input terminals LV0 to LV15 and the output terminal SOUT, respectively.
These transistors 5A to 5D are controlled to be turned on / off according to the input codes inputted from the code input terminals D0 to D3. As a result, one of the output voltages input to the output voltage input terminals LV0 to LV15 is selected and output from the output terminal SOUT.

Here, the code input terminals D0 to D3 are connected to the four transistors 5A to 5D connected between the output voltage input terminals LV0 to LV15 and the output terminal SOUT, respectively. That is, the code input terminal D0 is connected to 15 transistors 5D connected to the output voltage input terminals LV0 to LV15. The code input terminal D1 is connected to 15 transistors 5C connected to the output voltage input terminals LV0 to LV15. The code input terminal D2 is connected to 15 transistors 5B connected to the output voltage input terminals LV0 to LV15. The code input terminal D3 is connected to 15 transistors 5A connected to the output voltage input terminals LV0 to LV15.

The value of each bit of the input code input to the code input terminals D0 to D3 is logically inverted by the first inverter circuit 10 and input to the gates of some transistors. The value of each bit of the input code input to the code input terminals D0 to D3 is logically inverted by the first inverter circuit 10 and further logically inverted by the second inverter circuit 11 and input to the gates of the remaining transistors. It has become so.

As shown in FIGS. 11 and 12, the voltage follower circuit has the non-inverting input terminal connected to the output terminal SOUT of the selector circuit 5, the inverting input terminal connected to the output terminal, and the non-inverting input terminal. Is output as a drive voltage from the output terminal.
Specifically, the voltage follower circuit is configured as shown in FIG. 18, for example, so that the output voltage (IN L) selected by the selector circuit 5 is input to the gate 6Xa of the transistor 6X included therein. It has become. The gate 6Xa of the transistor 6X has a high input resistance. For this reason, the resistance component added in the path from the tap of the resistor string 2Y to the non-inverting input terminal of the voltage follower circuit 6 is virtually invisible, and does not affect the voltage characteristics of the R-DAC. Here, in the voltage follower circuit shown in FIG. 18, the negative input terminal and the output terminal of the operational amplifier are connected, and when the input voltage is applied to the positive input terminal, the same potential as the input voltage is generated at the output terminal. In addition, it has a function of driving a load connected to the output terminal with an amplified current. That is, it is used as a buffer for driving the load.

Therefore, according to the semiconductor device and the manufacturing method thereof according to the present embodiment, the area for providing the resistance element 2 when the resistance element 2 connected to the integrated circuit is provided above the semiconductor substrate 1 having the integrated circuit. There is an advantage that can be reduced. As a result, the area of the semiconductor integrated circuit can be reduced, and the cost can be reduced.
In addition, this invention is not limited to the structure described in embodiment mentioned above, A various deformation | transformation is possible in the range which does not deviate from the meaning of this invention.

For example, in the above-described embodiment, the case where the above-described via-shaped resistance element 2 is applied to a semiconductor device including an integrated circuit having a long resistor string such as an R-DAC is described as an example. It is not limited.
For example, the via-shaped resistance element 2 described above can be applied to a semiconductor device including an integrated circuit having a band gap reference (BGR) circuit as a reference voltage generation circuit. For example, the resistance elements 13 to 15 included in the band gap reference circuit 16 as shown in FIG. 19 can be configured by the via-shaped resistance element 2 of the above-described embodiment. In this case, since the specific accuracy is important for the resistance elements 13 to 15, it is preferable that each of the resistance elements 13 to 15 is configured as a resistance unit as described above for the case where high specific accuracy is required.

Here, as shown in FIG. 19, the bandgap reference circuit 16 is a circuit including one operational amplifier A1, two bipolar transistors Q1 and Q2, and three resistance elements 13-15. The connection point X between the resistance element 13 and the bipolar transistor Q1 is connected to the positive input terminal of the operational amplifier A1, and the connection point Y between the resistance element 14 and the resistance element 15 is connected to the operational amplifier A1. Is connected to the negative terminal. Further, the output terminal of the operational amplifier and the negative input terminal are connected via the resistance element 14.

The output Vout of such a band gap reference circuit 16 is given by the following equation.
Vout = VQ1 + (R2 / R3) * (k * T / q) * LN (n * R2 / R1)
Here, VQ1 is a potential difference of the bipolar transistor Q1, R1 to R3 are respective resistance values of the resistance elements 13 to 15, k is a Boltzmann constant, T is an absolute temperature, q is a unit charge, LN is a natural logarithm, and n is a bipolar transistor. It is an area ratio of Q1 and Q2. When the bipolar transistors Q1 and Q2 have completely the same characteristics, the area ratio n of the bipolar transistors Q1 and Q2 is a ratio of the number of the bipolar transistors Q1 and Q2. For example, when the number of bipolar transistors Q1 is one, the ratio is the number of bipolar transistors Q2 connected in parallel to the bipolar transistor Q1.

The second term on the right side of the above formula increases in proportion to the absolute temperature, but VQ1 in the first term has a negative temperature coefficient, so the second term on the right side and the temperature in the first term By appropriately selecting the resistance values R1 to R3 of the resistance elements 13 to 15 and the area ratio n of the bipolar transistors Q1 and Q2 so that the coefficients are canceled out, the temperature coefficient of the output voltage Vout can be made substantially zero. . Since this characteristic is determined by the physical properties of silicon, for example, it is known that the output voltage Vout is about 1.25 V when the temperature dependence is zero.

Further, the via-shaped resistance element 2 described above can be applied to a semiconductor device including an integrated circuit having an I / O buffer circuit including a pull-up resistance element or a pull-down resistance element. For example, in the output buffer circuit 18 including the pull-up resistor element 17 as shown in FIG. 20A, the pull-up resistor element 17 can be configured by the via-shaped resistor element 2 of the above-described embodiment. For example, in the output buffer circuit 20 including the pull-down resistor element 19 as shown in FIG. 20B, the pull-down resistor element 19 can be configured by the via-shaped resistor element 2 of the above-described embodiment.

Here, the output buffer circuit 18 including the pull-up resistor element 17 as shown in FIG. 20A has a function of fixing the OUT terminal to the H level when the buffer is not driven. On the other hand, the output buffer circuit 20 including the pull-down resistor element 19 as shown in FIG. 20B has a function of fixing the OUT terminal to the L level when the buffer is not driven. In this case, the pull-up resistor element 17 and the pull-down resistor element 19 need only have a certain set value, so that no particular device for maintaining the specific accuracy is required.

Also, the via-shaped resistance element 2 described above can be applied to a semiconductor device including an integrated circuit having an SRAM having a cell using a resistance element instead of the PMOS transistor constituting the CMOS inverter. For example, in an SRAM cell 25 including four NMOS transistors 21 to 24 and resistance elements 26 and 27 as shown in FIG. 21, the resistance elements 26 and 27 are configured by the via-shaped resistance element 2 of the above-described embodiment. You can also.

Here, as shown in FIG. 21, the SRAM cell 25 includes an inverter composed of a resistance element 26 and an NMOS transistor 22, and an inverter composed of a resistance element 27 and an NMOS transistor 23. These two inverters are connected to each other (cross-coupled) so that the output signal of one inverter is input as the input signal of the other inverter to form a ring-shaped latch circuit. This is where information is stored. The latch circuit is connected to a digit line (read / write line) via read / write NMOS transistors 21 and 24 that act as gates during read / write. Further, a word line 28 (access line) is connected to the gates of the NMOS transistors 21 and 24. When reading / writing, the word line 28 is set to “H” and the NMOS transistors 21 and 24 are turned on to read / write information (data).

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Resistance element 2A One resistance element (1st resistance element)
2B Other resistance elements (second resistance elements)
2X resistor unit 2Y resistor string 3 wiring film 3A wiring film (first wiring film; lower wiring film)
3B wiring film (second wiring film; upper wiring film)
3X lead wiring film 4 insulating film 4A through hole 5 selector circuit 5A to 5D transistor 5X, 5Y transistor 5Xa drain 6 voltage follower circuit 6X transistor 6Xa gate 7 via 8, 8A wiring layer 9, 9A, 9B contact 10 first inverter circuit 11 Second inverter circuit 13 to 15 Resistance element 16 Band gap reference circuit 17 Pull-up resistance element 18 Output buffer circuit 19 Pull-down resistance element 20 Output buffer circuit 21 to 24 Transistor 25 Cell 26, 27 Resistance element 28 Word line

Claims (10)

A semiconductor substrate having an integrated circuit;
A first wiring film provided above the semiconductor substrate;
An insulating film provided on the first wiring film and having a through hole;
A second wiring film provided on the insulating film;
A semiconductor device comprising: a resistance element provided in the through hole and connected to the integrated circuit through the first wiring film and the second wiring film. The semiconductor device according to claim 1, comprising a plurality of resistance elements as the resistance elements. The semiconductor device according to claim 1, comprising a plurality of resistance elements stacked via a wiring film as the resistance element. 4. The semiconductor device according to claim 1, further comprising: a plurality of resistance elements electrically connected in series via wiring films as the resistance elements. 5. The resistance element according to claim 1, further comprising a plurality of resistance elements stacked in series in a direction perpendicular to the surface of the semiconductor substrate via a wiring film as the resistance element. Semiconductor device. The resistance element includes a first resistance element and a second resistance element provided at a position shifted in a direction parallel to the surface of the semiconductor substrate with respect to the position of the first resistance element,
6. The semiconductor device according to claim 1, wherein the first resistance element and the second resistance element are in contact with a wiring film extending in a direction parallel to a surface of the semiconductor substrate. The semiconductor device according to claim 1, wherein a plurality of resistance elements are provided between the first wiring film and the second wiring film as the resistance elements. The resistance element includes a plurality of resistance elements that are electrically connected in series via a wiring film and constitute a resistance string,
8. The semiconductor device according to claim 1, wherein the semiconductor substrate includes a selector circuit connected to the resistor string, and a voltage follower circuit connected to the selector circuit. . As the wiring film, comprising a lead wiring film extending in a direction parallel to the surface of the semiconductor substrate,
9. The semiconductor device according to claim 8, wherein the lead-out wiring film is connected to a gate of a transistor of the voltage follower circuit through the selector circuit. Forming a first wiring film over a semiconductor substrate having an integrated circuit;
Forming an insulating film on the first wiring film;
Forming a through hole in the insulating film;
A semiconductor device comprising: a second wiring film formed on the insulating film; and a resistance element connected to the integrated circuit through the first wiring film and the second wiring film is formed in the through hole. Device manufacturing method.

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