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WO2012005394A1 - Carte de circuit imprimé et son procédé de fabrication - Google Patents

Carte de circuit imprimé et son procédé de fabrication Download PDF

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Publication number
WO2012005394A1
WO2012005394A1 PCT/KR2010/004460 KR2010004460W WO2012005394A1 WO 2012005394 A1 WO2012005394 A1 WO 2012005394A1 KR 2010004460 W KR2010004460 W KR 2010004460W WO 2012005394 A1 WO2012005394 A1 WO 2012005394A1
Authority
WO
WIPO (PCT)
Prior art keywords
adhesive layer
layer
electronic element
region
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2010/004460
Other languages
English (en)
Inventor
Jae Bong Choi
Min Seok Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Innotek Co Ltd
Original Assignee
LG Innotek Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Innotek Co Ltd filed Critical LG Innotek Co Ltd
Priority to PCT/KR2010/004460 priority Critical patent/WO2012005394A1/fr
Publication of WO2012005394A1 publication Critical patent/WO2012005394A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0358—Resin coated copper [RCC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H05K2203/1469—Circuit made after mounting or encapsulation of the components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Definitions

  • the disclosure relates to a printed circuit board and a method of manufacturing the same.
  • PCB printed circuit board
  • CTE coefficient of thermal expansion
  • an adhesive layer is locally formed on a region corresponding to a chip, so that the region formed with the adhesive layer may have the characteristic different from the characteristic of other regions. For this reason, severe crack or warpage may occur in the PCB.
  • the embodiment provides a PCB for minimizing crack or warpage and a method of manufacturing such a PCB.
  • the embodiment provides a PCB manufactured through a simple process and a method of manufacturing such a PCB.
  • a method of manufacturing a printed circuit board includes preparing a metal layer formed with an adhesive layer on which first and second regions are defined; attaching an electronic element to the first region of the adhesive layer; forming an insulating layer on the second region of the adhesive layer to surround the electronic element; and forming a circuit pattern by patterning the metal layer.
  • a printed circuit board includes a circuit pattern; an adhesive layer on the circuit pattern; an electronic element on a first region of the adhesive layer; and an insulating layer formed on a second region of the adhesive layer while surrounding the electronic element, wherein the second region is defined as a region besides the first region, and the adhesive layer is formed over the first and second regions.
  • the adhesive layer is formed on the second region as well as the first region where the electronic element is positioned, so that the adhesive layer can be uniformly formed in a large area.
  • the PCB may have uniform characteristics over the whole area thereof, thereby preventing the crack or warpage from occurring in the PCB.
  • the manufacturing process can be simplified as compared with a case in which the adhesive layer is locally formed on the region where the electronic element is positioned.
  • FIGS. 1 to 10 are sectional views showing a method of manufacturing a PCB according to the embodiment.
  • a layer (or film), a region, a pattern, or a structure is referred to as being on or under another substrate, another layer (or film), another region, another pad, or another pattern, it can be directly or indirectly on the other substrate, layer (or film), region, pad, or pattern, or one or more intervening layers may also be present. Further, on or under of each layer is determined based on the drawing.
  • each layer shown in the drawings can be exaggerated, omitted or schematically drawn for the purpose of convenience or clarity.
  • the size of elements does not utterly reflect an actual size.
  • a first metal layer 10 having a first adhesive layer 20 is prepared.
  • the first adhesive layer 20 is formed over first regions A where electronic elements 36 (see, FIGS. 3 to 5) are positioned and second regions B besides the first regions A.
  • the first regions A may include a region where the electronic element 36 is actually positioned and a region located around the electronic element 36 by taking the process tolerance into consideration.
  • the second regions B may include a region interposed between the electronic elements 36, a region around a via hole 61 (see, FIG. 7), and a margin region, which is inevitably formed.
  • the first adhesive layer 20 is formed on a part or a whole area of the second regions B as well as the first regions A such that the first adhesive layer 20 can be formed over 80% of the whole area of the first metal layer 10. In this case, the crack or warpage of the PCB can be minimized.
  • the first adhesive layer 20 can be formed over the whole area of one surface of the first metal layer 10.
  • the expression formed over the whole area of the first metal layer 10 may include a situation in which the first adhesive layer 20 is not formed on specific regions of the first metal layer 10, inevitably.
  • the first metal layer 10 includes at least one selected from the group consisting of copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni) and tin (Sn).
  • the first adhesive layer 20 may include semi-cured (B-stage) resin material having adhesive property, such as epoxy resin or phenol resin.
  • the thickness of the first adhesive layer 20 may vary depending on applications. If the first adhesive layer 20 is too thin, leakage current or electric short may occur. Thus, the first adhesive layer 20 must have the thickness sufficient for preventing the leakage current or electric short. For instance, the first adhesive layer 20 may have the thickness of about 10 to 25.
  • the first adhesive layer 20 can be obtained by laminating an adhesive film having a predetermined thickness onto the first metal layer 10.
  • the first adhesive layer 20 can be obtained by roll coating adhesive material onto one surface of the first metal layer 10.
  • the adhesive layer is locally formed on the region where the chip is attached through the printing scheme or the distribution scheme.
  • air bubbles may be generated when the adhesive layer is formed, so that leakage current or electric discharge may occur due to the air bubbles, causing the electric short.
  • an alignment process and/or a patterning process is necessary to form the adhesive layer on the desired region with the desired shape, so that the manufacturing process is complicated.
  • the thickness difference may occur between the region having the adhesive layer and the region having no adhesive layer, so that the adhesive layer may not be uniformly formed. For this reason, when the adhesive layer is cured, the crack or warpage may occur in the PCB due to difference in coefficient of thermal expansion (CTE). As a result, the chip may be damaged during the manufacturing process and failure of electric connection may occur. In addition, the circuit pattern, which will be formed later, may be misaligned, so that the degree of precision may be degraded.
  • CTE coefficient of thermal expansion
  • the first adhesive layer 20 is laminated or roll-coated onto the first metal layer 10, so that air bubbles generated during the manufacturing process can be minimized.
  • the first adhesive layer 20 is formed over the whole area of the first metal layer 10, the alignment process and the patterning process may be omitted. Therefore, the manufacturing process can be simplified.
  • the first adhesive layer 20 is formed over the whole area of the first metal layer 10, the crack or warpage occurring in the PCB due to the difference in CTE can be minimized.
  • the first adhesive layer 20 can be formed with the uniform thickness, so that the electronic element 36 is prevented from being damaged and the degree of precision for the circuit pattern can be improved.
  • the electronic elements 36 are attached onto the first adhesive layer 20.
  • the electronic element 36 may include at least one of a chip 30 and a passive element 35.
  • the chip 30 may include a bare chip or a wave level package (WLP) chip obtained by forming a redistribution layer of the bare chip, but the embodiment is not limited thereto.
  • the chip may include a connection terminal 31 electrically connected to other circuit pattern, chip or passive element.
  • connection terminal 31 of the chip 30 is attached to the first adhesive layer 20, but the embodiment is not limited thereto. That is, according to another embodiment, a surface of the chip 30 having no connection terminal 31 can be attached to the first adhesive layer 20. That is, the attachment surface of the chip 30 to the first adhesive layer 20 may vary depending on applications.
  • the passive element 35 may include a resistor, an inductor or a capacitor.
  • the passive element 35 can also be freely attached to the first adhesive layer 20 depending on applications.
  • the first adhesive layer 20 is under the B stage and has adhesive property, so that the electronic elements 36 can be easily attached to the first adhesive layer 20 by pressing the electronic elements 36 against the first adhesive layer 20 while applying heat or pressure to the electronic elements 36.
  • the first adhesive layer 20 is cured to securely fix the electronic elements 36.
  • the first adhesive layer 20 can be cured by applying heat or ultraviolet ray onto the first adhesive layer 20.
  • an insulating layer 40 is formed on the second regions B of the first adhesive layer 20 in such a manner that the electronic elements 36 are surrounded by the insulating layer 40.
  • the insulating layer 40 may be under the B stage.
  • a second metal layer 50 having a second adhesive layer 51 can be formed on the insulating layer 40.
  • the insulating layer 40 includes a first layer 41 having openings 41a corresponding to the electronic elements 36 and thickness corresponding to that of the electronic elements 36, and a second layer 42 covering the electronic elements 36 and the first layer 41.
  • first layer 41 and one second layer 42 are shown in FIG. 3, the embodiment is not limited thereto. According to the embodiment, a plurality of first and second layers 41 and 42 can be prepared.
  • the insulating layer 40 may include a recess having a shape corresponding to the electronic elements 36.
  • the insulating layer 40 may include an opening 40a corresponding to the electronic elements 36 and have a thickness corresponding to that of the electronic elements 36.
  • the insulating layer 40 may include resin material having adhesive property, such as epoxy resin or phenol resin.
  • the insulating layer 40 may include an ABF (Ajinomoto buildup film) or a polyimide film.
  • the insulating layer 40 may include a prepreg which can be obtained by infiltrating thermosetting resin into glass fiber.
  • the second metal layer 50 formed with the second adhesive layer 51 may be identical to the first metal layer 10 formed with the first adhesive layer 20 and aligned on the insulating layer 40 such that the top surface of the second metal layer 50 can be exposed.
  • the insulating layer 40 and the second metal layer 50 formed with the second adhesive layer 51 are placed on the first adhesive layer 20 and pressed against the first adhesive layer 20.
  • the insulating layer 40 is formed on the first adhesive layer 20 and the electronic elements 36
  • the second adhesive layer 51 is formed on the insulating layer 40
  • the second metal layer 50 is formed on the second adhesive layer 51.
  • the insulting layer 40 is formed on the electronic elements 36 based on the structure shown in FIGS. 3 and 4. Although not shown in the drawings, the electronic elements 36 may directly make contact with the first adhesive layer 51 based on the structure shown in FIG. 5.
  • the electronic elements 36 can be securely fixed by curing the insulating layer 40 after the pressing process.
  • heat and ultraviolet ray may be applied to the insulating layer 40.
  • the second metal layer 50 formed with the second adhesive layer 51 is pressed against the insulating layer 40, but the embodiment is not limited thereto. According to another embodiment, only the second metal layer 50 can be aligned on the insulating layer 40 or RCC (resin coated Cu-foil) is aligned on the insulating layer 40 to press the second metal layer 50 or the RCC against the insulating layer 40. In this case, the second metal layer or the RCC is formed on the insulating layer 40. If the RCC is formed on the insulating layer 40, a resin layer (not shown) is formed on the insulating layer 40 and a second metal layer 50 including Cu-foil is formed on the resin layer.
  • RCC resin coated Cu-foil
  • first via holes 60 are formed to partially expose the electronic elements 36. If it is necessary to electrically connect a circuit pattern 80 (see, FIG. 9), which will be formed on both surfaces of the PCB, second via holes 61 can be formed.
  • the PCB is turned over in FIG. 7 for the purpose of explanation.
  • the first and second via holes 60 and 61 can be formed through laser drilling, selective etching or chemical etching.
  • a plating process is performed with respect to the first and second via holes 60 and 61 to form first and second conductive vias 70 and 71.
  • a seed layer is formed through an electroless plating process and then an electroplating process is performed.
  • the first and second conductive vias 70 and 71 can be formed by using metal including at least one selected from the group consisting of copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni) and tin (Sn).
  • the circuit pattern 80 is formed by selectively removing the first and second metal layers 10 and 50.
  • a photoresist pattern (not shown) is formed on the first and second metal layers 10 and 50 and the metal layers 10 and 50 are selectively etched by using the photoresist pattern as a mask.
  • the method of forming the metal layers 10 and 50 is generally known in the art, so detailed description thereof will be omitted.
  • a circuit pattern unit 81 can be formed by repeatedly forming the insulating layer, the circuit pattern and the conductive via on the circuit pattern 80 according to the circuit design of the PCB. That is, the circuit pattern unit 81 may include a plurality of insulating layers, circuit patterns and conductive vias. The method for forming the circuit pattern unit 81 is generally known in the art, so detailed description thereof will be omitted.
  • the circuit pattern unit 81 shown in FIG. 10 is illustrative purpose only, and the circuit pattern unit 81 may be designed with various configurations.
  • solder mask or a solder ball can be formed on the circuit pattern unit 81 according to the circuit design of the PCB to make electric connection with other circuit pattern unit, electronic elements or substrates.
  • the first adhesive layer 20 is positioned in a first circuit pattern 10a formed by the first metal layer 10, and the electronic elements 36 are positioned on the first adhesive layer 20.
  • the first adhesive layer 20 is formed on the second regions B having no electronic elements 36 as well as the first regions A having the electronic elements 36.
  • the second regions B include a region between the electronic elements 36 (for instance, between the chip 30 and the passive element 35), and a region where the second conductive via 71 is formed.
  • the first adhesive layer 20 can be continuously formed on adjacent first and second regions A and B.
  • a portion 20b of the first adhesive layer 20 for attaching the chip 30 serving as a first electronic element may be integrally formed with a portion 20a of the first adhesive layer 20 for attaching the passive element 35 serving as a second electronic element in the second region B shown in the center of FIG. 10.
  • the adhesive layer is locally formed on the region where the chip is provided, the adhesive layer is divided to attach the electronic elements spaced apart from each other.
  • the above structure of the embodiment can be achieved because the first adhesive layer 20 is formed over the whole area (80% or more) of the first metal layer 10 when the first metal layer 10 having the first adhesive layer 20 is prepared.
  • the first adhesive layer 20 may occupy 80% or more relative to the whole area of the PCB.
  • the embodiments are applicable to the PCB and the method of manufacturing the same.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention porte sur une carte de circuit imprimé et son procédé de fabrication. Le procédé consiste à préparer une couche métallique pourvue d'une couche adhésive sur laquelle des première et seconde régions sont définies ; attacher un élément électronique à la première région de la couche adhésive ; former une couche isolante sur la seconde région de la couche adhésive afin d'entourer l'élément électronique ; et former un motif de circuit par formation des motifs de la couche métallique.
PCT/KR2010/004460 2010-07-09 2010-07-09 Carte de circuit imprimé et son procédé de fabrication Ceased WO2012005394A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/KR2010/004460 WO2012005394A1 (fr) 2010-07-09 2010-07-09 Carte de circuit imprimé et son procédé de fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/KR2010/004460 WO2012005394A1 (fr) 2010-07-09 2010-07-09 Carte de circuit imprimé et son procédé de fabrication

Publications (1)

Publication Number Publication Date
WO2012005394A1 true WO2012005394A1 (fr) 2012-01-12

Family

ID=45441357

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2010/004460 Ceased WO2012005394A1 (fr) 2010-07-09 2010-07-09 Carte de circuit imprimé et son procédé de fabrication

Country Status (1)

Country Link
WO (1) WO2012005394A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115206190A (zh) * 2022-07-11 2022-10-18 武汉华星光电半导体显示技术有限公司 显示装置
US12402258B2 (en) 2022-03-21 2025-08-26 At&S Austria Technologie & Systemtechnik Ag Direct resin embedding

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7049224B2 (en) * 2003-09-22 2006-05-23 Oki Electric Industry Co., Ltd. Manufacturing method of electronic components embedded substrate
JP2006222334A (ja) * 2005-02-14 2006-08-24 Matsushita Electric Ind Co Ltd 部品内蔵モジュールと部品内蔵配線基板とその製造方法およびそれらを用いた電子装置
US20070206366A1 (en) * 2002-01-31 2007-09-06 Tuominen Risto Method for embedding a component in a base
KR20100104932A (ko) * 2009-03-19 2010-09-29 엘지이노텍 주식회사 인쇄회로기판의 제조방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070206366A1 (en) * 2002-01-31 2007-09-06 Tuominen Risto Method for embedding a component in a base
US7049224B2 (en) * 2003-09-22 2006-05-23 Oki Electric Industry Co., Ltd. Manufacturing method of electronic components embedded substrate
JP2006222334A (ja) * 2005-02-14 2006-08-24 Matsushita Electric Ind Co Ltd 部品内蔵モジュールと部品内蔵配線基板とその製造方法およびそれらを用いた電子装置
KR20100104932A (ko) * 2009-03-19 2010-09-29 엘지이노텍 주식회사 인쇄회로기판의 제조방법

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12402258B2 (en) 2022-03-21 2025-08-26 At&S Austria Technologie & Systemtechnik Ag Direct resin embedding
CN115206190A (zh) * 2022-07-11 2022-10-18 武汉华星光电半导体显示技术有限公司 显示装置
CN115206190B (zh) * 2022-07-11 2023-11-28 武汉华星光电半导体显示技术有限公司 显示装置

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