[go: up one dir, main page]

WO2012085627A1 - Procédé de fonctionnement d'un transistor, architecture de traitement reconfigurable et utilisation d'un transistor cassé et restauré pour un fonctionnement à multiples modes - Google Patents

Procédé de fonctionnement d'un transistor, architecture de traitement reconfigurable et utilisation d'un transistor cassé et restauré pour un fonctionnement à multiples modes Download PDF

Info

Publication number
WO2012085627A1
WO2012085627A1 PCT/IB2011/001257 IB2011001257W WO2012085627A1 WO 2012085627 A1 WO2012085627 A1 WO 2012085627A1 IB 2011001257 W IB2011001257 W IB 2011001257W WO 2012085627 A1 WO2012085627 A1 WO 2012085627A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
resistive switching
current
per
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2011/001257
Other languages
English (en)
Inventor
Carmen GARCIA ALMUDEVER
Antonio RUBIO SOLA
Albert CRESPO YEPES
Javier MARTIN MARTINEZ
Montserrat Nafria Maqueda
Rosana RODRIGUEZ MARTINEZ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Universitat Autonoma de Barcelona UAB
Universitat Politecnica de Catalunya UPC
Original Assignee
Universitat Autonoma de Barcelona UAB
Universitat Politecnica de Catalunya UPC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Universitat Autonoma de Barcelona UAB, Universitat Politecnica de Catalunya UPC filed Critical Universitat Autonoma de Barcelona UAB
Publication of WO2012085627A1 publication Critical patent/WO2012085627A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/34—Material includes an oxide or a nitride
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/53—Structure wherein the resistive material being in a transistor, e.g. gate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Definitions

  • the present invention generally relates, in a first aspect, to a method for operating a transistor, and more particularly to a method allowing selectively operating a transistor as per a conventional mode, after reversibly breaking the transistor dielectric, and according to a second mode based on the creation of a closable resistive switching path through the transistor dielectric and employed for using the transistor as a non volatile memory.
  • a second aspect of the invention relates to a reconfigurable processing architecture, comprising a plurality of reconfigurable transistors, and intended to reconfigure them to make them work according to said conventional mode and/or said second mode of operation of the method of the first aspect.
  • a third aspect of the invention relates to a use of a restored broken down transistor for a multiple mode operation, including, simultaneously or selectively, using the transistor for implementing logic functions, for implementing non-volatile memory functions and/or for implementing a controlled multidirectional switch.
  • transistors are usually operated according to conventional modes by applying different electrical signals at their terminals in order to create a conductive channel between a first and a second of said terminals, through a semiconductor substrate, and make a channel current to flow there through.
  • the electrical signals applied to their terminals are current signals and/or voltage signals.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • CMOS integrated circuits [4], Fig. 3 shows the MOSFET structure.
  • the main body of the device is a Metal-Oxide-Semiconductor capacitor.
  • the MOSFET has four terminals and the current collected at the drain, that is called the drain current, is controlled by the voltage applied to the gate and drain contacts.
  • the electric field creates an inversion layer of carriers (channel) close to the interface between the semiconductor and the insulator.
  • the inversion layer provides a channel through which current can flow if a voltage is applied between drain and source. Varying the voltage between the gate and bulk the conductivity of this layer is modulated and allows controlling the channel current.
  • non-volatile memory devices should present characteristics such as high-density and low cost, fast write and read access, low energy operation and high performance with respect to endurance (write cyclability) and retention.
  • Si based Flash memory devices represent the most prominent NVM because of their high density and low fabrication costs.
  • Flash devices suffer from low endurance, low write speed and high voltages required for the write operations.
  • further scaling i.e. a continuation in increasing the density of Flash is expected to run into physical limits in the near future.
  • FeRAM ferroelectric random access memory
  • MRAM magneto resistive random access memory
  • RRAM resistive switching based resistive random access memory
  • the resistive switching (RS) phenomenon is observed in capacitor structures as Metal-Insulator- Metal (MIM) and Metal-Insulator-Semiconductor (MIS) structures [1,2,3].
  • MIM Metal-Insulator- Metal
  • MIS Metal-Insulator-Semiconductor
  • the 'M' in MIM denotes any reasonable good electron conductor, often different for the two sides, and the T stands for an insulator, typically rare earths materials with thicknesses around tens of nanometers (Fig. 1).
  • These two terminal resistive switching devices (2-t RSD) can switch between a high conductivity state 'ON state' and a low conductivity state 'OFF state', by applying adequate voltages, and controlling the flow of the current between the two terminals of the structure (gate and bulk).
  • switching has a filamentary character, which means that the current mainly flows through a small area of the insulator (from now on we call to this area the RS path, and the current through it the
  • the switching between both states can be achieved, for example, by applying ramp voltages to the device (Fig. 2), and limiting the maximum current through the device in the transition between the OFF and ON states.
  • the dielectric changes the state from ON to OFF or OFF to ON. That is, the other state is 'written' in the device. If the voltage is kept below the 'writing' voltages, the conductive state remains stable, and it is possible to 'read' it without changing to the other state.
  • US2003112055A1 discloses an anti-fuse circuit, which uses a transistor to provide two detected states, an un-programmed state where the transistor operates as a normal transistor and a programmed state which is achieved by forcing a normal transistor to conduct current through its gate, i.e. by permanently breaking its dielectric. Due to the permanent nature of said dielectric breaking, once in the programmed state, the transistor is a degraded device that cannot go back to the un-programmed state. Said dielectric breaking is provided between gate and drain, gate and source or both at a time, and, obviously, its permanent nature does not allow using said transistor as a switch but as a fuse, as no return for the created dielectric conductive paths to a non-conductive state is possible once the dielectric is broken.
  • An application for said anti-fuse circuit relates to the implementation of a function such as redundancy in a memory, providing the anti-fuse circuit, not the memory storing entities, but interconnection paths (when in the broken dielectric state) between memory storing entities which are not disclosed by US2003112055 Al .
  • US20031 12055A1 further discloses the interconnection of several of the anti-fuse circuits to provide a kind of interconnection architecture.
  • US20031 12055A1 does not disclose to use a transistor to implement logic functions, while the memory functions implemented by the proposed anti-fuse circuit are only related to the above mentioned interconnection functions, not related to storing functions.
  • US20100008132A1 discloses a resistance memory element formed by an alike MIM structure joined to a transistor.
  • Said alike MIM structure is formed by a sandwich of three layers: a first conductive layer, or word line, a resistance switching layer and a second conductive layer, or bit line.
  • Said bit line is placed onto a substrate channel region of the transistor, whether directly or through an intermediate isolating layer, depending on the embodiment, the conductive layer of said bit line acting also as the transistor electrode.
  • the RS phenomenon of said alike MIM structure is not local, as the resistive state of the intermediate resistive switching layer uniformly distributed there along.
  • US20100008132A1 further discloses to implement a memory array structure by interconnecting several of the proposed memory elements, with their drains and/or sources interconnected, thus not allowing using individual drain and/or sources of each transistor independently from other transistor drains arid/or sources.
  • US2008106926A1 relates to an integrated circuit memory cell which, for some embodiments, includes a FET transistor and a layer of a variable resistance material (VRM) directly above the FET channel or via an intermediate insulating layer.
  • VRM variable resistance material
  • the resistive phenomenon appearing in the VRM layer is not local, i.e. does not provide a local conduction path there through, but provides a uniformly distributed resistance there along, being thus the memory cell provided able to store only one bit.
  • US2008106926A1 further discloses to implement a memory circuit formed by an array of the proposed memory elements, constituting a two-terminal crossbar which only implements memory functions. No logic functions at all can be implemented by said crossbar, neither by the memory elements themselves nor by any other entity included therein.
  • [15] and [16] disclose some of said studies, particularly focused on the gate dielectric breakdown (BD) reversibility in MOSFETs with ultra-thin high-k dielectric.
  • the dielectric is reversibly electrically broken by applying a current limited voltage stress, thus creating a kind of closable conductive path, or RS path, which can be Opened' and 'closed' many times, the BD recovery partially restoring not only the current through the gate, but also the MOSFET channel related electrical characteristics.
  • BD gate dielectric breakdown
  • the present inventors don't know any proposal disclosing the operation of a transistor according to different modes, including the above referred as conventional mode and a further operation mode based on said resistive switching phenomenon, and the employment of the latter for using the transistor as a non volatile memory.
  • One of the main applications or uses of transistors is their inclusion, in a high number, in processing architectures.
  • microprocessors Today the advanced and promising computing industry, at all levels, from laptops to supercomputers, is based on the existence of complex and sophisticated monolithic integrated circuits implemented through circuits formed by billions of MOS [5] transistors.
  • the fixed architecture of the microprocessor device is oriented to execute such programs with a high level of efficiency. For a given computer the flexibility in the application domain is based on the programming capability, and because of this the programs are also called software while the physical implementations of the integrated circuits are called hardware.
  • the first electronic computers were developed in the mid-20th century (1940-45) while the invention of the integrated circuits corresponds to 1958. It is important to indicate that the adaptability, the flexibility of computers to specific applications is based on the software, while the hardware is fixed.
  • High performance microprocessors are based on specific and sophisticated architectures implemented on silicon integrated circuits [6]. Through the principles of semiconductor devices with a finely calculated and fixed size, distribution and interconnection of a complex network of MOS transistors the processor is configured at the design time. Consequently the high performance processors are based on a fixed hardware organization. As an alternative to integrated circuits with a fixed organization a new idea was developed under the name FPGA (Field Programmable Logic Arrays) devices, based on the use of fuse devices first and electrically erasable transistors. The first patents related with this new concept are dated in 1980 but most of the industry's foundational concepts and technologies for FPGAs are founded in patents awarded to David W. Page and LuVerne R. Peterson in 1985 [7].
  • FPGA Field Programmable Logic Arrays
  • the FPGAs contain a huge number of pre-defined logic blocks with a hierarchy of reconfigurable interconnects that allow the blocks to be wired among them following the indications of designers or CAD tools given as a result a specifically oriented final configuration.
  • the 1990s were an explosive period of time for FPGAs, both in sophistication and volume of production. In the early 1990s, FPGAs were primarily used in telecommunication and networking. By the end of the decade, FPGA found their way into consumer, automotive, and industrial applications.
  • RS devices Resistive Switching
  • the devices that exhibit this phenomenon could be used in huge crossbar structures. Overlaying two nanowire electrode arrays perpendicularly, a RS device is located at each crosspoint or junction. Furthermore, each crosspoint can be independently configured in a nonvolatile low or high impedance state by applying appropriate voltages in the respective bar extremes. The device can be configured easily and can be read through any mechanism of resistance evaluation. So, it is a promising device for future memories.
  • FPGA types are based on a pre-defined and fixed organization of processing entities that collaborate in the computing tasks. These entities are physically distributed through the entire surface of the integrated circuit in a fixed manner. Hence, each one of the entities that form the integrated circuit is characterized by a specific and fixed characteristic (e.g. the number of stored words in a memory, the number of core units, the number of I/O sections ... ) .
  • the present invention provides, in a first aspect, a method for operating a transistor, comprising:
  • the method of the invention further comprises, in a characteristic manner:
  • the method comprises selecting using said transistor according to one of said first and second modes, or according to both of said first and second modes.
  • said resistive switching path is a first resistive switching path
  • said second mode of operation further comprises applying at least a third set of electrical signals at at least part of the terminals of said transistor in order to create at least a second resistive switching path and make current to flow locally through said dielectric between said third terminal and another of said terminals not involved in said first resistive switching path.
  • the second mode of operation of the method comprises applying further sets of electrical signals at at least part of the terminals of the transistor in order to create further corresponding resistive switching paths and make current to flow locally through the dielectric between the third terminal and another of the terminals not involved in said first and second resistive switching paths.
  • the method of the first aspect of the invention comprises, for an embodiment, employing said second mode of operation for using said transistor as a non volatile multibit memory, where each of said resistive switching paths represents a memory bit having a value with a certain logic state or with a logic state complementary to said certain logic state, depending on at least the value of the current circulating there through.
  • the method of the first aspect of the invention comprises, as per an embodiment, controlling said sets of electrical signals in order to control the opening/closing of the resistive switching paths, their location and the values and directions of said current flows.
  • the method comprises, for an embodiment, carrying out said control such that said channel current flow is substantially null and reading each memory bit value by measuring the respective resistive switching path current value at a terminal of the transistor where said current flows.
  • the method comprises carrying out said control such that the channel current flow is not null and reading each memory bit value by measuring the combined current resulting from the combination (such as the subtraction or addition) of the respective resistive switching path current and the channel current, at a terminal of the transistor where said current combination is produced.
  • the method comprises at least the next two manners of performing it:
  • the method of the first aspect of the invention comprises employing said second mode of operation for using the transistor, instead or complementarily to as a non volatile memory, as a controlled multidirectional switch between the third terminal and two or more of the other transistor terminals, where:
  • the method comprising selectively controlling the switching ON/OFF and location of said single connection, or
  • the method comprising controlling the simultaneous switching ON/OFF of said first and second connections.
  • the method of the first aspect of the invention comprises, for an embodiment, selecting employing said second mode of operation for using the transistor as said non volatile memory and/or as said multidirectional switch.
  • the transistor is a Field Effect Transistor (FET) such as a
  • MOSFET with a single gate, a multigate transistor (such as a FINFET) or a CNTFET, with a material with resistive switching properties.
  • the transistor operated according to the method of the first aspect of the invention is a MOSFET with a dielectric with resistive switching properties, said first, second and third terminals corresponding, respectively, to the source, drain and gate of said MOSFET, the above referred as electrical signals being voltage signals, and each of said one or more resistive switching paths passing only:
  • the transistor used according to the method of the first aspect of the invention is, for an embodiment, a standard MOSFET with ultra-thin high-k material as gate dielectric. No especial characteristics of the transistor (gate electrode, oxide thickness, dimensions...) are required to observe the RS phenomenon in them. Therefore, the device can be fabricated using state of the art high-performance logic CMOS technology.
  • a different manner of referring to said new operation modes is that of calling the I bit non volatile memory as second operation mode, the multibit non volatile memory as third operation mode and the controlled multidirectional switch as fourth mode, the method comprising to use the transistor to make it operate according to part or all of said operation modes, individually or at a time.
  • a second aspect of the invention concerns to a reconfigurable processing architecture, comprising: - a plurality of transistors for implementing required logic functions,
  • control unit for controlling said transistors and resistive switching elements.
  • said transistors are intended for implementing both, said required logic functions and said memory functions, said resistive switching elements being provided by said transistors, as the latter have respective reversibly electrically breakable dielectrics each providing, after being reversibly broken in a controlled manner, at least one closable resistive switching path to appear there through while at least partially restoring the channel electric properties of the respective transistor, at least when said at least one resistive switching path is closed, and said control unit is intended for, once said dielectric reversible breaking has been caused, selecting and controlling at least part of said transistors for making each of them work according to first and second modes of operation, at least one mode at a time, by means of:
  • said control unit being intended for employing said second mode of operation for using each selected transistor as a non volatile memory, where said at least one resistive switching path represents a memory bit having a value with a certain logic state or with a logic state complementary to said certain logic state, depending on at least the value of the current circulating there through.
  • said transistor dielectrics are already reversibly broken (each providing at least one of said closable resistive paths) when the architecture is built, or they are broken in an initial phase of use of the architecture or when required, individually, by groups or all of them at the same time.
  • said control unit is also intended for employing said second mode of operation for using each selected transistor as a controlled multidirectional switch between said third terminal and at least two of the other transistor terminals, by connections provided by respective closable resistive switching paths, the control unit being in charge of selecting if employing said second mode for using each selected transistor as a non volatile memory or as a controlled multidirectional switch.
  • the control unit of the reconfigurable processing architecture implements the method of the first aspect to control and supply said sets of electrical signals to make each selected transistor work in said first and/or second modes of operation.
  • control unit is intended for controlling said sets of electrical signals, to select transistors and dynamically modify the mode of operation they work between said first and second modes, as a function of instantaneous computing requirements and/or in order to correct possible malfunctioning of some parts of the processing architecture, the control unit being arranged for sensing the processing architecture performance in order to carry out said dynamic modification.
  • control unit is intended for controlling the sets of electrical signals to select transistors and dynamically making them stop working, as a function of instantaneous computing requirements and/or in order to correct possible malfunctioning of some parts of the processing architecture, the control unit being arranged for sensing the processing architecture performance in order to carry out said working stop.
  • the reconfigurable processing architecture comprises, for an embodiment, a library registering several possible logic and memory entities to be mounted, and the control unit has access to said library and is intended:
  • Said logic entities include, for an embodiment, entities implementing negate Boolean functions.
  • a new architecture principle self-adaptive to the data requirements is presented, representing a new computing and organizational architecture paradigm or new operative computer organization oriented to execute computing tasks in a dynamic, flexible, efficient and adaptive way taking into account the processing needs that are being executed in each moment.
  • the space distribution of the processing entities is not fixed but oriented to satisfy the instantaneous needs of computation, being modified dynamically and managed by a control unit through the selective supply of the transistors forming the architecture.
  • a third aspect of the invention concerns to a use of a restored broken down transistor for a multiple mode operation, where said restoration relates to the at least partially restoring of the transistor channel electric properties after reversibly electrically breaking the dielectric of said transistor in a controlled manner for creating a closable resistive switching path to appear there through, said multiple mode operation including, simultaneously or selectively:
  • Said multiple mode operation further includes, for an embodiment of the use of the third aspect of the invention, selectively or simultaneously with said logic functions use and non-volatile memory functions use, using the transistor for implementing a controlled multidirectional switch also based on the conduction state of said resistive switching path created in the transistor dielectric.
  • Fig. 1 shows a MIM or MIS structure with the RS effect, for an ON state, left view, where the current flowing through the RS path is high, and for an OFF state, right view, where the RS current is low;
  • Fig. 2 is a graph showing ramp voltages applied to change the state of the device of Fig. 1 , where the transition between the ON-OFF or OFF-ON states can be detected, respectively, as a high decrease or increase of the gate current;
  • Fig. 3 shows a MOSFET structure, which four terminals allow controlling the current that flows from source to drain, i.e. the channel current;
  • Fig. 4 shows, by means of a graph, the typical channel currents measured in a MOSFET as a function of the drain-source voltage for three different gate voltages;
  • Fig. 5 shows a MOSFET used according to the method of the first aspect of the invention, for an embodiment, in which the RS effect can be observed, so that two currents due to two different mechanisms are present in the transistor, the current due to the RS effect (RS current) and the channel current, both of said currents being controlled by the method of the invention by applying the adequate voltages to the MOSFET terminals;
  • Fig. 6 shows a MOSFET used according to the method of the first aspect of the invention, for another embodiment, where the transistor is used as a 1 bit memory element, and according to a first reading method, a null channel current is forced, and the memory state is read from the RS current;
  • Fig. 7 shows the reading window obtained using the first reading method of Fig. 6, said reading window being similar to the one corresponding to the MIM structure represented in Fig. 1 ;
  • Fig. 8 shows also a MOSFET used according to the method of the first aspect of the invention, for another embodiment, where the transistor is used as a 1 bit memory element, like in Fig. 6, but for a second reading method where a low channel current is forced, lower than the RS current at the OFF state, and the read operation is done in the drain terminal, where the difference of both currents difference is measured;
  • Fig. 9 shows the reading window obtained using the first and the second reading methods of Figs. 6 and 8 respectively, where it can be observed that in the second reading method, the forced channel current reduces the current measured at the OFF state respect the first reading method, whereas it has negligible effects in the ON state; therefore, an enlargement of the reading window is obtained;
  • Fig. 10 shows the reading window obtained using a third reading method, for which a channel current higher than the RS current at the OFF state but lower than the RS current at the ON state is forced, which makes that the memory state is distinguished by the sign of the current at the drain terminal.
  • the current is dominated by the channel current, that has lower dispersion;
  • Fig. 11 shows a MOSFET used according to the method of the first aspect of the invention, for an embodiment, in which the device is used as a multibit non-volatile memory by creating several RS paths through the dielectric thereof;
  • Fig. 12 is a graph which shows the channel current measured in a transistor in which, according to the method of the first aspect of the invention, two RS paths have been created, one close to the drain and another one close to the source.
  • Four different drain current levels are possible (II , 12, 13, 14) demonstrating its operation as a 2-bit memory cell;
  • Fig. 13 shows a MOSFET used according to the method of the first aspect of the invention, for an embodiment, in which several RS paths are created in the transistor (see left view), the current flowing between gate and the terminals where the paths are created, for an operating mode where controlling the state of the RS paths, the transistor is equivalent to a multidirectional/multiplexor switch between gate and the other terminals thereof, as shown schematically in the right view;
  • Fig. 14 is a graph which shows the electrical characteristics of a MOSFET used according to the method of the first aspect of the invention, but keeping the RS current at the OFF state, where similar curves than standard MOSFETs used according to conventional methods are obtained, which, therefore, if kept at the OFF state, makes the MOSFET able to be used as a standard transistor;
  • Fig. 15 shows schematically an electronic device including a MOSFET with a gate dielectric of a material with RS properties, and a control unit connected to its terminals to make it operate according to the method of the first aspect of the invention
  • Fig. 16 schematically shows the structure of the reconfigurable processing architecture of the second aspect of the invention, for an embodiment
  • Fig. 17 shows an example of adaptive computing for the mounting phases of a LIFO memory, implemented with the reconfigurable processing architecture of the second aspect of the invention, for an embodiment
  • Fig. 18 shows an example of adaptive computing for the dismount phases of a LIFO memory, implemented with the reconfigurable processing architecture of the second aspect of the invention, for an embodiment
  • Fig. 19 shows, by means of four views, an example of sequential mounting and dismounting phases adapting the capability of the circuit to the data requirements, by means of the reconfigurable processing architecture of the second aspect of the invention, for an embodiment.
  • the Figure shows how the architecture is not fixed as happen in conventional computers but adapts the size and composition dynamically.
  • Fig. 20 shows the electrical model of a RS path, at view A, and of a memFet, at view B;
  • Fig. 21 shows at view A a conventional crossbar architecture based purely on 2t-RSDs for memory applications, and at view B a crossbar implementing the reconfigurable architecture of the second aspect of the invention for an embodiment;
  • Fig. 22 shows several designs obtained by a crossbar implementing the reconfigurable architecture of the second aspect of the invention for several embodiments that exemplify how a crossbar based in memFETs works;
  • Fig. 23A schematically shows an EHW based on a FPGA, logic and memory entities change from one stage (left view) to other (right view);
  • Fig. 23B shows the Shapeshifting Evolvable Hardware concept based on a memFET crossbar architecture as per the second aspect of the invention, where different entities (logic gates in this case) are stored in a library, and the HOS is the responsible to mount, dismount or change the position of any block on the computing board in accordance with task requirements; and
  • Fig.24 shows different examples of application of the SEHW concept, particularly at view A an application of SEHW concept in a LIFO memory is shown, where the elemental blocks of both, the binary counter (1 bit counting unit) and the memory unit (register) are stored in the library, which are mounted or dismounted depending on the input output data; and at view B an application of SEHW concept in a multi- core system, is shown for which a core and a memory unit are stored in the library.
  • Figs. 1 to 14 The method for operating a MOSFET according to multiple operation modes of the first aspect of the invention is represented, for different embodiments, in Figs. 1 to 14, and an electronic device implementing said method by means of a control unit connected to the terminals of the MOSFET is illustrated in Fig. 15.
  • the transistor used is a MOSFET in which the gate dielectric is a material with RS properties.
  • the RS effect can be observed in standard high-k dielectrics in MOSFETs after their dielectric breakdown (BD) [2]. Therefore, the RS path, which is equivalent to the BD path, is opened electrically controlling the BD event in these layers.
  • BD dielectric breakdown
  • Fig. 5 illustrates the MOSFET transistor after the resistive switching path has been created. This device will be called hereafter memFET. Two different currents can be distinguished: ⁇
  • the channel and RS currents can be controlled by applying adequate voltages at the device terminals (gate, source, drain and bulk), as per the method of the first aspect of the invention.
  • the next operation modes can be obtained depending on the voltages applied to the terminals of the MOSFET according to the method of the invention.
  • the memFET can be used for memory applications, to store 1 bit, as in MIS/MIM capacitors.
  • the presence of four terminals allows taking advantage of the channel current, which can be used to enlarge and improve the possibilities of reading, as it is explained later.
  • the information is written in the memFET as in conventional MIM/MIS capacitors (see Prior State of the Art section).
  • the gate dielectric can be switched between the ON and OFF states applying voltages to the gate, with source, drain and bulk grounded. With this voltage configuration, the RS path is created in a random location of the dielectric of the memFET. For simplicity, in this first application, a unique RS path is considered located between drain and gate, as shown in Fig. 6, to explain the reading process of the memFET. Reading the memFET:
  • Reading method 1 As a MIM/MIS capacitor (null channel current).
  • the current through the gate will be low or high depending on the RS dielectric state, OFF or ON, respectively.
  • Fig. 7 shows the read current after ten successive switching cycles (writing + erasing) between the
  • the reading window between both states is around 2-3 orders of magnitude, which are typical values in conventional MIM structures based in the RS effect.
  • Reading method 2 Forcing a low channel current.
  • a small voltage difference between drain and source and a voltage at the gate are applied.
  • the RS current and the channel current are flowing during the reading process, as shown in Fig. 8.
  • a channel current lower than the RS current during the ON state and comparable to the RS current during the OFF state is forced.
  • the memory-MOSFET state is read from the current at the drain terminal, where the difference between the two currents is measured. Note that the use of the drain current for reading is a different methodology as the used in conventional MIM structures, where the reading process is performed at the gate terminal.
  • Fig. 9 shows the drain current at the ON and OFF states when the second reading method is applied (crosses).
  • the current measured using reading method 1 is also plotted (circles).
  • the second method when at the ON state, the RS current is much higher than the channel current, so that no difference in the ON current measured is observed with respect to the one obtained in the previous method.
  • the channel current is lower but comparable to the RS current. Therefore a lower OFF current is measured when the second method is used for reading. Therefore, if the second method is used for reading, the reading window between the ON and OFF states increases, improving the memory performance.
  • Reading method 3 Forcing a high channel current.
  • the last method to read this memory-MOSFET consists in forcing a channel current higher than the RS current in the OFF state but lower than the RS current in the ON state. Under these conditions, the current in the drain terminal has opposite direction (changes its sign) when the device is in the ON or OFF state.
  • Fig 10 shows the drain current measured using this third reading method.
  • the current is around 300uA (same order of magnitude than the one measured using the two previous methods); however at the OFF state the measured channel current is -600nA. Therefore, both states are distinguished by the current sign.
  • a new technique for the reading process is allowed since typically the memories based on the RS effect discriminate the state from the difference in magnitude of the currents, and not from their sign.
  • the RS current at the OFF state has a high dispersion (200%-300%). With this new method the current at the OFF state is mainly due to the channel current, that has a low standard deviation (25%).
  • MOSFET transistors allows implementing a multi-bit non volatile memory cell.
  • the advantage of reading through a high channel current, (change in the current sign and lower dispersion) can be obtained at different RS paths along the channel: between gate and source, gate and bulk or gate and drain (see Fig. 11).
  • the appearance of the RS path in these different locations can be controlled applying the correct voltages to the transistor terminals, as per the method of the first aspect, and can be used to implement a multi-bit memory cell. This increases widely the possibilities of the memFET in front the MIM/MIS capacitors, where the RS path is created randomly and a determined location can not be selected.
  • Fig. 12 shows the channel current measured in a multi bit non- volatile memFET in which two RS paths have been created, one close to the drain and another one close to the source.
  • Four different drain current levels are possible (II, 12, 13, 14) and therefore, two bits can be stored in this device.
  • RS paths in a MOSFET transistor is used, for an embodiment of the method of the invention, to implement a multidirectional switch between gate and source, gate and bulk or gate and drain.
  • the current flows through the gate and the terminals which have the RS path at the ON state, as Fig. 13 shows, providing several (in this case three) possible connections, to be established at a time, individually or in any possible combination of two connections.
  • memFETs increases the possibilities respect the MIM/MIS capacitors where only one switch can be obtained.
  • the memFET used shows the behaviour of a typical MOSFET. Hence, if the RS paths remain at the OFF state it can be used as a standard MOSFET with the same applications.
  • Fig. 14 shows the I -V characteristics of the transistor of
  • the method of the first aspect of the invention has many applications, including those which require circuitry including elements operating as transistors, memory elements and/or multi-switches, and particularly for those which require the same elements to carry out, under control, at least two of the above mentioned operation modes, individually or at a time, which provides a new type of reconfigurable circuitry unknown up to now, which can transform in part the functions provided by an electronic circuit, or even transform completely the main functions of such a circuit just by applying different sets of voltages to the transistors it includes, as it could be for example the case of a memory board transformable into a switch board, or vice versa.
  • the reconfigurable processing architecture of the second aspect of the invention takes advantage of the use of transistors controlled as per the method of the first aspect, being therefore an application of particular interest.
  • said architecture is a highly-scaled system, where the MOSFET transistors in which the RS effect takes place are used, according to the method of the first aspect, in adaptive computing architectures that use the crossbar logic concepts.
  • a memFET is located in each crosspoint and can be dynamically and electrically configured as memory cell, multidirectional switch or transistor, as per the method of the first aspect of the invention.
  • Another advantage of using memFETs transistors instead of MIM/MIS capacitors in the crossbars is that the correct combination of nMOS and pMOS memFETs in the array allows obtaining the negative logic with CMOS technology completely integrated in the architecture.
  • the integration of the memFETs in the crossbar makes possible to implement the logic inversion. Therefore, complex systems can be built by replicating the same kind of device and electrically configuring it as needed, which simplifies their fabrication process.
  • the RS path can be electrically modelled as a voltage controlled switch, with a control voltage equal to the voltage that drops at the RS-path, in the form of a RS path model as shown at Fig. 20A.
  • the ON and OFF switch resistances and threshold voltages can be easily obtained from IGS-VGS characteristics.
  • a MOSFET transistor in which a RS path has been created can be electrically modelled by connecting the RS path model between the gate and the terminal/s where the RS path/s is/are located, as shown in Fig. 20B for a p-type MOSFET.
  • This memFET model can accurately reproduce the memFET electrical characteristics at the OFF and ON states when introduced in a circuit simulator.
  • Figs. 21 and 22 the memFET model of Fig. 20B is used to represent the memFETs included in the crossbars there illustrated.
  • Fig. 21 A shows a conventional crossbar architecture based purely on 2t-RSDs for memory applications
  • Fig. 2 IB shows a crossbar implementing the reconfigurable architecture of the second aspect of the invention, including memFETs, which, as previously shown, offers additional operation modes compared to 2t-RSDs, and can thus be used to optimize the circuit design, including not only increasing its storage capacities, as multi-bi cells, but also due to their increased functionalities opening the possibility of extending the concept of RSDs based crossbar to more advanced architectures, since the inclusion of memFETs in a crossbar also adds computation and multi-switch capabilities to the structure.
  • the memFETs are interconnected by voltage controlled switches, which will be opened or closed to define the operations performed by the structure. These switches can be fabricated with the same technology as that of the memFETs and would be activated or deactivated using an auxiliary crossbar (zoom in Fig. 2 IB).
  • Each memFET can be used as a standard MOSFET transistor, when all the RS paths are in the OFF state, so that logic circuits can be implemented in the crossbar.
  • the same device can be used as a n-bit memory cell or n-directional switch, if one or more RS paths are created.
  • a block of eight memFETs (four P type and four N type, with RS paths located at drain and source) arranged in a bi-dimensional crossbar structure (shaded in grey in Fig. 2 IB), allows to configure the basic logic operations (NAND, NOR and NOT).
  • the connection of different blocks increases the capability of logic computation and information storage.
  • Fig. 22 shows several designs that exemplify how a crossbar based in memFETs works.
  • the switches in the block are configured to build a NOR gate.
  • the interconnected memFETS are used as MOSFETs (i.e., all the RS paths are OFF), whereas those memFETs that are not involved in the logic operation (enclosed in grey rectangles) can be used as memory cells.
  • Fig. 22B shows two blocks of eight memFETs designed to implement a AND operation. This is done by configuring the first and the second eight-memFETs blocks as NAND and NOT gates, respectively, and using the multidirectional switch function of one of the memFETs (enclosed in a grey oval) in which one RS path is at the ON state to connect the NAND output to the NOT input. In this case, 9 memFETs (enclosed in grey rectangles) can be used as memory cells.
  • the crossbar of Fig. 22 is a crossbar supplying the above mentioned sets of electrical signals at the source, drain gate and bulk of the selected memFETs from the crossbar terminals, in this case through the voltage controlled switches, although for another embodiment said supplying is performed by different means.
  • the crossbar has a number of terminals different from four.
  • the multiple operation modes of the memFETs also add reconfiguration properties to the crossbar.
  • the operation of a 8-memFET block (as that shaded in grey in Fig. 2 IB) has been simulated, whose configuration is sequentially changed to work as different logic gates.
  • an electrical model presented in Fig. 20B has been introduced in a circuit simulator.
  • Fig. 22C shows the transient simulation of the block output.
  • the configuration of the block has been sequentially modified at 2ms, 6ms, 12ms and 16ms to build a NOT, NAND, NOR logic gates and a connection stage, respectively. Additionally, the block can store information.
  • a short time interval (marked with grey rectangles) is reserved to change the operation mode of the block (by opening/closing the adequate switches and selecting the memFETs operation modes) and for the writing or reading process of the memFETs acting as memory cells.
  • the number of available bits that each 8- memFET block is store at any moment of the simulation is also indicated in Fig. 22C, and has been determined by multiplying the number of memFETs that are not involved in the logic gate by the number of bits that each memFET can store (n).
  • FIG. 16 shows the basis of the structure of the reconfigurable processing architecture of the second aspect of the invention, for an embodiment assuming a large planar bi-dimensional crossbar structure, indicated as architecture board AB, where in each cross point there is a hybrid RS/CMOS device (MOSFET with dielectric providing the RS phenomenon), which are non-volatile devices programmable through voltage excitation actions caused by an internal section, implemented in the circuit that is called HOS (Hardware Operating System), and which was called in a previous section as control unit.
  • RS/CMOS device MOSFET with dielectric providing the RS phenomenon
  • the HOS is able to replicate or mount any specific logic entity from a set called LIBRARY (see Fig. 16) to any point of the architecture board (AB) thanks to the flexibility of the hybrid RS/CMOS device, indicated as basic device in Fig. 16, with no more limit that the dimension of the global circuit.
  • the HOS configures the computing architecture in the AB through the dynamic "mounting" of entities, depending on the computing requirements.
  • the HOS is able also to dismount or erase blocks in the dynamic reconfiguration sequences, adapting the computing architecture to the instantaneous data requirement.
  • the ability of mounting or dismounting entities is based on the RS/CMOS electrical reconfiguration principles.
  • the HOS adapts the architecture to the computational requirements.
  • One of the complementary advantages of the reconfigurable processing architecture of the second aspect of the invention is based on the capability to reconfigure the circuit in the AB in case of manufacturing defects in certain cross point.
  • the new paradigm provided by the invention extends the flexibility of the software to the architecture level, allowing a higher efficiency of the circuit in case of different computing tasks or loads.
  • Figs. 17 and 18 show an example of application, or embodiment, of the architecture of the second aspect of the invention, consisting of a simple LIFO (Last Input, First Output memory) represented by a register unit and a counter unit.
  • LIFO Last Input, First Output memory
  • Fig. 17 shows the system at starting time where no information is registered and a cero is indicated in the counter module, and for different needs of storage, 1, 2, 3, 4 data, indicated in binary by the counter module, respectively, as 01, 10, 11 and 100. Observe that the architecture adapts both the width of the counter and the memory map to the storage requirements.
  • the architecture is also able to erase or dismount entities when no required, as is shown in Fig. 18 for 4, 3, 2, 1, 0 data, i.e. 100, 1 1, 10, 01, 00 being indicated in the binary counter unit.
  • FIG. 19 Another example of application of the architecture of the second aspect of the invention, is shown in Fig. 19, where different blocks are illustrated representing different elements forming an architecture, such as the one of a microprocessor, corresponding to, for example, memory blocks, processing cores, arithmetic units and I/O banks.
  • the architecture is evolving, i.e. being reconfigured, by selectively adding or removing some of said elements, depending on the requirements, what is done, as described previously, by changing the functions of the hybrid RS/CMOS devices forming the architecture, i.e. by means of the HOS circuit replicating and erasing blocks of the LIBRARY on the Architecture Board through a sequence of signals and voltages to the hybrid RS/CMOS devices.
  • the reconfigurable memFETs based architecture opens new possibilities for the design of future large computation systems, where the function of all the elements could be adapted to the instantaneous needs.
  • the strongly repetitive structure of this architecture suggests a reduction in the complexity of the fabrication process, when compared to the actual approaches.
  • SEHW Shapeshifting Evolvable Hardware
  • EHW concept appeared early 90's and it refers to hardware that can change its own hardware structure and behaviour dynamically and autonomously adapting itself to changes in task requirements or in its environment.
  • EHW Error Correction Code
  • FPGA Field Programmable Gate Array
  • GA Genetic Algorithm
  • FIG. 23 A An illustrative example of EHW concept is shown in Fig. 23 A.
  • the chip is composed of a finite number of pre-defined entities (logic blocks and memory, I O blocks and programmable interconnections) that are stationary distributed over the entire surface of the chip, and that can be reconfigured from configuration bits and evolve (find out better hardware structure) thanks to the use of genetic algorithms. Observe how the logic and memory (flat rectangles, in dark grey means not used, in light grey means used) change from one stage to other.
  • SEHW operative computer organization oriented to execute computing tasks in a dynamic, flexible, efficient and adaptive way taking into account the processing requirements/needs that are being executed at each time.
  • the SEHW mechanism implementing an embodiment of the second aspect of the invention is able to transform the functionality and change the location of the hardware structure dynamically and autonomously, self-adapting resources to computation requirements.
  • the hardware develops its own hardware structure depending on task requirements.
  • SEHW is built on a large bi-dimensional memFET crossbar (Fig. 23B, left); it is called Computing Board (CB).
  • CB Computing Board
  • the Library is defined, where a set of specific elementary processing elements is stored (Fig. 23B, left).
  • the CB is surrounded by a programmable interconnection ring that links up the CB with the above mentioned controller element called Hardware Operative System (HOS).
  • HOS Hardware Operative System
  • the HOS is responsible for identifying the computing requirements and satisfy them. For that, the HOS is able to replicate any specific logic entity from the Library in the CB (mount) as well as erase (dismount) or modify the position of any logic entity within the CB (relocate). This is achieved applying a set of electrical signals through the ring connections that allows reconfiguring each non-volatile memFET device (crosspoint) of the CB. So, the HOS detects the processing requirements and satisfy them by copying, deleting or changing the position of the different logic blocks towards a new structure.
  • the interconnection ring allows the communication between the CB and the HOS for both configure the computing structure and sense the need of hardware evolution.
  • the SEHW concept is shown in Fig. 23B. Observe that the space distribution of the processing entities is not fixed as in FPGAs but can be positioned in any free space of the CB. So SEHW, not having a predefined or predetermined structure, makes better use of available chip area and therefore higher performance. In addition, thanks to the mounting, dismounting and relocation of the blocks, SEHW could be a defect-tolerant and even fault- tolerant system.
  • FIG. 24 A simple illustrative example of SEHW application in a LIFO (Last In, First Out) memory is shown in Fig. 24A. Note that both, the counter (light grey blocks) and the memory unit (dark grey blocks) expand or shrink dynamically depending on the input/output data. First two data are stored, and then a third one is stacked. A new register is "mounted" to the memory unit whereas the binary counter works keeping its size (2 counting units). Next, a fourth data enters, an in this case a counting unit is added to the counter. Finally, the last data is removed so the last register and counting unit are "dismounted".
  • LIFO Last In, First Out
  • SEHW single component with a high number (tens or hundreds) of independent cores that have been attached for enhanced performance, reduced power consumption, and more efficient simultaneous processing of multiple tasks (parallel processing).
  • OS operative system
  • SMT simultaneous multithreading technology
  • Fig. 24B shows an application of SEHW technique in a many-core structure.
  • a core and a basic memory block form the library.
  • the HOS starts with a basic computing architecture formed by a single core and a certain amount of memory. Evolving towards the computing needs, the system modifies the number of cores and the amount of memory assigned to each core.
  • the system first evolves from a single-core structure to a three-core architecture in which each core has a specific amount of memory to finally become a dual-core system.
  • the reconfigurable processing architecture of the second aspect of the invention a new computer organizational concept that autonomously configures the type, size and position of the elementary bock elements is provided.
  • the configuration is highly dynamic adapting the architecture to the instantaneous data requirements.
  • the block elements that form part of the architecture are replicated or erased in the architecture depending of the data requirements.
  • the architecture is not fixed as happen in conventional computers but adapts the size and composition dynamically.
  • the reconfigurable memFETs based architecture is a step toward the design of future large computation systems.
  • the versatility and easy reconfiguration of memFETs crossbar architecture leads to the Shapeshifting Evolvable Hardware principle, a technique that can change the location of the hardware structure dynamically and autonomously self-adapting resources to computation requirements.
  • Patent 3,102,230 filed in 1960, issued in 1963).
  • CMOL FPGA a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Logic Circuits (AREA)

Abstract

Le procédé comprend la mise en fonctionnement d'un transistor selon un mode classique, après une cassure de manière réversible du diélectrique du transistor, et selon un second mode sur la base de la création d'un trajet de commutation résistif apte à être fermé à travers le diélectrique de transistor et employé pour utiliser le transistor en tant qu'élément de mémoire non volatile et/ou en tant qu'élément multi-commutation. L'architecture de traitement reconfigurable comprend une pluralité de transistors reconfigurables et une unité de commande destinée à les reconfigurer pour les faire fonctionner selon ledit mode classique et/ou ledit second mode de fonctionnement. La structure est flexible et n'est pas fixe comme cela arrive dans des calculateurs classiques mais s'adapte à la dimension et à la composition de manière dynamique. L'utilisation comprend, simultanément de manière sélective, l'utilisation du transistor pour mettre des fonctions logiques, des fonctions de mémoire non volatile et/ou pour mettre en œuvre un commutateur multidirectionnel commandé.
PCT/IB2011/001257 2010-12-23 2011-06-07 Procédé de fonctionnement d'un transistor, architecture de traitement reconfigurable et utilisation d'un transistor cassé et restauré pour un fonctionnement à multiples modes Ceased WO2012085627A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EPE10016028.2 2010-12-23
EP10016028 2010-12-23

Publications (1)

Publication Number Publication Date
WO2012085627A1 true WO2012085627A1 (fr) 2012-06-28

Family

ID=43608088

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2011/001257 Ceased WO2012085627A1 (fr) 2010-12-23 2011-06-07 Procédé de fonctionnement d'un transistor, architecture de traitement reconfigurable et utilisation d'un transistor cassé et restauré pour un fonctionnement à multiples modes

Country Status (1)

Country Link
WO (1) WO2012085627A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10396175B2 (en) 2014-11-25 2019-08-27 University Of Kentucky Research Foundation Nanogaps on atomically thin materials as non-volatile read/writable memory devices
US10886333B2 (en) 2019-03-01 2021-01-05 International Business Machines Corporation Memory structure including gate controlled three-terminal metal oxide components
TWI734452B (zh) * 2020-04-23 2021-07-21 友達光電股份有限公司 記憶體裝置以及寫入方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3102230A (en) 1960-03-08 1963-08-27 Bell Telephone Labor Inc Electric field controlled semiconductor device
US4508977A (en) 1983-01-11 1985-04-02 Burroughs Corporation Re-programmable PLA
US20030112055A1 (en) 2001-12-14 2003-06-19 Reber Douglas M. Anti-fuse circuit and method of operation
US20070030719A1 (en) * 2005-08-05 2007-02-08 Hoefler Alexander B One time programmable memory and method of operation
US20080106926A1 (en) 2006-11-08 2008-05-08 Symetrix Corporation Non-volatile resistance switching memories and methods of making same
US20100008132A1 (en) 2008-07-08 2010-01-14 Cheol-Seong Hwang Resistance memory element, phase change memory element, resistance random access memory device, information reading method thereof, phase change random access memory device, and information reading method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3102230A (en) 1960-03-08 1963-08-27 Bell Telephone Labor Inc Electric field controlled semiconductor device
US4508977A (en) 1983-01-11 1985-04-02 Burroughs Corporation Re-programmable PLA
US20030112055A1 (en) 2001-12-14 2003-06-19 Reber Douglas M. Anti-fuse circuit and method of operation
US20070030719A1 (en) * 2005-08-05 2007-02-08 Hoefler Alexander B One time programmable memory and method of operation
US20080106926A1 (en) 2006-11-08 2008-05-08 Symetrix Corporation Non-volatile resistance switching memories and methods of making same
US20100008132A1 (en) 2008-07-08 2010-01-14 Cheol-Seong Hwang Resistance memory element, phase change memory element, resistance random access memory device, information reading method thereof, phase change random access memory device, and information reading method thereof

Non-Patent Citations (18)

* Cited by examiner, † Cited by third party
Title
"Resistance Switching Characteristics in Polycrystalline Silicon Film Resistors", J. ELECTROCHEM. SOC., vol. 132, no. 5, 1985, pages 1193 - 1196
A. CRESPO-YEPES, J. MARTIN-MARTINEZ, A. ROTHSCHILD, R. RODRIGUEZ, M. NAFRIA, X. AYMERICH: "Recovery of the MOSFET and circuit functionality after the dielectric breakdown of ultrathin high-k gate stacks", IEEE ELECTRON DEVICE LETTERS, vol. 31, no. 6, June 2010 (2010-06-01), XP011307732
A. CRESPO-YEPES, J. MARTIN-MARTINEZ, R. RODRIGUEZ, M. NAFRIA, X. AYMERICH: "Resistive switching-like behaviour of the dielectric breakdown in ultra-thin Hf based gate stacks in MOSFETS", SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2010 PROCEEDINGS OF THE EUROPEAN
CRESPO-YEPES A ET AL: "Recovery of the MOSFET and Circuit Functionality After the Dielectric Breakdown of Ultrathin High-k Gate Stacks", IEEE ELECTRON DEVICE LETTERS, IEEE SERVICE CENTER, NEW YORK, NY, US, vol. 31, no. 6, 1 June 2010 (2010-06-01), pages 543 - 545, XP011307732, ISSN: 0741-3106 *
CRESPO-YEPES A ET AL: "Resistive switching-like behaviour of the dielectric breakdown in ultra-thin Hf based gate stacks in mosfets", SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2010 PROCEEDINGS OF THE EUROPEAN, IEEE, PISCATAWAY, NJ, USA, 14 September 2010 (2010-09-14), pages 138 - 141, XP031787645, ISBN: 978-1-4244-6658-0 *
D. B. STRUKOV, K. K. LIKHAREV: "CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices", NANOTECHNOLOGY, vol. 16, no. 6, 2005, pages 888 - 900, XP020091102, DOI: doi:10.1088/0957-4484/16/6/045
G. S SNIDER, R. S. WILLIAMS: "Nano/CMOS architectures using a field-programmable nanowire interconnect", NANOTECHNOLOGY, vol. 18, no. 3, 2007, pages 035204, XP020119626, DOI: doi:10.1088/0957-4484/18/3/035204
G. SINDER, P. KUEKES, T. HOGG, R. STANLEY WILLIAMS: "Nanoelectronic architectures", APPL.PHYSICS A, vol. 80, 2005, pages 1183 - 1195
J. BORGHETTI, Z.LI, J. STRAZNICKY, X. LI, D.A. OHLBERG, D.R. STEWART, R. STANLEY WILLIAMS: "A hybrid nanomemristor/transistor logic circuit capable of self-programming", PROCEEDINGS OF THE NATIONAL ACADEMY OF SCIENCES OF THE UNITED STATES OF AMERICA, Retrieved from the Internet <URL:www.pnas.org/cgi/doi/10.1073/pnas.0806642106>
JING GUO ET AL: "Assessment of silicon MOS and carbon nanotube FET performance limits using a general theory of ballistic transistors", IEEE XPLORE; [INTERNATIONAL ELECTRON DEVICES MEETING],, 8 December 2002 (2002-12-08), pages 711 - 714, XP010626140, ISBN: 978-0-7803-7462-1, DOI: DOI:10.1109/IEDM.2002.1175937 *
M. Y. CHAN, T. ZHANG, V. HO, P. S. LEE: "Resistive switching effects on Hf02 high-k dielectric", MICROELECTRONICS ENGINEERING, vol. 85, 2008, pages 2420 - 2424, XP025710406, DOI: doi:10.1016/j.mee.2008.09.021
Q. XIA ET AL.: "Memristor-CMOS Hybrid Integrated Circuits for Reconfigurable Logic", NANO LETTERS, vol. 9, no. 10, 2009, pages 3640 - 3645
R. WASER: "Resistive non-volatile memory devices", MICROELECTRONIC ENGINEERING, vol. 86, 2009, pages 1925 - 1928, XP026158528, DOI: doi:10.1016/j.mee.2009.03.132
S. KAERIYAMA, T. SAKAMOTO, H. SUNAMURA, M. MIZUNO, H. KAWAURA, T. HASEGAWA, K. TERABE, T. NAKAYAMA, M. AONO: "A nonvolatile programmable solid-electrolyte nanometer switch", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 40, no. 1, 2005, pages 168 - 176
THE NOBEL PRIZE IN PHYSICS, 2000
W. ZHANG, N. K. JHA, L. SHANG: "NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture", ANNUAL ACM IEEE DESIGN AUTOMATION CONFERENCE, PROC. OF THE 43RD ANNUAL DESIGN AUTOMATION CONFERENCE, 2006, pages 711 - 716, XP010936595, DOI: doi:10.1109/DAC.2006.229220
XUEJUE HUANG ET AL: "Sub 50-nm FinFET: PMOS", ELECTRON DEVICES MEETING, 1999. IEDM TECHNICAL DIGEST. INTERNATIONAL WASHINGTON, DC, USA 5-8 DEC. 1999, PISCATAWAY, NJ, USA,IEEE, US, 5 December 1999 (1999-12-05), pages 67 - 70, XP010372115, ISBN: 978-0-7803-5410-4, DOI: DOI:10.1109/IEDM.1999.823848 *
Y. TAUR, T. H. NING: "Fundamentals of Modem VLSI Devices", 1998, CAMBRIDGE UNIVERSITY PRESS

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10396175B2 (en) 2014-11-25 2019-08-27 University Of Kentucky Research Foundation Nanogaps on atomically thin materials as non-volatile read/writable memory devices
US10886333B2 (en) 2019-03-01 2021-01-05 International Business Machines Corporation Memory structure including gate controlled three-terminal metal oxide components
TWI734452B (zh) * 2020-04-23 2021-07-21 友達光電股份有限公司 記憶體裝置以及寫入方法

Similar Documents

Publication Publication Date Title
Siemon et al. Stateful three-input logic with memristive switches
US10056907B1 (en) Field programmable gate array utilizing two-terminal non-volatile memory
JP5032611B2 (ja) 半導体集積回路
US8674724B2 (en) Field programmable gate array utilizing two-terminal non-volatile memory
Gaillardon et al. Design and architectural assessment of 3-D resistive memory technologies in FPGAs
US8901962B2 (en) Programmable logic device structure using third dimensional memory
US9548741B1 (en) Memristive akers logic array
US20140292368A1 (en) Field programmable gate array utilizing two-terminal non-volatile memory
EP2737628B1 (fr) Matrice de portes programmables par l&#39;utilisateur qui utilise une mémoire non-volatile à deux bornes
US9729155B2 (en) Field programmable gate array utilizing two-terminal non-volatile memory
US8081499B2 (en) Semiconductor integrated circuit
WO2012085627A1 (fr) Procédé de fonctionnement d&#39;un transistor, architecture de traitement reconfigurable et utilisation d&#39;un transistor cassé et restauré pour un fonctionnement à multiples modes
Mbarek et al. On the design and analysis of a compact array with 1T1R RRAM memory element
Strukov et al. Reconfigurable nano-crossbar architectures
Haghiri et al. A memristor based binary multiplier
US10396798B2 (en) Reconfigurable circuit
Junsangsri et al. Logic-in-memory with a nonvolatile programmable metallization cell
Levisse et al. Resistive switching memory architecture based on polarity controllable selectors
Abusultan et al. Exploring static and dynamic flash-based FPGA design topologies
JP2017037689A (ja) 半導体装置およびスイッチセルの書き換え方法
Aljafar et al. Memristor-based volistor gates compute logic with low power consumption
Kang et al. Energy-efficient memristive analog and digital electronics
Ziegler et al. Eliminating capacitive sneak paths in associative capacitive networks based on complementary resistive switches for in-memory computing
Laiho et al. Memristive analog arithmetic within cellular arrays
Almudever et al. Shape-shifting digital hardware concept: Towards a new adaptive computing system

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11729698

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11729698

Country of ref document: EP

Kind code of ref document: A1