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WO2012059004A1 - 芯片封装方法 - Google Patents

芯片封装方法 Download PDF

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Publication number
WO2012059004A1
WO2012059004A1 PCT/CN2011/080875 CN2011080875W WO2012059004A1 WO 2012059004 A1 WO2012059004 A1 WO 2012059004A1 CN 2011080875 W CN2011080875 W CN 2011080875W WO 2012059004 A1 WO2012059004 A1 WO 2012059004A1
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WO
WIPO (PCT)
Prior art keywords
wafer
mask
packaging method
chip packaging
ball
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2011/080875
Other languages
English (en)
French (fr)
Inventor
石磊
陶玉娟
高国华
舜田直实
目黑弘一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nantong Fujitsu Microelectronics Co Ltd
Original Assignee
Nantong Fujitsu Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nantong Fujitsu Microelectronics Co Ltd filed Critical Nantong Fujitsu Microelectronics Co Ltd
Priority to US13/883,399 priority Critical patent/US9362173B2/en
Publication of WO2012059004A1 publication Critical patent/WO2012059004A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a wafer level chip packaging method. Background technique
  • Wafer Level Chip Size Packaging is a technology that performs a package test on a whole wafer and then cuts a single finished chip.
  • the packaged chip size is exactly the same as the chip.
  • Wafer-level chip-scale packaging technology revolutionizes traditional packaging such as Ceramic Leadless Chip Carriers and Organic Leadless Chip Carriers, and is increasingly light in the market for microelectronics. , small, short, thin and low-cost requirements.
  • the chip size after wafer-level chip-scale packaging technology has been highly miniaturized, and the cost of the chip has been significantly reduced as the chip size has decreased and the wafer size has increased.
  • Wafer-level chip-size packaging technology is a technology that integrates IC design, wafer fabrication, package testing, and integration. It is a hot spot and future development trend in the current packaging field.
  • Chinese Patent Application No. 200610096807.5 discloses a packaging method based on wafer level chip size, which mainly includes the following process steps:
  • the semiconductor wafer 1 is bonded to the first glass substrate 2 of the same size, so that in the initial stage of the package, the device portion of the wafer surface will be covered by the substrate to protect the external environment. Pollution and damage.
  • the semiconductor wafer 1 is thinned relative to the back surface of the first glass substrate 2, and the back surface of the wafer is selectively etched by photolithography and plasma etching to form a plurality of V shapes.
  • the trench serves as a dicing street and exposes a portion of the die pad 11 (i.e., the chip electrode).
  • the V-shaped groove is filled with an insulating medium, and the second glass substrate 3 and the solder mask 4 are pressed against the back surface of the wafer.
  • the second glass substrate 3 is used to support the semiconductor wafer 1 and is electrically heated
  • the insulating solder 4 is used to mechanically buffer the semiconductor wafer 1 in a subsequent mechanical cutting process.
  • a mechanical cutting process is used to semi-cut the position of the original V-shaped groove (without penetrating the separation chip), a new V-shaped groove is formed as a dicing street of the wafer, and the die pad 11 is formed from a V shape. The sides of the grooves are exposed.
  • the outer lead 12 is then formed by an electroplating process, the outer lead 12-end is connected to the die pad n in the V-shaped groove, and the other end is extended to the back surface of the wafer, and the chip pad 11 is The electrical function extends through the outer leads 12 to the back side of the wafer.
  • an insulating protective layer 14 is selectively formed on the back surface of the wafer to expose a portion of the outer leads 12, and solder bumps 15 are formed on the exposed outer leads 12 to cut the wafer along the V-shaped grooves on the back surface thereof.
  • the dicing is performed to form a discrete chip, and then the discrete chip is packaged in the outer casing to finally complete the packaging process of the chip.
  • the existing wafer level chip packaging method has the following problems: when the outer lead 12 is formed by an electroplating process, the metal in the scribe line (for example, in the V-shaped groove described in the above patent) is also easily plated and precipitated, resulting in the connection. A short circuit occurs between them. In addition, after cutting, the side surface of the discrete chip, that is, the side wall of the original V-shaped groove, is exposed to the external environment, and is easily damaged when the outer casing is packaged, thereby causing the external lead to be broken, thereby affecting the yield of the chip. SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to provide a chip packaging method which can improve packaging efficiency and yield.
  • the chip packaging method provided by the present invention comprises the steps of: providing a semi-packaged wafer, the metal pad having a dicing street and a chip on the package wafer; forming a ball metal electrode on the metal pad by a selective forming process ;
  • the wafer is diced along the scribe line.
  • the selective formation process is selective plating.
  • the selective plating process includes:
  • Forming a mask layer on the surface of the wafer Forming a mask layer on the surface of the wafer, the mask layer exposing a position on the wafer where a metal ball under the ball is to be formed; performing a zincate cleaning process on the surface of the wafer; using the mask layer as a mask, using no Electrolytic plating, nickel metal and gold metal are sequentially plated on the wafer; the mask layer is removed.
  • the plating thickness of the nickel is 3 ⁇ m, and the plating thickness of gold is 0.05 ⁇ m.
  • the mask layer is a photoresist mask.
  • the selective formation process is selective vapor deposition.
  • the selective vapor deposition process includes: providing a mask on a surface of the wafer, the mask exposing a position on the wafer where a metal electrode under the ball is to be formed; using the mask as a mask, using a physical vapor deposition process, Nickel metal and copper metal are sequentially deposited on the wafer; the mask is removed.
  • the mask is a metal mask.
  • the protective layer has a thickness of 5 ⁇ m to 50 ⁇ m.
  • the protective layer is made of a thermosetting epoxy resin and formed by a screen printing technique.
  • the step of grinding the surface of the wafer is further included.
  • the grinding is performed by mechanical grinding, specifically comprising: placing the wafer on a fixed worktable; wrapping a nonwoven fabric having a softness less than the wafer on the grinding disc and adhering to the surface of the wafer; and impregnating the nonwoven with the polishing liquid Cloth, mechanical grinding.
  • the step of removing the thermosetting epoxy resin covering the top surface of the under-ball metal electrode by plasma etching is further included.
  • the temperature of the wafer is kept lower than the curing temperature of the thermosetting epoxy resin.
  • the thermosetting resin has a curing temperature of less than 200 °C.
  • thermosetting resin comprises a curing filler
  • the curing filler has a particle diameter smaller than 1/3 of the thickness of the epoxy printing.
  • thermosetting resin has a printing thickness of 15 ⁇ m
  • the curing filler has a particle diameter of less than 5 ⁇ m
  • the protective layer has an average thickness of 11 ⁇ m to 12 ⁇ m.
  • the wafer is subjected to a baking treatment or a surface-activated plasma treatment.
  • the packaging method of the present invention has the following advantages:
  • under-ball metal electrode by a selective forming process, which can effectively prevent the inside of the cutting channel
  • the metal is plated or deposited by vapor deposition when the metal electrode is fabricated under the ball.
  • a protective layer is formed on a region other than the metal electrode under the ball, and the protective layer covers the scribe line.
  • a thermosetting epoxy resin may be selected as the protective layer material. After the dicing, the thermosetting epoxy is used. The resin protects the sides of the discrete chip (the side walls of the original scribe line), especially the metal leads there, from damage.
  • FIG. 6 are schematic cross-sectional views showing steps of a conventional wafer level chip packaging method
  • FIG. 7 is a basic flow chart of the packaging method of the present invention
  • FIG. 8 is a schematic flow chart of a first embodiment of the present invention.
  • Figure 9 Figure 11 to Figure 21 are schematic views of the steps shown in Figure 8;
  • Figure 10 is a top plan view of Figure 9;
  • FIG. 23 and 24 are schematic views of part of the steps shown in Fig. 22.
  • the metal in the dicing street is easily plated out during the fabrication of the metal electrode under the ball to cause a short circuit, and after the dicing of the wafer, the side surface of the discrete chip is exposed to the external environment. damage.
  • the present invention solves the above problems by a selective forming process for forming a metal electrode under the ball and forming a protective layer covering the scribe line. The invention will now be described in detail with reference to the accompanying drawings.
  • the basic flow diagram of the encapsulation method provided in this embodiment is shown in FIG. 7, and includes:
  • Step S101 is performed to provide a semi-packaged wafer.
  • the semi-packaged wafer comprises: a semiconductor substrate formed with a chip, a dicing street dividing the wafer into a plurality of independent chip units, and a protective mask having a plurality of openings on the semiconductor substrate for insulation protection Metal exposed in the mold and opening Solder pad.
  • the protective mask may be an organic film such as polyimide, and the metal pad may be a conventional interconnect metal such as copper or aluminum.
  • Step S102 forming a sub-ball metal electrode on the metal pad by using a selective forming process
  • the above selective formation process avoids the influence of the metal in the dicing street when the metal electrode under the ball is fabricated.
  • the selective formation process may include selective plating or selective vapor deposition.
  • the selective plating process includes: forming a photoresist mask on the surface of the wafer for electroplating.
  • the electroless plating technique can be used to improve the uniformity of plating and to form a thinner under-ball metal electrode.
  • the selective vapor deposition process comprises: providing a mask on the surface of the wafer for vapor deposition, the mask may be a metal mask, and the same metal mask may be repeatedly used to reduce the cost when packaging the same batch of wafers. .
  • Common under-ball metal electrode materials include nickel, gold, copper, aluminum, titanium, tungsten, chromium or alloys thereof, combinations, etc., and the corresponding materials can be selected according to the actual thickness dimension of the metal electrode under the ball to meet the process and cost requirements.
  • Step S103 is performed to form a protective layer on a wafer and a region other than the metal ball under the ball, and the protective layer covers the scribe line.
  • the protective layer can improve the protection effect on the wafer, especially the metal in the scribe line, and improve the yield of the package.
  • the protective layer can be printed using a screen printing technique.
  • the protective layer may be a thermosetting resin such as an epoxy resin, a phenol resin, a urea resin, a melamine-formaldehyde resin, an unsaturated resin, a polyurethane, a polyimide, or the like.
  • the specific formation position of the protective layer can be selected to cover at least the scribe line.
  • the surface of the wafer should generally be treated by a grinding process.
  • plasma etching should be used to remove the partial protective layer on the top surface of the metal electrode under the ball due to the fluidity of the thermosetting resin to expose the top of the metal electrode under the ball, which facilitates the subsequent process of solder ball fabrication. .
  • Step S104 is performed to form a solder ball on the metal electrode under the ball.
  • the solder may be applied to the top of the metal electrode under the ball and then reflowed at a high temperature to form the solder ball.
  • Common solders include metals such as tin, lead, silver, copper, zinc, or alloys thereof, combinations, and the like.
  • Step S105 is performed to scribe the wafer along the scribe line to form a discrete chip. Mechanical cutting is usually performed with a blade having a width smaller than that of the cutting path, and laser cutting can also be used. The cut side of the discrete chip and the top edge are covered with a protective layer to protect the metal wiring from damage during subsequent packaging. Finally, the package of the chip casing is completed to complete the chip packaging process of the present invention.
  • FIG. 8 is a schematic flow chart of a first embodiment of the present invention
  • FIGS. 9 to 16 are schematic views of respective steps in the above flow, and each step will be described in detail below with reference to FIG. 8.
  • Step S201 is performed.
  • a semi-packaged wafer 10 is provided.
  • the semi-packaged wafer includes: a semiconductor substrate 100 formed with a chip, a dicing street 200 dividing the wafer into a plurality of individual chip units, and located at
  • the semiconductor substrate 100 has an opening protective mask 101, and a metal pad 102 exposing the chip in the opening.
  • the protective mask 101 may be an organic film such as polyimide, and the metal pad 102 may be a conventional interconnect metal such as copper or aluminum. It should be noted that the above semiconductor substrate 100 is not limited to an elemental silicon or silicon-on-insulator substrate, but should also include semiconductor devices, metal interconnections, and other semiconductor structures fabricated thereon.
  • the protective mask 101 covers the surface of the semiconductor structure to protect the chip.
  • the metal pad 102 of the chip serves as an electrode at the input/output end of the chip for extracting the electrical function of the chip.
  • 10 is a top plan view of the semi-packaged wafer. The wafer is formed with a grid-shaped scribe line 200.
  • the dicing street 200 divides the wafer into a plurality of square regions, and each square region represents an independent region.
  • the cross-sectional shape of the dicing street 200 may be an isosceles trapezoid, and the depth should not be too deep to affect the steel hardness of the wafer.
  • the opening width of the dicing street 200 is 30 to 80 ⁇ m.
  • the photoresist 301 may be a positive gel or a negative gel, and may be formed by spin coating or spray coating.
  • the photoresist 301 is positively coated and applied to the wafer by spin coating.
  • the thickness of the spin coating can be 1 ⁇ 10 ⁇ .
  • After spin-coating the photoresist it usually includes a pre-baking step, for example, under vacuum conditions, at a temperature of 85 degrees Celsius to 120 degrees Celsius, and heating for 30 seconds to 60 seconds, which can be volatilized to remove residuals in the above various spray/spin coating methods.
  • the organic solvent used enhances the adhesion between the photoresist 301 and the bottom wafer and the internal stress of the photoresist.
  • the photoresist 301 is exposed using a photolithographic mask, and the pattern of the photolithographic mask is transferred onto the photoresist 301.
  • the pattern of the photolithographic mask corresponds to the protective mask 101 on the wafer such that the area where the metal pad 102 forming the under-ball metal electrode is exposed is exposed.
  • the exposed areas of the photoresist 302 are characterized by oblique hatching in the figure.
  • the post-baking step should be included. Under vacuum conditions, heating at a temperature of 110 degrees Celsius to 130 degrees Celsius for 30 seconds to 60 seconds can reduce the standing wave effect.
  • the exposed photoresist 301 is developed to form a photoresist mask 302. Since the photoresist 301 is a positive gel, a developer applied to a positive gel such as tetramethylammonium hydroxide ( ⁇ ) or the like is used.
  • the wafer having the exposed photoresist 301 on the surface is immersed in the developing solution, and the exposed portion of the photoresist 301 is dissolved in the developing solution to finally form the photoresist mask 302. Then, the wafer is taken out, washed with deionized water, and the residual developer and the photoresist are taken out. After the cleaning is completed, it is also possible to assist in the hard baking step of evaporating the residual organic solvent on the photoresist mask 302, and at the same time functioning as a hard film.
  • the photoresist mask 302 will expose a position on the semi-packaged wafer 10 where the under-ball metal electrode is required to be formed, that is, the opening of the protective mask 101 is exposed.
  • the photoresist mask 302 is an electroplating mask, and electroless plating is performed on the metal pad 102 to form the under-ball metal electrode 103. Specifically, first, the surface of the wafer is subjected to zincate treatment to remove the oxide film on the surface of the metal pad 102 to reduce the contact resistance; and then the wafer is sequentially placed in the corresponding electrolyte to perform stepless electroless plating.
  • the photoresist does not react with the zincate or the electrolyte.
  • the position of the wafer surface other than the metal pad 102, especially at the dicing street 200, is located at the bottom of the photoresist mask 302, so that metal plating is not precipitated, thereby implementing the selective plating process of the present invention. . As shown in FIG. 15, the photoresist mask 302 is removed.
  • the photoresist mask 302 may be removed by using an ashing process, including: introducing oxygen, and heating the photoresist mask 302 at a temperature of 100 degrees Celsius to 250 degrees Celsius for 30 seconds to 60 seconds. .
  • Step S204 is performed.
  • a protective layer 303 is formed on the wafer by a screen printing technique, and the protective layer 303 covers the scribe line 200.
  • the protective layer 303 is a thermosetting resin as exemplified above.
  • the protective layer 303 is preferably a thermosetting epoxy resin for the purpose of cost reduction.
  • the position at which the above protective layer 303 is formed can be selected by adjusting the screen opening used for screen printing.
  • the schematic diagram of the screen printing process is as shown in FIG. 17, comprising: fixing the wafer 10 in a printing device, the bottom of the screen plate 20, and applying a liquid epoxy resin on the screen plate 20;
  • the doctor blade 30 presses the screen plate 20 and the wafer 10 such that the liquid epoxy resin is applied to the surface of the wafer 10 through the opening of the screen plate 20; the screen plate 20 is removed from the wafer 10, so that the liquid
  • the epoxy is transcribed onto the wafer 10 to form the desired pattern.
  • the protective layer 303 has a thin film structure and has a thickness ranging from 5 ⁇ m to 50 ⁇ m.
  • the curing temperature of the epoxy resin used in this embodiment is less than 200 °C.
  • a curing filler such as a filler containing silica or other solid particles is usually included in the epoxy resin.
  • the filler particle diameter should be less than 1/3 of the printed thickness to achieve uniformity of film printing and flatness requirements, thereby reducing warpage of the surface of the wafer 10.
  • the printed thickness is controlled by adjusting the emulsion thickness of the screen plate 20.
  • the printing thickness of the liquid epoxy resin is 15 ⁇ m, and the diameter of the filler particles is not more than 5 ⁇ m, and the average thickness of the protective layer 303 formed by curing the epoxy resin can be controlled at 11 ⁇ . 12 ⁇ .
  • the liquid epoxy resin since the liquid epoxy resin has fluidity, it is inevitably infiltrated into the under-ball metal electrode 103 region.
  • the epoxy resin located on the top surface of the under-ball metal electrode 103 will reduce the contact area of the solder ball with the under-ball metal electrode 103, thereby The combination of the solder ball and the under-metal electrode 103 is hindered, and even the solder ball may fall off during the reliability test after the package and the substrate drop test, which may have an adverse effect. Therefore, after the protective layer 303 is formed, it is usually necessary to surface-treat the wafer 10 by polishing to remove the residue.
  • the grinding may be mechanical or chemical grinding or the like. As shown in FIG.
  • the specific grinding process used includes: placing the wafer 10 on a fixed worktable; and making the softness less than the nonwoven of the wafer.
  • the cloth 40 is wound around the polishing disk 50 and abuts against the surface of the wafer 10; then the nonwoven fabric 40 is impregnated with a polishing liquid, and mechanically ground to remove residue material adhering to the surface of the wafer 10.
  • a plasma etching process may be further performed to further remove the epoxy resin covering the top surface of the under-ball metal electrode 103.
  • the etching gas of the above plasma etching process contains oxygen and can be removed by reacting with a cured epoxy resin to form a gas.
  • Step S205 is performed; as shown in FIG. 20, a solder ball is formed on the top of the metal electrode 103 under the ball by a solder reflow process.
  • solder paste is applied to the under-ball metal electrode 103, and then subjected to high-temperature reflow, so that the solder paste is converted into the solder ball 104.
  • an underfill process is also performed on the surface of the wafer other than the solder balls 104. Step S206 is performed. As shown in FIG. 21, after the solder ball fabrication process is completed, the wafer 10 is diced along the scribe line 200 to form a discrete chip.
  • the wafer 10 is mechanically cut by using a dicing blade having a width smaller than the dicing street 200, so that after cutting, the side surface, the edge top and the surface of the discrete chip are covered with a continuous protective layer 303, the metal lead at the above position or Other semiconductor structures are effectively protected.
  • the above-mentioned discrete chip is packaged in a casing, and finally the chip packaging method of the present invention is completed.
  • Fig. 22 is a flow chart showing a second embodiment of the present invention
  • Figs. 23 and 24 are schematic views showing part of the steps in the above flow. The respective steps will be described in detail below with reference to Fig. 22.
  • Step S301 is performed; providing a semi-packaged wafer, the semi-packaged wafer comprising: a semiconductor substrate formed with a chip, a dicing street dividing the wafer into a plurality of individual chip units, and having an opening on the semiconductor substrate A protective mask is exposed, and a metal pad of the chip is exposed in the opening.
  • This step is the same as the first embodiment, as shown in Fig. 9 and Fig. 10.
  • Step S302 is performed. As shown in FIG.
  • a mask 60 is disposed on the surface of the wafer 10.
  • the mask may be a metal glass or a hard mask of other materials, and is adhered to the wafer 10, and the mask is An opening is formed in 60, and the opening of the mask 60 is aligned with the opening of the surface of the wafer 10 to protect the opening of the mask 101, that is, the metal pad 103 of the chip on the wafer 10.
  • the mask 60 is a copper plate.
  • an organic or inorganic lubricant may be applied to the surface of the wafer 10, and then the mask 60 is attached to the wafer. 10 on. The above lubricant also prevents gas from entering the gap between the mask 60 and the wafer 10 in the subsequent vapor deposition, and forms excess metal in the region outside the opening.
  • Step S303 is performed.
  • the wafer 10 and the mask 60 are placed in a deposition chamber, and a nickel metal and a copper metal are sequentially deposited by a physical vapor deposition process to form a desired under-ball metal electrode. 103.
  • the above metal may only be deposited in the opening of the protective mask 101, that is, the predetermined under-ball metal electrode 103 is formed, thereby achieving selective vapor deposition. Since the positions of the under-ball metal electrodes formed are the same when the same batch of wafers are packaged, the mask sheet 60 can be repeatedly used, which is more economical and more economical than the first embodiment.
  • the vapor deposition process of the under-ball metal electrode 103 has the advantages of faster deposition speed and shorter process flow than electroless plating.
  • the mask 60 is removed.
  • a protective layer 303 is formed on the wafer by a screen printing technique, and a protective layer 303 is overlaid on the dicing street 200.
  • Step S305 is performed on the metal electrode under the ball.
  • a solder ball is formed by a solder reflow process; in step S306, the wafer 10 is diced along the scribe line 200.
  • the semi-finished product of the wafer 10 may be first baked or plasma-activated before screen printing. deal with.
  • the present invention has been disclosed in the preferred embodiments as described above, but it is not intended to limit the invention, and the present invention may be utilized by the method and technical contents disclosed above without departing from the spirit and scope of the invention.
  • the technical solutions make possible changes and modifications, and the technical features having the differences in the above two embodiments are mutually replaced. Therefore, the content that does not deviate from the technical solutions of the present invention belongs to the protection scope of the technical solution of the present invention.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明提供了一种芯片封装方法，包括步骤：提供半封装晶圆，所述办封装晶圆上具有切割道以及芯片的金属焊垫；采用选择性形成工艺在所述金属焊垫上形成球下金属电极；在晶圆上、球下金属电极以外区域形成保护层，且所述保护层覆盖于所述切割道上；在所述球下金属电极上形成焊球；沿切割道对晶圆进行划片。本发明能够使得切割道内的金属在制作球下金属电极时不受到影响，且在切割后能够保护分立芯片的侧面，工艺流程简单，提高了封装效率以及成品率。

Description

芯片封装方法 本申请要求于 2010年 11 月 05 日提交中国国家知识产权局、 申请号为 201010534406.X, 发明名称为"芯片封装方法"的中国专利申请的优先权， 其全 部内容通过引用结合在本申请中。 技术领域
本发明涉及半导体技术领域， 尤其涉及一种晶圆级的芯片封装方法。 背景技术
晶圆级芯片尺寸封装（ Wafer Level Chip Size Packaging, WLCSP )技术是 对整片晶圆进行封装测试后再切割得到单个成品芯片的技术，封装后的芯片尺 寸与棵片完全一致。晶圆级芯片尺寸封装技术彻底颠覆了传统封装如陶瓷无引 线芯片载具 ( Ceramic Leadless Chip Carrier ) 、 有机无引线芯片载具（Organic Leadless Chip Carrier ) 的模式， 顺应了市场对微电子产品日益轻、 小、 短、 薄 化和低价化要求。经晶圆级芯片尺寸封装技术封装后的芯片尺寸达到了高度微 型化， 芯片成本随着芯片尺寸的减小和晶圆尺寸的增大而显著降低。 晶圆级芯 片尺寸封装技术是可以将 IC设计、 晶圆制造、 封装测试、 整合为一体的技术， 是当前封装领域的热点和未来发展的趋势。
中国发明专利申请第 200610096807.5号公开了一种基于晶圆级芯片尺寸 的封装方法， 主要包括如下工艺步骤：
首先如图 1所示， 将半导体晶圆 1与同样尺寸的第一玻璃基板 2粘接， 这样 在封装的初始阶段， 所述晶圆表面的器件部分将被基板盖住保护， 减少了外界 的污染和损害。
如图 2所示， 对半导体晶圆 1相对于第一玻璃基板 2的背面进行减薄， 并利 用光刻技术以及等离子刻蚀对所述晶圆背面进行选择性刻蚀， 形成多个 V形沟 槽作为切割道， 并暴露出部分芯片焊垫 11 (即芯片电极） 。
如图 3所示， 用绝缘介质填充所述 V形沟槽， 并在所述晶圆背面压合第二 玻璃基板 3以及焊料掩模 4。所述第二玻璃基板 3用于支撑半导体晶圆 1 , 而电热 绝缘焊料 4则用于在后续的机械切割工艺中起机械緩冲保护半导体晶圆 1的作 用。
如图 4所示， 采用机械切割工艺半切割原 V形沟槽所在位置 （不穿透分离 芯片） ， 形成新的 V形沟槽作为晶圆的切割道， 且使得芯片焊垫 11从 V形沟槽 的侧面暴露。
如图 5所示， 然后采用电镀工艺制作外引线 12, 所述外引线 12—端在 V形 沟槽内与芯片焊垫 n连接， 另一端延伸至晶圆背面， 所述芯片焊垫 11的电性功 能通过外引线 12而延伸至晶圆背面。
如图 6所示， 在晶圆背面选择性形成绝缘保护层 14, 露出部分外引线 12, 在露出的外引线 12上制作焊接凸点 15, 将上述晶圆沿其背面的 V形沟槽切割划 片， 形成分立芯片， 然后再对分立芯片进行外壳的封装， 最终完成芯片的封装 工艺。
现有的晶圆级芯片封装方法存在如下问题：在采用电镀工艺制作外引线 12 时， 切割道内 （例如上述专利所述的 V形沟槽内）的金属也容易电镀析出而导 致各连线之间发生短路。 此外在切割后， 分立芯片的侧面也即原 V形沟槽的侧 壁， 暴露于外界环境中， 在进行外壳封装时容易受到损伤， 导致外引线断路， 进而影响芯片的成品率。 发明内容 本发明解决的技术问题是提供一种芯片封装方法，可以提高封装效率以及 成品率。 本发明提供的芯片封装方法， 包括步骤： 提供半封装晶圆， 所述办封装晶圆上具有切割道以及芯片的金属焊垫； 采用选择性形成工艺在所述金属焊垫上形成球下金属电极；
在晶圆上、 球下金属电极以外区域形成保护层， 且所述保护层覆盖于所述 切割道上；
所述球下金属电极上形成焊球；
沿切割道对晶圆进行划片。
可选的， 所述选择性形成工艺为选择性电镀。 所述选择性电镀工艺包括：
在晶圆表面形成掩模层， 所述掩模层露出晶圆上需形成球下金属电极的 位置； 对晶圆表面进行锌酸盐清洗处理； 以所述掩模层为掩模， 采用无电解电 镀， 在晶圆上依次电镀镍金属以及金金属； 去除所述掩模层。
优选的， 所述镍的电镀厚度为 3μηι, 金的电镀厚度为 0.05μηι。 所述掩模 层为光刻胶掩模。
可选的， 所述选择性形成工艺为选择性气相沉积。
所述选择性气相沉积工艺包括： 在晶圆表面设置掩模板， 所述掩模板露 出晶圆上需形成球下金属电极的位置； 以所述掩模板为掩模， 采用物理气相沉 积工艺， 在晶圆上依次沉积镍金属以及铜金属； 移除所述掩模板。
优选的， 所述掩模板为金属掩模板。
可选的， 所述保护层的厚度为 5μηι~50μιη。 所述保护层的材质为热固性 环氧树脂， 采用丝网印刷技术形成。
优选的， 所述形成保护层后， 还包括研磨晶圆表面的步骤。 所述研磨采 用机械研磨， 具体包括： 将晶圆放置于固定工作台； 将柔软度小于晶圆的非织 造布缠绕于研磨盘上， 并紧贴晶圆表面； 使用研磨液浸润所述非织造布， 进行 机械研磨。
优选的， 所述形成保护层后， 还包括采用等离子刻蚀去除覆于球下金属 电极顶部表面的热固性环氧树脂的步骤。
优选的， 所述丝网印刷时， 保持晶圆的温度低于所述热固性环氧树脂的 固化温度。 所述热固性树脂的固化温度小于 200°C。
优选的， 所述热固性树脂中包含固化填充剂， 所述固化填充剂的颗粒直 径小于环氧树脂印刷厚度的 1/3。
优选的， 所述热固性树脂的印刷厚度为 15μηι, 固化填充剂的颗粒直径小 于 5μηι, 固化后形成的保护层平均厚度为 11μηι~12μιη。
优选的， 在进行丝网印刷技术时， 先对晶圆进行烘烤处理或者进行表面 活性化的等离子处理。 本发明所述封装方法具有如下优点：
1、 采用选择性形成工艺形成所述球下金属电极， 能够有效防止切割道内 的金属在制作球下金属电极时， 被电镀析出或者受到气相沉积的影响。
2、 在晶圆上， 球下金属电极以外区域形成保护层， 且所述保护层覆盖所 述切割道上， 具体的可以选择热固性环氧树脂作为保护层材料， 在划片后， 上 述热固性环氧树脂能够保护分立芯片的侧面 （原切割道的侧壁）， 尤其是该处 的金属引线， 不受到损伤。
3、 本发明工艺流程筒单， 成本低廉， 且提高了封装效率以及封装成品率。 附图说明
通过附图中所示的本发明的优选实施例的更具体说明 ,本发明的上述及其 他目的、特征和优势将更加清晰。 附图中与现有技术相同的部件使用了相同的 附图标记。 附图并未按比例绘制， 重点在于示出本发明的主旨。 在附图中为清 楚起见， 放大了层和区域的尺寸。
图 1至图 6为现有的一种晶圆级的芯片封装方法各步骤剖面示意图； 图 7为本发明所述封装方法的基本流程图；
图 8为本发明第一实施例的流程示意图；
图 9、 图 11至图 21为图 8所示各步骤的示意图；
图 10为图 9的俯视示意图；
图 22为本发明第二实施例的流程示意图；
图 23以及图 24为图 22所示部分步骤的示意图。
具体实施方式 现有的晶圆级芯片封装方法，切割道内的金属容易在球下金属电极制作时 电镀析出而导致短路，且晶圆在划片后， 分立芯片的侧面暴露于外界环境中容 易受到损伤。本发明则采用选择性形成工艺制作球下金属电极， 并且形成覆盖 切割道的保护层的方法解决上述问题。 下面结合附图对本发明进行具体说明。 本实施例提供的封装方法的基本流程示意图如图 7所示， 包括：
执行步骤 S101、 提供半封装晶圆。 具体的， 所述半封装晶圆包括： 形成有芯 片的半导体衬底、将晶圆划分成若干个独立芯片单元的切割道、位于半导体衬 底上起到绝缘保护作用且具有若干开口的保护掩模、开口内曝露出芯片的金属 焊垫。 所述保护掩模可以是聚酰亚胺等有机膜， 所述金属焊垫可以是铜、 铝等 常规的互连金属。
执行步骤 S102、 采用选择性形成工艺在所述金属焊垫上形成球下金属电 极；
上述选择性形成工艺， 避免了在制作球下金属电极时， 对切割道内的金 属造成影响。 所述选择性形成工艺可以包括选择性电镀或选择性气相沉积。
其中， 选择性电镀工艺包括： 在晶圆表面形成光刻胶掩模， 进行电镀。 具体的， 采用无电解电镀技术可以提高电镀的均匀性， 并且能够形成较薄的球 下金属电极。选择性气相沉积工艺包括：在晶圆表面设置掩模板进行气相沉积， 所述掩模板可以为金属掩模板， 在对同批次晶圆进行封装时， 可以反复利用同 一块金属掩模板以降低成本。
常见的球下金属电极材料包括镍、 金、 铜、 铝、 钛、 钨、 铬或其合金、 组合等， 可以根据球下金属电极的实际厚度尺寸限制选择相应材料， 以满足工 艺以及成本需求。
执行步骤 S103、 在晶圆上、 球下金属电极以外的区域形成保护层， 且所 述保护层覆盖于所述切割道上。
所述保护层能够改善对晶圆的保护效果， 尤其保护切割道内的金属， 提 高封装的成品率。 具体的， 可以采用丝网印刷技术印刷所述保护层。 为降低工 艺难度， 所述保护层可以采用热固性树脂， 例如环氧树脂、 酚醛树脂、 脲醛 树脂、 三聚氰胺 -甲醛树脂、 不饱和树脂、 聚氨酯、 聚酰亚胺等。 通过设 置丝网印刷所采用的丝网版的开口区域，即可以选择所述保护层的具体形成位 置， 使其至少覆盖于切割道上。
在形成保护层后， 通常应当采用研磨工艺处理晶圆的表面。 此外还应当 利用等离子刻蚀去除丝网印刷时，因热固性树脂的流动性而覆于球下金属电极 顶部表面的部分保护层， 以暴露出球下金属电极顶部，便于后续工艺进行焊球 的制作。
执行步骤 S104、 在所述球下金属电极上形成焊球。 可以在球下金属电极 的顶部先涂覆焊料，然后进行高温的回流，形成所述焊球。常见的焊料包括锡、 铅、 银、 铜、 锌等金属或其合金、 组合等。 执行步骤 S105、 沿所述切割道对晶圆进行划片， 形成分立的芯片。 通常采用宽度小于切割道的刀片进行机械切割，还可以采用激光切割。切 割后的分立芯片侧面以及顶部边缘均覆有保护层， 能够在后续封装过程中，保 护该处的金属布线避免受到损伤。最后进行芯片外壳的封装完成本发明所述芯 片封装工艺。 为进一步阐述本发明之优点，以下结合说明书附图提供了本发明的两个具 体实施例。 第一实施例 图 8为本发明第一实施例的流程示意图， 而图 9至图 16为上述流程中各 步骤的示意图， 以下结合图 8对各步骤进行详细说明。 执行步骤 S201 ; 如图 9所示， 提供半封装晶圆 10, 所述半封装晶圆包括： 形成有芯片的 半导体衬底 100、 将晶圆划分成若干个独立芯片单元的切割道 200、 位于所述 半导体衬底 100上具有开口的保护掩模 101、 所述开口内曝露出芯片的金属焊 垫 102。 所述保护掩模 101可以是聚酰亚胺等有机膜， 所述金属焊垫 102可以 是铜、 铝等常规的互连金属。 需要指出的是， 上述半导体衬底 100 并非局限于单质硅或绝缘体上硅衬 底， 还应当包括制作于其上的半导体器件、 金属互连以及其他半导体结构。 所 述保护掩模 101即覆于上述半导体结构的表面，从而起到保护芯片的作用。所 述芯片的金属焊垫 102作为芯片的输入 /输出端的电极， 用于引出芯片的电性 功能。 图 10为上述半封装晶圆的俯视示意图， 可见所述晶圆上形成有格子状的 切割道 200, 上述切割道 200将晶圆划分成若干方片区域， 每个方片区域代表 一块独立的芯片。 所述切割道 200的截面形状可以为等腰梯形， 深度不宜过深 以免影响晶圆的钢型硬度。 本实施例中， 所述切割道 200 的开口宽度为 30~80μηι。 执行步骤 S202; 如图 11所示， 在图 9所示半封装晶圆 10的表面形成光刻胶 301。
所述光刻胶 301可以为正胶也可以负胶，可以采用旋涂或者喷涂的方法形 成。 本实施例中， 所述光刻胶 301采用正胶， 并通过旋涂的方式均勾地涂覆于 晶圆上。 旋涂的厚度可以为 1~10μηι。 在旋涂光刻胶后， 通常还包括前烘的步骤， 例如在真空条件下， 以 85摄 氏度 ~120摄氏度的温度， 加热 30秒~60秒， 可以挥发去除残留上述各喷涂 / 旋涂方法中使用的有机溶剂，增强光刻胶 301与底部晶圆之间的粘附性以及释 放光刻胶的内应力等。
如图 12所示， 使用光刻掩膜版对光刻胶 301进行曝光， 将光刻掩膜版的 图形转移至光刻胶 301上。
其中， 所述光刻掩膜版的图形与晶圆上的保护掩模 101相对应，使得需形 成球下金属电极的金属焊垫 102所在的区域被曝光。图中以斜影线表征光刻胶 302的曝光区域。
通常在曝光结束后还应当包括后烘的步骤， 在真空条件下， 以 110摄氏度 ~130摄氏度的温度， 加热 30秒~60秒， 可以减少驻波效应。
如图 13所示， 对曝光后的光刻胶 301进行显影， 形成光刻胶掩模 302。 由于所述光刻胶 301为正胶， 因此采用应用于正胶的显影液， 例如四甲基 氢氧化铵（ΤΜΑΗ )等。 将上述表面具有曝光后的光刻胶 301的晶圆浸没于显 影液中， 所述光刻胶 301的曝光部分溶解于所述显影液， 最终形成光刻胶掩模 302。 然后取出晶圆， 使用去离子水对其进行清洗， 取出残留的显影液以及光 刻胶溶渣等。 在清洗结束后， 还可以辅助以硬烘的步骤， 蒸发光刻胶掩模 302 上的残留有机溶剂， 并同时起到坚膜的作用。
执行步骤 S203;
如图 14所示， 形成光刻胶掩模 302后， 所述光刻胶掩模 302将露出半封 装晶圆 10上所需形成球下金属电极的位置， 也即露出保护掩模 101开口内的 金属焊垫 102。 已所述光刻胶掩模 302为电镀掩模， 在所述金属焊垫 102上进 行无电解电镀形成球下金属电极 103。 具体的， 首先对晶圆表面进行锌酸盐处理，去除金属焊垫 102表面的氧化 物薄膜， 以降低接触电阻； 然后将晶圆依次放置于相应的电解液中进行分步的 无电解电镀，先进行无电解电镀镍再无电解电镀金， 最终形成凸出于晶圆表面 的球下金属电极 103。 具体的， 所述镍金属的电镀厚度为 3μηι, 金金属的电镀 厚度为 0.05μηι。 在上述电镀过程中， 光刻胶并不会与锌酸盐或者电解液发生反应。 晶圆表 面除金属焊垫 102以外的位置， 尤其是切割道 200处， 由于位于光刻胶掩模 302底部， 因此不会发生金属电镀析出的情况， 从而实现本发明所述的选择性 电镀工艺。 如图 15所示， 去除光刻胶掩模 302。 具体的， 可以采用灰化工艺去除所述光刻胶掩模 302, 包括： 通入氧气， 在 100摄氏度 ~250摄氏度的温度， 加热 30秒~60秒， 将所述光刻胶掩模 302 去除。 执行步骤 S204; 如图 16所示， 采用丝网印刷技术在晶圆上， 球下金属电极 103以外的区 域形成保护层 303 , 且所述保护层 303覆盖于切割道 200上。 其中， 所述保护层 303如前例举的热固性树脂。 本实施例中， 出于降低成 本的考量， 所述保护层 303优选热固性环氧树脂。通过调整丝网印刷所使用的 丝网版开口， 可以选择上述保护层 303的形成位置。 具体的， 所述丝网印刷的工艺示意图如图 17所示， 包括： 将晶圆 10固定 于印刷装置中， 丝网版 20的底部， 在丝网版 20上涂抹液态的环氧树脂； 用刮 刀 30按压丝网版 20以及晶圆 10, 使得液态的环氧树脂通过丝网版 20的开孔 处涂布至晶圆 10表面； 将丝网版 20从晶圆 10上揭下， 这样液态的环氧树脂 便转录至晶圆 10上， 形成所需图案。 本实施例中， 所述保护层 303为薄膜结构， 厚度范围为 5μηι~50μιη。 为了 保证其薄膜均匀性， 需要在丝网印刷的过程中保持热固性环氧树脂的流动性， 即保证晶圆的温度低于热固性环氧树脂的固化温度。 为降低工艺难度， 本实施例采用的环氧树脂的固化温度小于 200°C。 为了 改善环氧树脂的固化性能，通常环氧树脂中还包含固化填充剂， 例如含有二氧 化硅或其他固体颗粒的填充剂。所述填充剂颗粒直径应当小于印刷厚度的 1/3 , 以实现薄膜印刷的均匀性以及平整度需求， 从而减少晶圆 10表面的翘曲。 所 述印刷厚度通过调节丝网版 20的乳剂厚度进行控制。 本实施例中， 进行丝网 印刷时， 液态的环氧树脂的印刷厚度为 15μηι, 而填充剂颗粒直径最大不得超 过 5μηι , 环氧树脂固化后形成的保护层 303 的平均厚度可以控制在 11μηι~12μιη。 在丝网印刷过程中， 由于液态环氧树脂具有流动性，依然难免会渗入球下 金属电极 103区域。这样会存在如下问题： 当在球下金属电极 103顶部制作焊 球时，所述位于球下金属电极 103顶部表面的环氧树脂将使得焊球与球下金属 电极 103的接触面积减小，从而阻碍焊球与球下金属电极 103的结合， 甚至可 能在封装后的可靠性实验以及衬底跌落实验中导致焊球的脱落， 产生不良影 响。 因此在形成保护层 303后， 通常需要利用研磨对晶圆 10作表面处理， 去 除上述残渣。 所述研磨可以是机械或化学研磨等， 如图 18所示， 本实施例中， 所采用 的具体的研磨工艺包括： 将晶圆 10放置于固定工作台； 将柔软度小于晶圆的 非织造布 40缠绕于研磨盘 50上， 并紧贴晶圆 10表面； 然后使用研磨液浸润 所述非织造布 40, 进行机械研磨， 去除附着于晶圆 10表面的残渣物质。 作为另一个可选方案， 在研磨结束后， 如图 19所示， 还可以进行等离子 刻蚀工艺， 进一步去除上述覆于球下金属电极 103顶部表面的环氧树脂。上述 等离子刻蚀工艺的刻蚀气体包含氧气，能够与固化的环氧树脂发生反应生成气 体而除去。
执行步骤 S205; 如图 20所示， 在球下金属电极 103的顶部， 采用焊料回流工艺制作焊球
104。 本实施例中， 出于降低成本的考量， 采用锡作为焊料材质。 具体包括： 将焊料锡膏涂覆于球下金属电极 103上， 然后进行高温回流，使得所述焊料锡 膏转变成焊球 104。 通常为了保持晶圆其他部分表面的平整性以及加强绝缘保 护， 还会在焊球 104以外的晶圆表面进行底部填充工艺。 执行步骤 S206; 如图 21所示，在完成焊球制作工艺后，沿切割道 200对晶圆 10进行划片， 形成分立的芯片。 具体的， 采用宽度小于切割道 200的划片刀对晶圆 10机械 切割， 这样在切割后， 分立芯片的侧面、 边缘顶部以及表面均覆有连续的保护 层 303 , 位于上述位置的金属引线或其他半导体结构均能够得到有效的保护。 对上述分立芯片进行外壳封装， 最终完成本发明所述芯片封装方法。
第二实施例 图 22为本发明第二实施例的流程示意图， 而图 23以及图 24为上述流程 中部分步骤的示意图， 以下结合图 22对各步骤进行详细说明。 执行步骤 S301 ; 提供半封装晶圆， 所述半封装晶圆包括： 形成有芯片的半导体衬底、 将晶 圆划分成若干个独立芯片单元的切割道、位于所述半导体衬底上具有开口的保 护掩模、 所述开口内曝露出芯片的金属焊垫。 此步骤与第一实施例相同， 具体 见图 9以及图 10。 执行步骤 S302; 如图 23所示， 在晶圆 10的表面设置掩模板 60, 所述掩模板可以是金属 玻璃、 或其他材质的硬掩模板， 紧贴于晶圆 10上， 且上述掩模板 60上形成有 开口， 所述掩模板 60的开口对准晶圆 10表面保护掩模 101的开口， 也即暴露 出晶圆 10上芯片的金属焊垫 103。 本实施例中， 所述掩模板 60为铜板。 为了使的所述掩模板 60与晶圆 10 紧贴后的粘附性以及密封性良好， 可以先在晶圆 10表面涂抹有机或无机润滑 剂， 然后将所述掩模板 60贴合于晶圆 10上。上述润滑剂还可以防止后续进行 气相沉积时， 气体进入掩模板 60与晶圆 10之间的缝隙中， 而在开口以外区域 形成多余的金属。
执行步骤 S303; 如图 24所示， 将上述晶圆 10以及掩模板 60放置于沉积腔内， 采用物理 气相沉积工艺，依次进行镍金属以及铜金属的沉积， 形成所需的球下金属电极 103。 由于掩模板 60的存在， 上述金属仅可能沉积于保护掩模 101的开口内， 也即预定的球下金属电极 103形成位置， 从而实现选择性气相沉积。 由于同批次的晶圆在进行封装时， 形成的球下金属电极位置是相同的， 因 此上述掩模板 60可以重复使用， 与第一实施例相比较， 具有更为优异的经济 性，且采用气相沉积工艺制作球下金属电极 103相比于无电解电镀， 具有沉积 速度快， 工艺流程短的优点。 在完成球下金属电极 103的制作后， 移除所述掩模板 60。 然后执行步骤 S304, 采用丝网印刷技术在晶圆上， 球下金属电极 103 以 外的区域形成保护层 303 , 且所述保护层 303覆盖于切割道 200上； 执行步骤 S305 , 在球下金属电极 103 的顶部， 采用焊料回流工艺制作焊球； 执行步骤 S306, 沿切割道 200对晶圆 10进行划片。
以上后续步骤与第一实施例的步骤 S204、步骤 S205以及步骤 S306相同， 不再赘述。
此外， 在上述实施例中， 为了提高丝网印刷工艺中热固性树脂的附着力， 通常在丝网印刷之前， 还可以先对上述晶圆 10的半成品进行烘烤处理， 或者 进行表面活性化的等离子处理。 本发明虽然已以较佳实施例公开如上，但其并不是用来限定本发明，任何 本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法 和技术内容对本发明技术方案做出可能的变动和修改，并对上述两实施例中具 有差异的技术特征互相进行替换， 因此， 凡是未脱离本发明技术方案的内容， 均属于本发明技术方案的保护范围。

Claims

权 利 要 求
1.一种芯片封装方法， 其特征在于， 包括步骤：
提供半封装晶圆， 所述办封装晶圆上具有切割道以及芯片的金属焊垫； 采用选择性形成工艺在所述金属焊垫上形成球下金属电极；
在晶圆上、球下金属电极以外区域形成保护层，且所述保护层覆盖于所述 切割道上；
在所述球下金属电极上形成焊球；
沿切割道对晶圆进行划片。
2.如权利要求 1所述的芯片封装方法， 其特征在于， 所述选择性形成工艺 为选择性电镀。
3.如权利要求 2所述的芯片封装方法， 其特征在于， 所述选择性电镀工艺 包括：
在晶圆表面形成掩模层，所述掩模层露出晶圆上需形成球下金属电极的位 置；对晶圆表面进行锌酸盐清洗处理；以所述掩模层为掩模，采用无电解电镀， 在晶圆上依次电镀镍金属以及金金属； 去除所述掩模层。
4.如权利要求 3所述的芯片封装方法， 其特征在于， 所述镍的电镀厚度为 3μηι, 金的电镀厚度为 0.05μηι。
5.如权利要求 3所述的芯片封装方法， 其特征在于， 所述掩模层为光刻胶 掩模。
6.如权利要求 1所述的芯片封装方法， 其特征在于， 所述选择性形成工艺 为选择性气相沉积。
7.如权利要求 6所述的芯片封装方法， 其特征在于， 所述选择性气相沉积 工艺包括：
在晶圆表面设置掩模板，所述掩模板露出晶圆上需形成球下金属电极的位 置； 以所述掩模板为掩模， 采用物理气相沉积工艺， 在晶圆上依次沉积镍金属 以及铜金属； 移除所述掩模板。
8. 如权利要求 7所述的芯片封装方法， 其特征在于， 所述掩模板为金属 掩模板。
9. 如权利要求 1所述的芯片封装方法， 其特征在于， 所述保护层的厚度 为 5μηι~50μιη。
10. 如权利要求 1所述的芯片封装方法， 其特征在于， 所述保护层的材质 为热固性环氧树脂， 采用丝网印刷技术形成。
11. 如权利要求 1所述的芯片封装方法，其特征在于，所述形成保护层后， 还包括研磨晶圆表面的步骤。
12. 如权利要求 11 所述的芯片封装方法， 其特征在于， 所述研磨采用机 械研磨， 具体包括：
将晶圆放置于固定工作台；
将柔软度小于晶圆的非织造布缠绕于研磨盘上， 并紧贴晶圆表面； 使用研磨液浸润所述非织造布， 进行机械研磨。
13. 如权利要求 10所述的芯片封装方法， 其特征在于， 所述形成保护层 后，还包括采用等离子刻蚀去除覆于球下金属电极顶部表面的热固性环氧树脂 的步骤。
14. 如权利要求 10所述的芯片封装方法， 其特征在于， 所述丝网印刷时， 保持晶圆的温度低于所述热固性环氧树脂的固化温度。
15. 如权利要求 10所述的芯片封装方法， 其特征在于， 所述热固性树脂 的固化温度小于 200 °C。
16. 如权利要求 15所述的芯片封装方法， 其特征在于， 所述热固性树脂 中包含固化填充剂，所述固化填充剂的颗粒直径小于环氧树脂印刷厚度的 1/3。
17. 如权利要求 16所述的芯片封装方法， 其特征在于， 所述热固性树脂 的印刷厚度为 15μηι, 固化填充剂的颗粒直径小于 5μηι, 固化后形成的保护层 平均厚度为 11μηι~12μιη。
18. 如权利要求 10所述的芯片封装方法， 其特征在于， 在进行丝网印刷 技术时， 先对晶圆进行烘烤处理或者进行表面活性化的等离子处理。
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