WO2012058897A1 - Device for compensating clock delay and synchronization method for clock delay compensation - Google Patents

Abstract

This invention refers to a device for compensating clock delay, which includes a first triggering circuit, a delay compensating circuit, a second triggering circuit, a crystal oscillator, and a time output circuit. The crystal oscillator is connected to the time output circuit and the delay compensating circuit respectively. The delay compensating circuit is further connected to the first triggering circuit and the second triggering circuit respectively. The second triggering circuit is further connected to the time output circuit. The crystal oscillator is used for providing a stable clock frequency to the time output circuit and the delay compensating circuit. In addition, this invention also provides a synchronization method for clock delay compensation, where the clock synchronization is implemented by using the device for compensating clock delay. Such technical scheme can improve the synchronization precision of the clock, and is suitable for the places in demand of high-precision clock such as nuclear power plants, high-speed railways, stations and airports.

Description

 Clock post-compensation device and clock post-compensation synchronization method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of clock synchronization in a sub-master clock system, and more particularly to an apparatus for realizing clock push compensation and a clock post-compensation synchronization method. BACKGROUND OF THE INVENTION The single-item comparison method is an important method for clock synchronization in a sub-master clock system. The clock synchronization process is as follows:

The first step, at T. At the moment, the standard clock transmits a clock synchronization signal to the calibrated clock through the communication system. In the second step, after the transmission delay d, the calibrated clock receives the clock synchronization signal and records the reception time stamp, wherein the actual time of the clock synchronization signal received by the calibrated clock is τ but the time of recording and reception is τ ₂ , A time stamp error t is generated in the step. In the third step, the calibrated clock performs signal processing such as decoding, filtering, and verification, and a signal processing time t ' is generated in this step. In the fourth step, the synchronization time of the calibrated clock is adjusted to T ₃ =T. +d; where the transmission delay d is known, but the time stamp error t and the signal processing time are both difficult to measure and estimate, so the synchronization time accuracy obtained by the clock synchronization method is poor, see FIG. The error between the calibrated clock and the standard clock is large, and it is not suitable for places with high clock accuracy requirements such as nuclear power, high-speed rail, stations, and airports. SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to provide a synchronous time precision high clock post-compensation device and a method for performing clock post-compensation synchronization using the device.

As an aspect of the present invention, the technical solution of the clock post-compensation device is as follows: including a first trigger circuit, a push-back compensation circuit, a second trigger circuit, a crystal oscillator, and a time output circuit; The body oscillator is respectively connected to the time output circuit and the push-back compensation circuit, and the push-back compensation circuit is further connected to the first trigger circuit and the second trigger circuit, respectively, and the second trigger circuit further Connected to the time output circuit; wherein

 The crystal oscillator is configured to provide a stable clock frequency to the time output circuit and the push-back compensation circuit;

 The first trigger circuit is configured to receive a synchronization signal sent by a standard clock, and reduce a pulse width of the synchronization signal to trigger the push-back compensation circuit;

The push-back compensation circuit is configured to count the post-reduction compensation time T _{d of} the synchronization signal;

 The second trigger circuit is configured to receive a signal output by the push-back compensation circuit, and reduce a pulse width of the signal, and trigger the time output circuit;

 The time output circuit is configured to output the compensated synchronization signal.

Further, the clock post-compensation device further includes a filter circuit, and the filter circuit is connected to the first trigger circuit.

 The filtering circuit is configured to receive a synchronization signal sent by the standard clock, filter the interference signal, and send the signal to the first trigger circuit.

 As another aspect of the present invention, there is also provided a clock post-compensation synchronization method, wherein the clock is synchronized by the following steps:

Step 1: preset the post-push compensation time T _d ;

 Step 2: determining whether a synchronization signal is received: if received, starting the post-push compensation circuit inside the calibrated clock, and then performing step 3; otherwise, continuing to monitor reception;

 Step 3: The calibrated clock performs signal processing;

Step 4: Determine whether the T _d is reached _: if it has arrived, perform step 5; otherwise, continue to monitor and judge;

Step 5: Adjust the synchronization time of the clock to be calibrated according to the T _d to complete clock synchronization. Further, the T _{d is} not less than the time when the step 3 performs signal processing. Further, while the calibrated clock performs signal processing, it also determines whether the signal triggering the push-back compensation circuit is an interference signal:

If it is an interference signal, return to the step 2 after the T _d arrives and continue to wait for receiving the synchronization signal;

If the interference signal is then to be adjusted by the synchronization time T of the calibration according to the clock _d T _d after arrival.

 Further, the interference signal is judged by the pulse width ratio comparison method: if the pulse width value of the signal for triggering the push-back compensation circuit is greater than the preset pulse width value, it is an interference signal; otherwise, the synchronization signal is.

 The invention has the beneficial effects of providing a clock post-compensation device and a method for performing clock post-compensation synchronization by using the device. The clock synchronization precision of the technical solution of the invention is high, and is suitable for clocks of nuclear power, high-speed rail, station, airport, etc. A place with high precision requirements. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic structural view of a clock post-compensation device according to the present invention;

 2 is another schematic structural diagram of a clock post-compensation device according to the present invention;

 3 is a schematic flow chart of a clock post-compensation synchronization method according to the present invention;

 4 is a schematic flow chart of another method for clock post-compensation synchronization according to the present invention;

 FIG. 5 is a timing diagram of a process of a clock synchronization method according to the present invention. The principles and features of the present invention are described below in conjunction with the accompanying drawings, which are intended to illustrate the invention and not to limit the scope of the invention.

As an aspect of the present invention, as shown in FIG. 1, the clock post-compensation device includes a first flip-flop circuit 100, a post-push compensation circuit 200, a second flip-flop circuit 300, a crystal oscillator 400, and a time output circuit 500. The crystal oscillator 400 is connected to the time output circuit 500 and the post-compensation circuit 200, respectively, and the post-compensation circuit 200 is also connected to the first trigger circuit 100 and the second trigger circuit 300, respectively. The second trigger circuit 300 is also coupled to the time output circuit 500. The crystal oscillator 400 is configured to provide a stable clock frequency to the time output circuit 500 and the post-compensation circuit 200. The first trigger circuit 100 is configured to receive the synchronization signal sent by the standard clock, and reduce the pulse width of the synchronization signal. The post-push compensation circuit 200 is triggered; the post-compensation circuit 200 is configured to count the post-compensation time T _{d of the} synchronization signal; and the second trigger circuit 300 is configured to receive the signal output by the post-compensation circuit 200 and reduce the signal. The pulse width, the trigger time output circuit 500; the time output circuit 500, for outputting the compensated synchronization signal.

 As shown in FIG. 2, the clock post-compensation device further includes a filter circuit 600 connected to the first flip-flop circuit 100. The filter circuit 600 is configured to receive the synchronization signal sent by the standard clock, filter the interference signal, and send the signal to the first trigger circuit 100.

As another aspect of the present invention, a clock post-compensation synchronization method is further provided. The clock of the calibrated clock of the clock post-compensation device is installed according to the following steps, as shown in FIG. 3: Step 1: Pre-suppressed Compensation time T _d ;

 Step 2: Determine whether a synchronization signal is received: If received, start the post-compensation circuit inside the calibrated clock, and then perform step 3; otherwise, continue to monitor reception;

 Step 3: The signal is processed by the calibrated clock;

Step 4: Determine whether T _d is reached _: If it has arrived, proceed to step 5; otherwise, continue to monitor and judge;

Step 5: Adjust the synchronization time of the clock to be calibrated according to T _d to complete the clock synchronization.

Since in the practical application, the time stamp error t and the signal processing time are difficult to measure and estimate, the present invention eliminates the clock error in the synchronization process by setting a known post-reduction compensation time T _d , T ₃ =T ₀ + d+T _d , see Figure 5.

Further, in order to ensure the accuracy of clock synchronization, T _d should be no less than the time for signal processing in step 3.

In the technical solution of the present invention, the post-reduction compensation time T _d can be set by the following method: 1. When the synchronization signal input to the clock post-compensation device is a general signal, first estimate the time T′ of the signal processing such as signal decoding, filtering, and verification of the clock to be calibrated, and the post-reduction compensation time T _{d is} satisfied as long as T _d > T 'Yes, in order to improve the reliability, the difference between T _d and T ' can be set slightly larger.

2. When the synchronization signal input to the clock post-compensation device is the PPS signal, only the time T of the PPS signal for filtering processing can be measured, and T _d is the difference between the whole second and the filter processing time T, that is, T _d = lT.

In addition, in order to eliminate the spike interference generated by the components, the power supply or the transmission line inside the calibrated clock, while the calibrated clock performs the signal processing of step 3, it may further determine whether the signal triggering the post-compensation circuit is the above-mentioned interference signal. : if the interference signal, until after T _d continues to wait for arrival returns to the step 2 receives the synchronization signal; if T _d is based on the time alignment adjustment is synchronized clock signal after the interference, the T _d until arrival.

Due to the uncertainty of the delay time of the synchronization signal during transmission, the start-up time of the post-compensation circuit is uncertain. Therefore, the calibrated clock starts the post-push compensation circuit to start counting down as soon as the trigger signal is received, in order to improve the synchronization accuracy. Also verify that the trigger signal is a sync signal. If it is a synchronization signal, adjust T ₃ =T after the timing of the post-push compensation circuit is completed. +d+T _d ; If it is an interference signal, after the timing of the post-push compensation circuit is completed, the signal processing result is discarded, and the synchronization signal is re-waited.

 In the above step of verifying the trigger signal, the interference signal can be judged by the pulse width ratio method: if the pulse width value of the signal of the triggering compensation circuit is greater than the preset pulse width value, it is an interference signal; otherwise, it is a synchronization signal.

 The technical solution of the present invention will be described in detail below by taking the PPS signal as an example.

The Global Navigation Positioning System (GPS) is equipped with four high-precision atomic clocks per satellite. It is not only a precise positioning system, but also transmits high-precision time information. The GPS signal solving device receives different navigation satellite signals through the GPS antenna, and solves these signals to obtain time information such as year, month, and day, and PPS signals, and sends them to the user, that is, the clock to be calibrated. Wherein, the PPS signal is a pulse signal, Its edge is aligned with the whole second, which is an important signal to ensure the accuracy of clock synchronization. The steps of the technical solution of the present invention for clock synchronization are as follows:

 In the first step, the clock post-compensation device receives the PPS signal, because the signal may have interference pulse noise after being transmitted over a long distance. In order to avoid the influence of the noise on the clock synchronization accuracy, the filter circuit 600 first filters out the clutter and eliminates Interference, the time for filtering processing here is T.

In the second step, since the rising edge of the PPS signal can trigger the push-back compensation circuit 200, the falling edge can stop the trigger. When the pulse width is too large, the high-level signal will continuously trigger the push-back compensation circuit 200, so the first step is required. the trigger circuit PPS signal into a narrow pulse output sharp, precise compensation circuit 200 is triggered, pushing the push compensation time counted after the PPS signal T _d.

In the third step, after the time output circuit 500 is triggered by the narrow pulse outputted by the second trigger circuit 300, the compensated PPS signal is output, and the trigger post-compensation circuit performs a delay countdown according to T _d (T _d = l - T ).

 In the fourth step, the calibrated clock performs signal processing steps such as decoding, filtering, and verifying; at the same time, the calibrated clock further verifies the signal triggering the post-compensation circuit to prevent the interfering signal from impersonating the PPS signal. Specifically, it can be performed by: setting a counter, starting from the rising edge of the signal to start counting, and stopping the counting on the falling edge, then the pulse width of the signal is saved in the counter, if the pulse width value is not greater than the preset pulse width value , it is considered to be a PPS signal.

In the fifth step, after the T _d counting is completed, the synchronization time of the clock to be calibrated is adjusted to be T ₃ =T. +d+T _d , thereby improving the synchronization precision of the clock for clock synchronization using the technical solution of the present invention.

 The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., which are within the spirit and scope of the present invention, should be included in the protection of the present invention. Within the scope.

Claims

Claim  A clock post-compensation device, comprising: a first trigger circuit, a push-back compensation circuit, a second trigger circuit, a crystal oscillator, and a time output circuit; and the crystal oscillator and the time output circuit respectively The push-back compensation circuit is connected to the first trigger circuit and the second trigger circuit, and the second trigger circuit is further connected to the time output circuit;  The crystal oscillator is configured to provide a stable clock frequency to the time output circuit and the push-back compensation circuit;  The first trigger circuit is configured to receive a synchronization signal sent by a standard clock, and reduce a pulse width of the synchronization signal to trigger the push-back compensation circuit; The push-back compensation circuit is configured to count the post-compensation time T _{d of} the synchronization signal; the second trigger circuit is configured to receive a signal output by the post-push compensation circuit, and reduce a pulse width of the signal , triggering the time output circuit;  The time output circuit is configured to output the compensated synchronization signal.  2. The clock post-compensation device according to claim 1, further comprising a filter circuit, wherein the filter circuit is connected to the first trigger circuit,  The filtering circuit is configured to receive a synchronization signal sent by the standard clock, filter the interference signal, and send the signal to the first trigger circuit.  3. A clock push compensation synchronization method, characterized in that  The calibrated clock to which the clock post-compensation device of claim 1 is mounted performs clock synchronization as follows: Step 1: preset the post-push compensation time T _d ; Step 2: determining whether a synchronization signal is received: if received, starting the post-compensation circuit inside the calibrated clock, and then performing step 3; otherwise, continuing to monitor reception; Step 3: The calibrated clock performs signal processing; Step 4: Determine whether the T _d is reached _: if it has arrived, proceed to step 5; otherwise, continue to monitor and judge; Step 5: Adjust the synchronization time of the clock to be calibrated according to the T _d to complete clock synchronization. 4. The clock post-compensation synchronization method according to claim 3, wherein the _{Td is} not less than a time during which the step 3 performs signal processing.  The clock push compensation synchronization method according to claim 3 or 4, wherein the calibrated clock performs signal processing, and further determines whether the signal triggering the push-back compensation circuit is an interference signal: If it is an interference signal, return to the step 2 after the T _d arrives and continue to wait for receiving the synchronization signal; If the interference signal is then to be adjusted by the synchronization time T of the calibration according to the clock _d T _d after arrival.  The clock push compensation synchronization method according to claim 5, wherein the interference signal is determined by a pulse width ratio method: if a pulse width value of the signal triggering the push compensation circuit is greater than a preset pulse width The value is the interference signal; otherwise it is the synchronization signal.