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WO2012053729A1 - Carte de circuit imprimé et son procédé de fabrication - Google Patents

Carte de circuit imprimé et son procédé de fabrication Download PDF

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Publication number
WO2012053729A1
WO2012053729A1 PCT/KR2011/004873 KR2011004873W WO2012053729A1 WO 2012053729 A1 WO2012053729 A1 WO 2012053729A1 KR 2011004873 W KR2011004873 W KR 2011004873W WO 2012053729 A1 WO2012053729 A1 WO 2012053729A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
insulation
insulation layer
circuit board
circuit pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2011/004873
Other languages
English (en)
Inventor
Il Sang Maeng
Duk Nam Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Innotek Co Ltd
Original Assignee
LG Innotek Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Innotek Co Ltd filed Critical LG Innotek Co Ltd
Priority to JP2013534796A priority Critical patent/JP2013540368A/ja
Publication of WO2012053729A1 publication Critical patent/WO2012053729A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/421—Blind plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0353—Making conductive layer thin, e.g. by etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer

Definitions

  • the present disclosure relates to a printed circuit board and a method for manufacturing the same.
  • PCBs are boards in which a circuit line pattern is printed on an insulating board using a conductive material such as copper, i.e., boards before electric components are mounted. That is, PCBS represent circuit boards in which each of components is decided in position and a circuit pattern connecting the components to each other is printed and fixed on a flat surface to densely mount various electric devices on a flat panel.
  • a term "via” represents “by way of”.
  • a via hole is a processed hole passing through a layer.
  • the layer is punched to define a hole, and copper is plated on a wall of the hole to electrically connect wires to each other.
  • the number of via hole is geometrically increased to provide several millions of hole.
  • it takes a long time to perform a YAG drill/CO 2 drillprocessforprocessingtheholes.
  • the above-described processes may act as neck processes. Therefore, there is a limitation that hole processing costs are significantly increased.
  • Embodiments provide a printed circuit board having a new structure and a method for manufacturing the same.
  • Embodiments also provide a printed circuit board in which a via is formed using a CO 2 drill.
  • a printed circuit board is formed using an inexpensive copper foil having a thickness about 12 ⁇ m. Also, a printed circuit board in which a via is formed using a plating layer as a seed layer and then a via hole is formed using a CO 2 drill to reduce manufacturing costs is prepared.
  • Fig. 1 is a sectional view of a printed circuit board according to an embodiment.
  • Fig. 2 is an enlarged view illustrating an area A of the printed circuit board of Fig. 1.
  • Figs. 3 to 10 are sectional views of a method for manufacturing the printed circuit board of Fig. 1.
  • Figs. 11 to 23 are sectional views of a method for manufacturing a printed circuit board according to another embodiment.
  • a printed circuit board includes: an insulation board on which a plurality of basic circuit patterns are disposed; an insulation layer having a via hole exposing the basic circuit patterns; a conductive via filling the via hole; and a circuit pattern on the insulation layer, wherein a plating layer having a roughness corresponding to that of the insulation layer is disposed between the circuit pattern and the insulation layer.
  • a method for manufacturing a printed circuit board includes: attaching a laminated structure, which has a first thickness, of a metal layer and an insulation layer to an insulation plate on which a basic circuit pattern is formed; performing a full etching process on the metal layer to an electroless plating layer having a second thickness; removing the electroless plating layer and the insulation layer at the same time using a CO2 laser drill to form a via hole so that a portion of the basic circuit pattern is exposed; filling the via hole to form an electroplating layer on the electroless plating layer; and etching the electroless plating layer and the electroplating layer to form an external circuit pattern.
  • a printed circuit board is formed using an inexpensive copper foil having a thickness about 12 ⁇ m. Also, a printed circuit board in which a via is formed using a plating layer as a seed layer and then a via hole is formed using a CO 2 drilltoreducemanufacturingcostsisprepared.
  • Fig. 1 is a sectional view of a printed circuit board according to an embodiment
  • Fig. 2 is an enlarged view illustrating an area A of the printed circuit board of Fig. 1.
  • a printed circuit board (PCB) 100 includes an insulation plate 110 and a basic circuit pattern 120 disposed on the insulation plate 110.
  • the insulation plate 110 may be a support board of the PCB 100 on which a single circuit pattern is disposed.
  • the insulation plate 110 may be an insulation layer having one basic circuit pattern 120 of a PCB having a plurality of stacked structures.
  • a plurality of basic circuit patterns 120 may be sequentially disposed on a top or bottom surface of the insulation plate 110.
  • the insulation plate 110 may include a thermosetting or thermoplastic polymer board, a ceramic board, an organic-inorganic composite material board, or a glass fiber impregnated board.
  • the insulation plate 110 may be formed of an epoxy-based insulating resin.
  • the insulation plate 110 may be formed of a polyimide-based resin.
  • the plurality of basic circuit patterns 120 are disposed on the insulation plate 110.
  • Each of the basic circuit patterns 120 may be formed of a conductive material.
  • the basic circuit pattern 120 may be formed of an alloy containing copper.
  • An insulation layer 130 covering the basic circuit pattern 120 disposed on the insulation plate 110 is disposed.
  • the insulation layer 130 may be formed of an epoxy-based insulating resin having conductivity of about 0.2 W/mk to about 0.4 W/mk.
  • the insulation layer 130 may be formed of a polyimide-based resin having relatively high conductivity.
  • a solid component such as a reinforcing fiber, a glass fiber, or a filter may be impregnated into the resin to form a prepreg, and then the prepreg may be cured to form the insulation layer 130.
  • the insulation layer 130 has a via hole 131 for exposing the basic circuit pattern 120.
  • the via hole 131 is filled with a conductive via 151 connecting the lower basic circuit pattern 120 to the circuit pattern disposed on the insulation layer 130.
  • the via hole 131 may be formed using a laser.
  • the via hole 131 may have a circular or square shape in section according to its design.
  • the via hole 131 may be inclined at a predetermined angle with respect to the insulation plate 110. Alternatively, the via hole 131 may be vertically disposed with respect to the insulation plate 110.
  • a circuit pattern 150 is disposed on the insulation layer 130.
  • the circuit pattern 150 is a plating layer formed by performing an electroplating process using the lower plating layer 140 as a seed.
  • the circuit pattern 150 may be formed of an alloy containing copper, gold, silver, platinum, palladium, or nickel.
  • the conductive via 151 in which the via hole 131 is filled is disposed in the via hole 131 of the insulation layer 130.
  • the via hole 131 may be filled onto the basic circuit pattern 120 and plated to expand the conductive via 151 on a top surface of the insulation layer 130.
  • the lower plating layer 140 is included in an area which the conductive via 151 is expanded to the top surface of the insulation layer 130.
  • the insulation layer 130 has a predetermined roughness on the top surface thereof. This is done because the insulation layer 130 is a resin layer formed by removing the copper foil from a copper clad laminate (CCL). That is, when the copper foil is removed or cured, the roughness may be formed on the top surface of the insulation layer 130.
  • CCL copper clad laminate
  • the lower plating layer 140 may be formed of an alloy containing at least one of copper, molybdenum, chrome, nickel, and silver.
  • the lower plating layer 140 may be formed of an alloy containing copper.
  • the lower plating layer 140 has a roughness disposed along the roughness of the insulation layer 130 and may be densely plated.
  • the lower plating layer 140 may have a thickness of about 0.5 ⁇ m to about 2 ⁇ m, preferably, a thickness of about 1 ⁇ m.
  • the lower plating layer 140 may be plated along the roughness of the insulation layer 130.
  • the seed layer may have a thin thickness and be dense to realize a fine pattern.
  • a basic circuit pattern 120 is formed on an insulation plate 110.
  • a copper foil having a CCL may be patterned to form the insulation plate 110 and the basic circuit pattern 120.
  • a prepreg formed on the CCL may be cured to form the insulation plate 110.
  • the prepreg and the CCL that is a stacked structure of the copper foil 135 are stacked on the insulation plate 110 having the basic circuit pattern 120. Then, the stacked structure of the prepreg and the CCL may be thermally pressed to cure the prepreg, thereby forming an insulation layer 130.
  • an inexpensive CCL enough to realize the copper film 135 having a thickness h2 of about 12 ⁇ m may be used.
  • a full etching process is performed on the copper foil 135.
  • the insulation layer 130 may have a roughness surface as shown in Fig. 2.
  • an electroless plating process is performed on the insulation layer 130 to form a lower plating layer 140.
  • the lower plating layer 140 may have a thickness less than that h2 of the copper foil 135.
  • the lower plating layer 140 may have a thickness of about 0.5 ⁇ m to about 2 ⁇ m, preferably, about 1 ⁇ m.
  • the electroless plating process may be performed on the insulation layer 130 having a roughness to form the lower plating layer 140 having a roughness corresponding to that of the insulation layer 130.
  • the lower plating layer 140 may be thin and dense.
  • the lower thin film plating layer 140 and the insulation layer 130 may be cut at the same time using a CO 2 laserdrilltoformaviahole131intheinsulationlayer130.
  • the lower plating layer 140 and the insulation layer 130 may be cut at the same time using a laser process, i.e., the inexpensive CO 2 laserdrilltoformtheviahole131,unlikethatametallayerformedontheinsulationlayer130isremovedtoformaholeintheinsulationlayer130accordingtoarelatedart.
  • the via hole 131 is filled to perform an electroplating process using the basic circuit pattern 120 and the lower plating layer 140 as a seed, thereby forming an electroplating layer 155.
  • a desmear process for removing a smear formed on an inner wall of the via hole 131 may be further performed to remove the remnant resin, thereby securing hole reliability.
  • a photo mask pattern 160 is formed on the electroplating layer 155, and then the electroplating layer 155 is etched to from a circuit pattern 150 and a via 151.
  • the via may be expanded up to a top surface of the insulation layer 130 outside the via hole 131.
  • the lower plating layer 140 may remain in the expanded area.
  • the insulation layer 130 may be formed from the inexpensive CCL, and then the electroplating process may be performed using the thin electroless plating layer as a seed layer to form the circuit pattern 150 and the via 151.
  • two insulation plates 210 having a basic circuit pattern 220 of Fig. 4 are stacked to allow back surfaces of the two insulation plates 210 to face each other with a release film 200 therebetween.
  • the release film 200 is coated on only dummy areas DA of edges of the insulation plates 210 to adhere to the insulation plates 210. Thus, the release film 200 does not adhere to an active area AA.
  • a prepreg and a CCL that is a stacked structure of a copper foil 235 are stacked on the insulation plates 210. Then, the stacked structure of the prepreg and the CCL is thermally pressed to cure the prepreg, thereby forming an insulation layer 230.
  • an inexpensive CCL enough to realize the copper film 235 having a thickness of about 12 ⁇ m may be used.
  • the insulation layer 230 may have a roughness surface as shown in Fig. 2.
  • the lower plating layer 245 has a thickness less than that of the copper foil 235.
  • the lower plating layer 245 may have a thickness of about 0.5 ⁇ m to about 2 ⁇ m, preferably, about 1 ⁇ m.
  • the electroless plating process may be performed on the insulation layer 230 having a roughness to form the lower plating layer 245 having a roughness corresponding to that of the insulation layer 230.
  • the lower plating layer 245 and the insulation layer 230 are cut at the same time using a CO 2 laserdrilltoformaviahole231intheinsulationlayer230.
  • the via hole 231 is filled to perform an electroplating process using the basic circuit pattern 220 as a seed, thereby forming an electroplating layer 255 as shown in Fig. 16.
  • a desmear process for removing a smear formed on an inner wall of the via hole 231 may be further performed to remove the remnant resin, thereby securing hole reliability.
  • a photo mask pattern is formed on the electroplating layer 255, and then the electroplating layer 255 is etched to from a circuit pattern 250 and a via 251.
  • the via may be expanded up to a top surface of the insulation layer 230 outside the via hole 231.
  • the lower plating layer 245 may remain in the expanded area.
  • the insulation layer 230 may be formed from the inexpensive CCL, and then the electroplating process may be performed using the thin electroless plating layer 255 as a seed layer to form the circuit pattern 250 and the via 251.
  • the CCL including the copper foil 265 having a thickness of about 12 ⁇ m is stacked on both circuit patterns and thermally pressed to form an upper insulation layer 160, thereby separating the dummy areas DA from the active area AA.
  • the release film 200 adhering to the dummy areas DA is separated from the insulation plates 210 to form two stacked structures.
  • the full etching process is performed to remove the copper foil 265 having the thickness of about 12 ⁇ m.
  • the electroless plating process is performed on a thin film having a thickness of about 1 ⁇ m to form a seed layer 275.
  • the conductive via 251 formed on the insulation layer 230 may be exposed through the upper via hole 261. Thereafter, as shown in Fig. 22, an electroplating process is performed using the conductive via 251 and the seed layer formed on the upper insulation layer 260 as seeds to form a plating layer 285. Then, as shown in Fig. 23, an upper via 281 and an upper circuit pattern 280 are formed.
  • the via is formed in two stages in Figs. 11 to 23, the same process may be repeatedly performed to form the via having a plurality of stages.
  • the two insulation plates 210 may adhere to improve process yield. Also, since the via hole is formed using the CO 2 laserdrillingprocess,themanufacturingprocessmaybeeconomical.
  • the manufacturing process may be economical.
  • the seed layer for forming the via may be formed as the plating to reduce a thickness of the seed layer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

La présente invention a trait à une carte de circuit imprimé et à son procédé de fabrication. La carte de circuit imprimé inclut une carte isolante sur laquelle une pluralité de tracés de circuit de base est disposée, une couche isolante qui est dotée d'un trou d'interconnexion exposant les tracés de circuit de base, un trou de raccordement conducteur qui remplit le trou d'interconnexion, et un tracé de circuit sur la couche isolante. Une couche de revêtement métallique qui est dotée d'une rugosité correspondant à celle de la couche isolante est disposée entre le tracé de circuit et la couche isolante. De la sorte, dans la mesure où la carte de circuit imprimé est formée à l'aide d'un CCL incluant un film de cuivre peu coûteux qui est doté d'une épaisseur d'environ 12 µm et où un processus de perçage de laser à CO2 est effectué une fois de manière à former le trou d'interconnexion, le processus de fabrication peut être économique.
PCT/KR2011/004873 2010-10-20 2011-07-04 Carte de circuit imprimé et son procédé de fabrication Ceased WO2012053729A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013534796A JP2013540368A (ja) 2010-10-20 2011-07-04 印刷回路基板及びその製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2010-0102395 2010-10-20
KR1020100102395A KR20120040892A (ko) 2010-10-20 2010-10-20 인쇄회로기판 및 그의 제조 방법

Publications (1)

Publication Number Publication Date
WO2012053729A1 true WO2012053729A1 (fr) 2012-04-26

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2011/004873 Ceased WO2012053729A1 (fr) 2010-10-20 2011-07-04 Carte de circuit imprimé et son procédé de fabrication

Country Status (4)

Country Link
JP (1) JP2013540368A (fr)
KR (1) KR20120040892A (fr)
TW (1) TW201230901A (fr)
WO (1) WO2012053729A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230300983A1 (en) * 2020-07-29 2023-09-21 Kyocera Corporation Circuit substrate and method for manufacturing the same

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CN104662692B (zh) * 2012-09-18 2018-07-06 应用材料公司 金属上方的sin层上的胶带辅助单步剥除
JP6322885B2 (ja) * 2012-11-01 2018-05-16 味の素株式会社 プリント配線板の製造方法
CN104661449B (zh) * 2015-02-16 2019-01-01 珠海元盛电子科技股份有限公司 一种基于激光活化技术的孔金属化方法
KR102326505B1 (ko) * 2015-08-19 2021-11-16 엘지이노텍 주식회사 인쇄회로기판 및 그의 제조 방법
KR20230048958A (ko) * 2021-10-05 2023-04-12 엘지이노텍 주식회사 회로기판 및 이를 포함하는 패키지 기판
CN116013898A (zh) 2021-10-22 2023-04-25 群创光电股份有限公司 电子装置及电子装置的制造方法
JP2023077787A (ja) * 2021-11-25 2023-06-06 日東電工株式会社 配線回路基板およびその製造方法

Citations (3)

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Publication number Priority date Publication date Assignee Title
KR20060061953A (ko) * 2004-12-02 2006-06-09 삼성전기주식회사 얇은 코어층을 갖는 인쇄회로기판 제조방법
KR20070021631A (ko) * 2005-08-19 2007-02-23 주식회사 두산 다층 인쇄 회로 기판 및 그 제조 방법
KR20100028306A (ko) * 2008-09-04 2010-03-12 삼성전기주식회사 인쇄회로기판 및 그 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060061953A (ko) * 2004-12-02 2006-06-09 삼성전기주식회사 얇은 코어층을 갖는 인쇄회로기판 제조방법
KR20070021631A (ko) * 2005-08-19 2007-02-23 주식회사 두산 다층 인쇄 회로 기판 및 그 제조 방법
KR20100028306A (ko) * 2008-09-04 2010-03-12 삼성전기주식회사 인쇄회로기판 및 그 제조 방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230300983A1 (en) * 2020-07-29 2023-09-21 Kyocera Corporation Circuit substrate and method for manufacturing the same
US12446153B2 (en) * 2020-07-29 2025-10-14 Kyocera Corporation Circuit substrate and method for manufacturing the same

Also Published As

Publication number Publication date
JP2013540368A (ja) 2013-10-31
KR20120040892A (ko) 2012-04-30
TW201230901A (en) 2012-07-16

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