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WO2011118685A1 - Cellule solaire et son procédé de production - Google Patents

Cellule solaire et son procédé de production Download PDF

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Publication number
WO2011118685A1
WO2011118685A1 PCT/JP2011/057115 JP2011057115W WO2011118685A1 WO 2011118685 A1 WO2011118685 A1 WO 2011118685A1 JP 2011057115 W JP2011057115 W JP 2011057115W WO 2011118685 A1 WO2011118685 A1 WO 2011118685A1
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Prior art keywords
solar cell
layer
semiconductor
semiconductor layer
insulating layer
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English (en)
Japanese (ja)
Inventor
三島　孝博
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
    • H10F77/147—Shapes of bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H10F10/166—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a solar cell manufacturing method and a solar cell.
  • the present invention relates to a method for manufacturing a back junction solar cell and a solar cell.
  • back junction solar cells in which a semiconductor junction is formed on the back surface side of the solar cell and no semiconductor junction is formed on the light receiving surface side (for example, Patent Documents 1 and 2 listed below and Non-patent document 1).
  • this back junction solar cell it is not necessary to provide an electrode on the light receiving surface side. For this reason, in the back junction solar cell, the light receiving efficiency can be increased. Therefore, higher power generation efficiency can be realized.
  • the solar cell can be connected by the wiring material only on the back surface side. For this reason, a wide wiring material can be used. Therefore, the voltage drop by wiring a plurality of solar cells using the wiring material can be suppressed.
  • Non-Patent Document 1 describes that the insulating layer is composed of a silicon oxide layer or an alumina layer.
  • the insulating layer that insulates the n-type semiconductor layer and the p-type semiconductor layer is required to have high insulating properties. For this reason, the insulating layer that insulates the n-type semiconductor layer from the p-type semiconductor layer is composed of an oxide layer such as a silicon oxide layer or an alumina layer having high insulating properties as described in Non-Patent Document 1 above. It was considered preferable to do.
  • the present inventor has found that when an oxide layer such as a silicon oxide layer or an alumina layer is used as an insulating layer that insulates the n-type semiconductor layer and the p-type semiconductor layer, photoelectric conversion of the solar cell is performed. We have found that the efficiency may be low.
  • This invention is made
  • the present inventor has found that when an oxide layer is used as an insulating layer that insulates an n-type semiconductor layer and a p-type semiconductor layer, the photoelectric conversion efficiency is lowered on the oxide layer. In the step of cleaning the surface of the semiconductor substrate before forming the layer, it has been found that impurities are generated from the oxide layer and the surface of the semiconductor substrate is contaminated. As a result, the present inventor came to make the present invention.
  • a method for manufacturing a solar cell according to the present invention includes a step of preparing a semiconductor substrate having first and second main surfaces, a first junction forming step, an insulating layer forming step, a cleaning step, 2 joining formation processes.
  • the first junction forming step is located on a part of the first main surface of the semiconductor substrate, and includes a first semiconductor layer made of one of a p-type semiconductor and an n-type semiconductor, and the first semiconductor. Forming a first electrode located on the layer.
  • the insulating layer forming step covers the first semiconductor layer and the first electrode, while exposing at least a part of a portion of the first main surface that is not covered by the first semiconductor layer. Is a step of forming.
  • the cleaning step is a step of cleaning the first main surface of the semiconductor substrate on which the insulating layer is formed.
  • the second bonding formation step is located on the exposed portion of the first main surface of the semiconductor substrate after the cleaning step, and a second semiconductor layer made of the other of the p-type semiconductor and the n-type semiconductor, And forming a second electrode located on the second semiconductor layer.
  • the insulating layer forming step is a step of forming the insulating layer so that at least the outermost layer of the insulating layer is an amorphous silicon layer containing no hydrogen.
  • the “amorphous silicon layer” is a layer made of amorphous silicon.
  • amorphous silicon includes microcrystalline silicon.
  • Microcrystalline silicon refers to silicon in which the average particle size of silicon crystals precipitated in amorphous silicon is 1 nm to 50 nm or less.
  • an amorphous silicon layer by a vapor deposition method in the insulating layer forming step.
  • the vapor deposition method include an electron beam vapor deposition method, a resistance heating vapor deposition method, and a sputtering method.
  • the insulating layer may be an amorphous silicon layer.
  • the portion other than the outermost layer of the insulating layer may be made of at least one of silicon oxide and silicon nitride.
  • the cleaning step preferably includes a step of cleaning with hydrofluoric acid.
  • a third semiconductor layer made of an intrinsic semiconductor is further formed between the semiconductor substrate and the first semiconductor layer, and in the second junction forming step, the semiconductor substrate and the first semiconductor layer are formed. It is preferable to further form a fourth semiconductor layer made of an intrinsic semiconductor between the two semiconductor layers.
  • an “intrinsic semiconductor” refers to a semiconductor formed so as not to substantially contain doping impurities.
  • the second semiconductor layer and the second electrode so as to cover the first main surface in the second bonding formation step.
  • the solar cell according to the present invention includes a semiconductor substrate, a first semiconductor layer, a first electrode, an insulating layer, a second semiconductor layer, and a second electrode.
  • the semiconductor substrate has first and second main surfaces.
  • the first semiconductor layer is formed on a portion of the first main surface of the semiconductor substrate.
  • the first semiconductor layer is made of one of a p-type semiconductor and an n-type semiconductor.
  • the first electrode is formed on the first semiconductor layer.
  • the insulating layer covers the first semiconductor layer and the first electrode, and is formed so as to expose at least a part of the portion of the first main surface that is not covered by the first semiconductor layer. Yes.
  • the second semiconductor layer is formed on the exposed portion of the first main surface of the semiconductor substrate.
  • the second semiconductor layer is made of the other of the p-type semiconductor and the n-type semiconductor.
  • the second electrode is formed on the second semiconductor layer.
  • At least the outermost layer of the insulating layer is composed of an amorphous silicon layer formed so as not to contain hydrogen.
  • a solar cell manufacturing method with high photoelectric conversion efficiency and a solar cell with high photoelectric conversion efficiency are provided.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. It is a flowchart showing the manufacturing process of the solar cell in 1st Embodiment. It is a schematic sectional drawing showing the film-forming process of the insulating film in 1st Embodiment. It is a schematic sectional drawing showing the patterning process of the insulating film in 1st Embodiment. It is schematic-drawing sectional drawing of the solar cell which concerns on 2nd Embodiment.
  • the solar cell 1 shown in FIG. 1 is merely an example.
  • the present invention is not limited to the solar cell 1 at all.
  • FIG. 1 is a schematic plan view of the back surface of the solar cell according to the first embodiment.
  • FIG. 2 is a schematic cross-sectional view of the solar cell according to the first embodiment.
  • the solar cell 1 is a solar cell having a BSF (Back Surface Field) structure and a HIT (registered trademark) structure.
  • the solar cell 1 may be used as a solar cell module in which a plurality of solar cells 1 are connected by a wiring material. .
  • the solar cell 1 includes a semiconductor substrate 10 made of a semiconductor material.
  • the semiconductor substrate 10 has a light receiving surface 10a as a second main surface and a back surface 10b as a first main surface.
  • the semiconductor substrate 10 generates carriers by receiving the light 11 on the light receiving surface 10a.
  • the carriers are holes and electrons that are generated when light is absorbed by the semiconductor substrate 10.
  • the semiconductor substrate 10 has n-type or p-type conductivity.
  • the semiconductor substrate 10 is made of, for example, a crystalline semiconductor material or a compound semiconductor material.
  • Specific examples of the compound semiconductor material include GaAs and InP.
  • Specific examples of the crystalline semiconductor material include single crystal silicon and crystalline silicon such as polycrystalline silicon.
  • the semiconductor substrate 10 is made of n-type crystalline silicon.
  • An i-type amorphous semiconductor layer 12 made of an intrinsic amorphous semiconductor (hereinafter, the intrinsic semiconductor is referred to as an “i-type semiconductor”) is formed on the light receiving surface 10 a of the semiconductor substrate 10.
  • an n-type amorphous semiconductor layer 13 having the same conductivity type as that of the semiconductor substrate 10 is formed on the i-type amorphous semiconductor layer 12.
  • a reflection suppression film (not shown) that suppresses reflection of light may be formed on the n-type amorphous semiconductor layer 13.
  • a plurality of IP stacked bodies 14 are formed on a part of the back surface 10b of the semiconductor substrate 10 as shown in FIG. Specifically, the plurality of IP laminates 14 are formed in stripes on the back surface 10b in parallel with each other at a predetermined interval.
  • each of the plurality of IP stacked bodies 14 includes a stacked body of an i-type amorphous semiconductor layer 15 and a p-type amorphous semiconductor layer 16 as a first semiconductor layer. Yes.
  • the plurality of i-type amorphous semiconductor layers 15 are formed in stripes on the back surface 10b of the semiconductor substrate 10 in parallel with each other.
  • the i-type amorphous semiconductor layer 15 is heterojunction with the semiconductor substrate 10.
  • the i-type amorphous semiconductor layer 15 is a layer made of an amorphous intrinsic semiconductor. Specifically, in this embodiment, the i-type amorphous semiconductor layer 15 is made of i-type amorphous silicon containing hydrogen.
  • the p-type amorphous semiconductor layer 16 is formed on each i-type amorphous semiconductor layer 15.
  • the p-type amorphous semiconductor layer 16 is formed in contact with the i-type amorphous semiconductor layer 15.
  • the p-type amorphous semiconductor layer 16 is an amorphous semiconductor layer to which a p-type dopant is added and has p-type conductivity.
  • the p-type amorphous semiconductor layer 16 is made of p-type amorphous silicon containing hydrogen.
  • the i (thickness of about several to 250 inches) i between the crystalline semiconductor substrate 10 and the p-type amorphous semiconductor layer 16 does not substantially contribute to power generation.
  • a HIT structure in which the type amorphous semiconductor layer 15 is provided is configured.
  • a p-side electrode 17 serving as a first electrode is formed on each of the plurality of p-type amorphous semiconductor layers 16.
  • the p-side electrode 17 is a collecting electrode that collects holes through the p-type amorphous semiconductor layer 16.
  • the p-side electrode 17 is not particularly limited as long as it can collect holes.
  • the p-side electrode 17 is composed of a stacked body of a TCO (Transparent Conducting Oxide) layer 17a and a metal layer 17b.
  • the TCO layer 17 a is formed on the p-type amorphous semiconductor layer 16.
  • the TCO layer 17a is made of, for example, a transparent conductive oxide (TCO) such as ITO (Indium Tin Oxide).
  • the metal layer 17b is made of a metal such as silver or aluminum or an alloy containing a metal such as silver or aluminum.
  • a metal such as silver or aluminum or an alloy containing a metal such as silver or aluminum.
  • the TCO layer 17a is made of ITO and the metal layer 17b is made of aluminum will be described.
  • An insulating layer 18 is formed on the p-side electrode 17.
  • the insulating layer 18 covers the p-side electrode 17, the IP stacked body 14, and a part of the back surface 10 b of the semiconductor substrate 10.
  • a part of the back surface 10b of the semiconductor substrate 10 is not covered with the insulating layer 18 and is exposed.
  • a BSF (Back Surface Field) junction described later is formed on the exposed portion 10b1 exposed from the insulating layer 18 on the back surface 10b.
  • the configuration of the insulating layer 18 will be described in detail later.
  • An IN laminate 19 is formed on the exposed portion 10b1 of the back surface 10b.
  • the IN stacked body 19 is formed on the entire surface of the back surface 10 b including the surface of the IP stacked body 14.
  • the IN stacked body 19 includes an i-type amorphous semiconductor layer 20 and an n-type amorphous semiconductor layer 21 as a second semiconductor layer.
  • the i-type amorphous semiconductor layer 20 is formed so as to cover substantially the entire back surface 10b including the exposed portion 10b1.
  • the i-type amorphous semiconductor layer 20 is heterojunction with the semiconductor substrate 10. Similar to the i-type amorphous semiconductor layer 15, the i-type amorphous semiconductor layer 20 is a layer made of an amorphous intrinsic semiconductor. Specifically, in this embodiment, the i-type amorphous semiconductor layer 20 is made of i-type amorphous silicon containing hydrogen.
  • the n-type amorphous semiconductor layer 21 is formed in a planar shape so as to cover the i-type amorphous semiconductor layer 20.
  • the n-type amorphous semiconductor layer 21 is formed in contact with the i-type amorphous semiconductor layer 20.
  • the n-type amorphous semiconductor layer 21 is an amorphous semiconductor layer to which an n-type dopant is added and has n-type conductivity.
  • the n-type amorphous semiconductor layer 21 is made of n-type amorphous silicon containing hydrogen.
  • an n-side electrode 22 as a second electrode is formed in a planar shape.
  • the n-side electrode 22 is a collecting electrode that collects electrons via the n-type amorphous semiconductor layer 21.
  • a BSF structure in which the i-type amorphous semiconductor layer 20 and the n-type amorphous semiconductor layer 21 are provided between the semiconductor substrate 10 and the n-side electrode 22 is configured. Yes. For this reason, recombination of minority carriers on the back surface 10b can be effectively suppressed.
  • the n-side electrode 22 is not particularly limited as long as it can collect electrons.
  • the n-side electrode 22 includes a TCO layer 22a and a metal layer 22b.
  • the TCO layer 22a is made of a transparent conductive oxide (TCO) such as ITO, for example, similarly to the TCO layer 17a.
  • the metal layer 22b is made of a metal such as silver or aluminum or an alloy containing a metal such as silver or aluminum.
  • TCO transparent conductive oxide
  • the metal layer 22b is made of a metal such as silver or aluminum or an alloy containing a metal such as silver or aluminum.
  • the insulating layer 18 includes a first insulating layer 18a and a second insulating layer 18b.
  • the first insulating layer 18 a is formed so as to cover the p-side electrode 17, the IP stacked body 14, and a part of the back surface 10 b of the semiconductor substrate 10.
  • the second insulating layer 18b is formed on the first insulating layer 18a. Substantially the entire portion excluding the end portion of the first insulating layer 18a is covered with the second insulating layer 18b.
  • the second insulating layer 18b constituting the outermost layer of the insulating layer 18 includes a p-type amorphous semiconductor layer 16 as a first semiconductor layer and an n-type amorphous semiconductor layer as a second semiconductor layer. And an amorphous semiconductor having an electric resistance higher than that of each of the two.
  • the second insulating layer 18b is made of morphous silicon formed without adding hydrogen.
  • the material of the 1st insulating layer 18a located inside the 2nd insulating layer 18b is not specifically limited as long as it has insulation.
  • the first insulating layer 18a is, for example, oxides typified by silicon oxide such as SiO 2, nitride typified by silicon nitride, such as SiN, carbides typified by silicon carbide, such as SiC, a high-resistance crystal It can be formed of silicon such as silicon or amorphous silicon, or an organic material having an insulating property.
  • the organic material having an insulating property include imide resins such as polyimide, fluororesins such as Teflon (registered trademark), polycarbonate, and liquid crystal polymer.
  • silicon oxide and silicon nitride are preferable as the material of the first insulating layer 18a.
  • the thickness of the insulating layer 18 is not particularly limited as long as it can sufficiently insulate the p-type amorphous semiconductor layer 16 and the n-type amorphous semiconductor layer 21, and depends on the material of the insulating layer 18 and the like. Can be set as appropriate.
  • the thickness of the insulating layer 18 is preferably about 20 nm to 100 ⁇ m, for example, and more preferably 50 nm to 5 ⁇ m.
  • the thickness of the first insulating layer 18a is preferably about 20 nm to 100 ⁇ m, for example, and more preferably 50 nm to 5 ⁇ m.
  • the thickness of the second insulating layer 18b is preferably about 10 nm to 1000 nm, for example, and more preferably 20 nm to 200 nm.
  • FIG. 3 is a flowchart showing the manufacturing process of the solar cell 1.
  • 4 and 5 are schematic cross-sectional views for explaining the manufacturing process of the solar cell 1. Next, an example of a method for manufacturing the solar cell 1 according to this embodiment will be described with reference to FIGS.
  • a semiconductor substrate 10 is prepared. Specifically, in the present embodiment, a semiconductor substrate 10 made of n-type crystalline silicon is prepared in which an i-type amorphous semiconductor layer 12 and an n-type amorphous semiconductor layer 13 are formed on the light receiving surface 10a side. .
  • the i-type amorphous semiconductor layer 12 and the n-type amorphous semiconductor layer 13 can be formed by, for example, a CVD (Chemical Vapor Deposition) method such as a plasma CVD method.
  • CVD Chemical Vapor Deposition
  • step S2 a first junction forming process for forming a HIT structure is performed.
  • an i-type amorphous semiconductor layer 15, a p-type amorphous semiconductor layer 16 as a first semiconductor layer, and a p-side electrode 17 as a first electrode are formed.
  • the i-type amorphous semiconductor layer 15 is formed in a state where a metal mask (not shown) is disposed on the back surface 10b of the semiconductor substrate 10.
  • step S2-2 the p-type amorphous semiconductor layer 16 is formed on the metal mask.
  • step S2-3, the p-side electrode 17 is formed on the metal mask.
  • a TCO layer 17a made of ITO is formed.
  • a metal layer 17b made of aluminum is formed.
  • the i-type amorphous semiconductor layer 15 and the p-type amorphous semiconductor layer 16 can be formed by, for example, a CVD method.
  • the TCO layer 17a can be formed by, for example, a sputtering method.
  • the metal layer 17b can be formed by, for example, a sputtering method or a vacuum evaporation method.
  • the insulating layer 18 covers the p-type amorphous semiconductor layer 16 and the p-side electrode 17, while at least a portion of the back surface 10b not covered by the p-type amorphous semiconductor layer 16 is covered. A portion is exposed (insulating layer forming step). Further, in the insulating layer forming step of step S3, the insulating layer 18 is formed so that at least the outermost layer of the insulating layer 18 is an amorphous silicon layer formed so as not to contain hydrogen.
  • the insulating film 23a for forming the first insulating layer 18a is formed in a planar shape on the back surface 10b.
  • the formation method of the insulating film 23a can be appropriately selected depending on the type of the insulating film 23a.
  • the insulating film 23a is silicon oxide, it can be formed by a sputtering method or the like.
  • an amorphous silicon film 23b for forming the second insulating layer 18b is formed on the insulating film 23a.
  • the amorphous silicon film 23b is preferably formed in an atmosphere not containing hydrogen by an evaporation method such as an electron beam evaporation method, a resistance heating evaporation method, or a sputtering method. This is because the amorphous silicon film 23b which is relatively thick and does not contain hydrogen can be formed in a short time.
  • step S3-3 the insulating film 23a and the amorphous silicon film 23b are patterned to form the insulating layer 18 composed of the first and second insulating layers 18a and 18b as shown in FIG. be able to.
  • the patterning of the insulating film 23a and the amorphous silicon film 23b can be performed by, for example, chemical etching using a resist film. More specifically, for example, a resist film having a shape corresponding to the shape to be patterned is disposed on the amorphous silicon film 23b, etched from above using an etchant such as hydrofluoric acid, and finally hydroxylated. By removing the resist using a sodium aqueous solution or the like, the insulating film 23a and the amorphous silicon film 23b can be patterned.
  • step S4 shown in FIG. 3 a cleaning process for cleaning the back surface 10b of the semiconductor substrate 10 on which the insulating layer 18 is formed is performed. It is preferable that the cleaning process of step S4 includes a process of cleaning with hydrofluoric acid. By doing so, the oxide film etc. on the back surface 10b of the semiconductor substrate 10 can be effectively removed.
  • step S4 first, cleaning by the RCA cleaning method is performed, and then cleaning by hydrofluoric acid is performed.
  • the RCA cleaning method is a kind of chemical cleaning method, and after cleaning with an alkaline aqueous solution containing hydrogen peroxide and ammonium hydroxide (SC1 cleaning), an acidic aqueous solution containing hydrochloric acid and hydrogen peroxide.
  • SC1 cleaning alkaline aqueous solution containing hydrogen peroxide and ammonium hydroxide
  • This is a cleaning method that performs cleaning by SC2 (SC2 cleaning).
  • SC1 cleaning organic contamination is removed
  • SC2 cleaning cations such as alkali ions, Al 3+ and Fe 3+ are removed.
  • step S5 a second bonding formation process for forming a BSF structure is performed.
  • an i-type amorphous semiconductor layer 20, an n-type amorphous semiconductor layer 21 as a second semiconductor layer, and an n-side electrode 22 as a second electrode are formed.
  • the i-type amorphous semiconductor layer 20 is formed in a planar shape so as to cover the back surface 10b by a CVD method or the like.
  • step S5-2 the n-type amorphous semiconductor layer 21 is formed in a planar shape so as to cover the back surface 10b by a CVD method or the like.
  • step S5-3 the n-side electrode 22 is formed.
  • the TCO layer 22a made of ITO is formed by sputtering or the like.
  • a metal layer 22b made of silver is formed by a sputtering method, a vacuum evaporation method, or the like.
  • Non-Patent Document 1 when the insulating layer is formed of an oxide layer, impurities generated from the insulating layer in the cleaning process adhere to the back surface of the semiconductor substrate. Therefore, since the back surface of the semiconductor substrate is contaminated, the i-type amorphous semiconductor layer 20 and the n-type amorphous semiconductor layer 21 cannot be suitably formed. As a result, there arises a problem that the photoelectric conversion efficiency of the obtained solar cell is lowered. In the case where the insulating film is formed of a silicon oxide layer, since the insulating layer is dissolved in hydrofluoric acid, it is difficult to clean the semiconductor substrate using hydrofluoric acid, which greatly restricts process conditions.
  • the second insulating layer 18b constituting the outermost layer of the insulating layer 18 is composed of an amorphous silicon layer that does not contain hydrogen and is formed in an atmosphere that does not contain hydrogen. . Therefore, in the cleaning process of step S4 shown in FIG. 3, a substance that contaminates the back surface 10b of the semiconductor substrate 10 from the insulating layer 18 is unlikely to be generated. Further, the amorphous silicon layer is difficult to dissolve in hydrofluoric acid. For this reason, in this embodiment, the washing
  • the cleanliness of the back surface 10b of the semiconductor substrate 10 can be sufficiently increased in the cleaning process. Therefore, the i-type amorphous semiconductor layer 20 and the n-type amorphous semiconductor layer 21 can be suitably formed. As a result, the solar cell 1 with high photoelectric conversion efficiency can be manufactured.
  • the following processing may be further performed in order to extract current from the p-side electrode 17 embedded in the insulating layer 18 to the outside. That is, for the portion from which current is taken out from the p-side electrode 17, the IN stacked body 19 and the n-side electrode 22 (both see FIG. 6) are not formed using a metal mask or the like. It may be.
  • the insulating layer (amorphous silicon layer, silicon nitride layer containing hydrogen, etc.) on the p-side electrode 17 from which current is taken out is protected with a resist film except for the processed portion. And then removed using sodium hydroxide and hydrogen fluoride. Through these steps, a part of the p-side electrode 17 covered with the insulating film can be exposed and current can be taken out to the outside.
  • the first insulating layer 18a is not completely covered by the second insulating layer 18b. A part of the first insulating layer 18a is exposed from the second insulating layer 18b. However, since most of the first insulating layer 18a is covered with the second insulating layer 18b, contaminants are hardly generated. Therefore, the solar cell 1 with high photoelectric conversion efficiency can be manufactured.
  • the first insulating layer 18a is formed of, for example, a silicon oxide layer, a silicon nitride layer, or the like, even if an eluate is generated from the first insulating layer 18a, for example.
  • the insulating layer 18a is made of an organic material or the like, there is little decrease in bonding characteristics due to the eluate. Therefore, the exposed portion 10b1 of the back surface 10b is not easily contaminated. Therefore, the solar cell 1 with higher photoelectric conversion efficiency can be manufactured.
  • the first insulating layer 18a is preferably completely covered with the second insulating layer 18b.
  • the first insulating layer 18a is completely covered with the second insulating layer 18b, for example, after the insulating film 23a is patterned, the amorphous silicon film 23b is formed and patterned. A method is mentioned.
  • the i-type amorphous semiconductor layer 15, the p-type amorphous semiconductor layer 16, and the p-side electrode 17 are covered with the insulating layer 18, the i-type amorphous semiconductor layer 20, n
  • the type amorphous semiconductor layer 21 and the n-side electrode 22 can be formed in a planar shape and do not need to be patterned. Therefore, the solar cell 1 can be easily manufactured.
  • FIG. 1 is referred to in common with the first embodiment.
  • FIG. 6 is a schematic cross-sectional view of a solar cell according to the second embodiment.
  • the solar cell 2 of the present embodiment differs from the solar cell 1 of the first embodiment only in the configuration of the insulating layer 18.
  • the solar cell 2 of the present embodiment includes the semiconductor substrate 10 having the light receiving surface 10a and the back surface 10b.
  • a stacked body of an i-type amorphous semiconductor layer 15 and a p-type amorphous semiconductor layer 16 as a first semiconductor layer is formed on a part of the back surface 10 b of the semiconductor substrate 10.
  • a p-side electrode 17 as a first electrode is formed on the p-type amorphous semiconductor layer 16.
  • the insulating layer 18 covers the p-type amorphous semiconductor layer 16 and the p-side electrode 17, while exposing at least a part of the portion of the back surface 10b that is not covered by the p-type amorphous semiconductor layer 16. Is formed.
  • the body is formed.
  • An n-side electrode 22 as a second electrode is formed on the n-type amorphous semiconductor layer 21.
  • the insulating layer 18 is composed of an amorphous silicon layer formed so as not to contain hydrogen.
  • the solar cell 2 of the present embodiment can be manufactured, for example, by the same procedure as Step S1 to Step S5 described in the first embodiment except for Step S3 shown in FIG.
  • the description of step S1, step S2, and steps S4 to S5 uses the description in the first embodiment, and only step S3 in this embodiment will be described.
  • step S3 first, an amorphous silicon film for forming the insulating layer 18 is formed on the back surface 10b in an atmosphere not containing hydrogen by an evaporation method such as an electron beam evaporation method or a resistance heating evaporation method. Form. Then, by patterning the amorphous silicon film by chemical etching, the insulating layer 18 made of an amorphous silicon layer formed so as not to contain hydrogen can be formed.
  • an evaporation method such as an electron beam evaporation method or a resistance heating evaporation method.
  • the insulating layer 18 is composed only of an amorphous silicon layer formed so as not to contain hydrogen, and the insulating layer 18 contains a substance that causes contamination of the back surface 10b of the semiconductor substrate 10 such as silicon oxide or alumina. Not. For this reason, it can suppress more effectively that the back surface 10b of the semiconductor substrate 10 is contaminated. Therefore, the solar cell 2 with higher photoelectric conversion efficiency can be manufactured.
  • the thickness of the insulating layer 18 is preferably about 20 nm to 2 ⁇ m, for example. More preferably, the thickness is 20 nm to 500 nm.
  • the first semiconductor layer covered with the insulating layer 18 is a p-type amorphous semiconductor layer
  • the second semiconductor layer positioned on the insulating layer 18 is an n-type amorphous semiconductor layer.
  • the example which is a quality semiconductor layer was demonstrated.
  • the present invention is not limited to this configuration.
  • the first semiconductor layer covered with the insulating layer 18 is an n-type amorphous semiconductor layer
  • the second semiconductor layer located on the insulating layer 18 is a p-type amorphous semiconductor layer. Also good.
  • the p-type amorphous semiconductor layer 16 as the first semiconductor layer, the n-type amorphous semiconductor layer 21 as the second semiconductor layer, and the semiconductor substrate 10 are respectively provided.
  • the case where the i-type amorphous semiconductor layers 15 and 20 are formed has been described.
  • the present invention is not limited to this configuration.
  • at least one of the i-type amorphous semiconductor layers 15 and 20 may not be provided.
  • the solar cell according to the present invention may not be provided with the i-type amorphous semiconductor layer 15 and does not have a HIT structure.
  • each of the p-side electrode 17 as the first electrode and the n-side electrode 22 as the second electrode is formed of a laminate of the TCO film and the metal film.
  • An example was described.
  • the present invention is not limited to this configuration.
  • Each of the first and second electrodes may be composed of, for example, only a TCO film, or may be composed of only a metal film or an alloy film.
  • the first electrode may have, for example, a bus bar and a plurality of fingers connected to the bus bar.
  • the present invention is not limited to this configuration.
  • the insulating layer includes a first insulating layer and a second insulating layer formed on the first insulating layer and formed of an amorphous silicon layer that does not contain hydrogen
  • the first insulating layer may be formed only on the upper surface of the first semiconductor layer.
  • Example 1 has the same configuration as that of the solar cell 1 according to the first embodiment except that the positions of the p-type amorphous semiconductor layer 16 and the n-type amorphous semiconductor layer 21 are switched.
  • the solar cell was prepared as follows.
  • an (100) -oriented n-type crystalline silicon substrate (resistivity: 1 ⁇ m, 25 mm square, thickness: 200 ⁇ m) was prepared.
  • a metal mask is disposed on the n-type crystalline silicon substrate, and an i-type amorphous semiconductor layer made of an i-type amorphous silicon film is formed on a part of the back surface of the n-type crystalline silicon substrate by a CVD method. And an n-type amorphous semiconductor layer made of an n-type amorphous silicon film were formed in a stripe shape. Further, a first electrode made of a laminate of an ITO film having a thickness of 100 nm and an aluminum film having a thickness of 3 ⁇ m was formed by a sputtering method.
  • a silicon oxide film having a thickness of 500 nm is formed on the entire back surface of the n-type crystalline silicon substrate by sputtering, a non-doped amorphous silicon layer not containing hydrogen having a thickness of 100 nm is further deposited by electron beam evaporation. Formed by the method. As a result, an insulating film made of a laminate of a silicon oxide film and a non-doped amorphous silicon layer containing no hydrogen was formed.
  • the insulating film located on the portion where the p-type amorphous semiconductor layer is formed on the back surface of the n-type crystalline silicon substrate was removed by chemical etching using a resist film. Specifically, first, a resist film having a desired shape was placed on an n-type crystalline silicon substrate. Then, the insulating film was etched from above the resist film using hydrofluoric acid. Finally, the insulating film was patterned by removing the resist film using a 1 wt% aqueous sodium hydroxide solution.
  • the back surface of the n-type crystalline silicon substrate was washed with an organic substance using ethanol, then RCA washed, and finally washed with hydrofluoric acid having a concentration of 1% by weight for 1 minute.
  • an i-type amorphous semiconductor layer having a thickness of 10 nm and a p-type amorphous semiconductor layer having a thickness of 10 nm are formed on the entire surface including the exposed portion of the back surface of the n-type crystalline silicon substrate by CVD. Laminated. Then, 10 solar cells according to Example 1 were formed by forming a laminate composed of an ITO film having a thickness of 100 nm and a silver film having a thickness of 20 ⁇ m as the second electrode by using a sputtering method. .
  • Comparative Example 1 instead of forming a stacked body of a silicon oxide film and a non-doped amorphous silicon layer containing no hydrogen as an insulating layer, an aluminum film having a thickness of 600 nm is formed by sputtering, and then anodized. Ten solar cells were produced in the same manner as in Example 1 except that a 100 nm thick alumina layer was formed by the treatment.
  • Example 2 the silicon oxide layer that forms part of the insulating film is formed only on the first electrode so that the side surfaces of the first semiconductor layer and the first electrode are not covered with the silicon oxide layer. Except for this, ten solar cells were prepared in the same manner as in Example 1 above.
  • an amorphous silicon film was formed after patterning by the method described in Example 1 above.
  • Comparative Example 2 the insulating film was composed only of a silicon oxide film having a thickness of 500 nm, and the patterning of the insulating film was performed using a metal mask. Further, ten solar cells were prepared in the same manner as in Example 2 except that RCA cleaning was not performed and cleaning was performed with 1% by mass hydrofluoric acid water for 10 seconds.
  • Examples 1 and 2 had higher photoelectric conversion efficiency than Comparative Examples 1 and 2. Further, in the second embodiment in which the silicon oxide layer is completely covered with an amorphous silicon layer formed so as not to contain hydrogen, the amorphous silicon layer formed so that the silicon oxide layer does not contain hydrogen is used. Thus, the photoelectric conversion efficiency was higher than that of Example 1 that was not completely covered. Moreover, it turned out that the comparative example 1 which uses the alumina for the insulating layer among the comparative examples 1 and 2 has especially a low open circuit voltage, and its joining characteristic is low. Since Comparative Example 2 used only silicon oxide for the insulating film, the cleaning conditions were limited, and the characteristics were inferior to those of Examples 1 and 2.
  • a solar cell having high photoelectric conversion efficiency can be obtained by configuring the outermost layer of the insulating film with an amorphous silicon layer formed so as not to contain hydrogen according to the present invention. It can also be seen that the higher the exposed area of the silicon oxide layer from the amorphous silicon layer, the higher the photoelectric conversion efficiency.

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  • Photovoltaic Devices (AREA)

Abstract

L'invention concerne un procédé de production d'une cellule solaire avec un fort rendement de conversion photoélectrique. Une première couche semi-conductrice (16) présentant une conductivité du type p ou du type n est formée à une position au-dessus d'une partie d'une première surface principale (10b) d'un substrat semi-conducteur (10). Une couche isolante (18) est formée au-dessus de la première couche semi-conductrice (16) de manière à exposer au moins une partie de l'aire de la première surface principale (10b) qui n'est pas couverte par la première couche semi-conductrice (16). La première surface principale (10b) du substrat semi-conducteur (10) formée par la couche isolante (18) est lavée. Une seconde couche semi-conductrice (21) présentant l'autre conductivité du type p ou du type n est formée à une position au-dessus d'une partie d'une section exposée (10b1). Au moins la couche la plus extérieure de la couche isolante (18) est constituée d'une couche de silicium amorphe (18b) formée de telle manière qu'elle ne contient pas d'hydrogène.
PCT/JP2011/057115 2010-03-25 2011-03-24 Cellule solaire et son procédé de production Ceased WO2011118685A1 (fr)

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CN107210331A (zh) * 2015-03-31 2017-09-26 株式会社钟化 太阳能电池及其制造方法

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JP6179900B2 (ja) 2012-03-30 2017-08-16 パナソニックＩｐマネジメント株式会社 太陽電池及びその製造方法
KR101977927B1 (ko) * 2012-07-11 2019-05-13 인텔렉츄얼 키스톤 테크놀로지 엘엘씨 광전소자 및 그 제조방법
KR101942783B1 (ko) * 2016-11-23 2019-04-17 엘지전자 주식회사 태양 전지 및 이의 제조 방법

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JPH11214720A (ja) * 1998-01-28 1999-08-06 Canon Inc 薄膜結晶太陽電池の製造方法
WO2009096539A1 (fr) * 2008-01-30 2009-08-06 Kyocera Corporation Élément de batterie solaire et procédé de fabrication d'élément de batterie solaire

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JPH11214720A (ja) * 1998-01-28 1999-08-06 Canon Inc 薄膜結晶太陽電池の製造方法
WO2009096539A1 (fr) * 2008-01-30 2009-08-06 Kyocera Corporation Élément de batterie solaire et procédé de fabrication d'élément de batterie solaire

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107210331A (zh) * 2015-03-31 2017-09-26 株式会社钟化 太阳能电池及其制造方法
CN107210331B (zh) * 2015-03-31 2019-06-28 株式会社钟化 太阳能电池及其制造方法

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