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WO2011116106A3 - Boîtier-système utilisant des substrats sans renforcement intérieur à matrice intégrée et procédés de fabrication associés - Google Patents

Boîtier-système utilisant des substrats sans renforcement intérieur à matrice intégrée et procédés de fabrication associés Download PDF

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Publication number
WO2011116106A3
WO2011116106A3 PCT/US2011/028689 US2011028689W WO2011116106A3 WO 2011116106 A3 WO2011116106 A3 WO 2011116106A3 US 2011028689 W US2011028689 W US 2011028689W WO 2011116106 A3 WO2011116106 A3 WO 2011116106A3
Authority
WO
WIPO (PCT)
Prior art keywords
embedded
package
processes
forming same
coreless substrates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2011/028689
Other languages
English (en)
Other versions
WO2011116106A2 (fr
Inventor
John S. Guzek
Vijay Nair
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to CN201180014284.4A priority Critical patent/CN102812550B/zh
Priority to SG2012061446A priority patent/SG183401A1/en
Priority to EP11756940.0A priority patent/EP2548225B1/fr
Priority to KR1020127024016A priority patent/KR101374463B1/ko
Publication of WO2011116106A2 publication Critical patent/WO2011116106A2/fr
Publication of WO2011116106A3 publication Critical patent/WO2011116106A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

La présente invention concerne un appareil comprenant un substrat sans renforcement intérieur à matrice intégrée, ladite matrice faisant partie intégrante du substrat sans renforcement intérieur, et au moins un dispositif monté sur une surface située à l'opposé d'un boîtier matriciel à grille disposé sur le substrat sans renforcement intérieur. Ledit appareil peut comprendre une couche de surmoulage destinée à protéger ledit dispositif installé sur ladite surface.
PCT/US2011/028689 2010-03-17 2011-03-16 Boîtier-système utilisant des substrats sans renforcement intérieur à matrice intégrée et procédés de fabrication associés Ceased WO2011116106A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201180014284.4A CN102812550B (zh) 2010-03-17 2011-03-16 采用嵌入管芯无芯衬底的系统级封装及其形成过程
SG2012061446A SG183401A1 (en) 2010-03-17 2011-03-16 System-in-package using embedded-die coreless substrates, and processes of forming same
EP11756940.0A EP2548225B1 (fr) 2010-03-17 2011-03-16 Boîtier-système utilisant des substrats sans renforcement intérieur à matrice intégrée et procédés de fabrication associés
KR1020127024016A KR101374463B1 (ko) 2010-03-17 2011-03-16 내장-다이 코어리스 기판들을 이용한 패키지형 시스템 및 그것을 형성하는 프로세스

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/725,925 US8891246B2 (en) 2010-03-17 2010-03-17 System-in-package using embedded-die coreless substrates, and processes of forming same
US12/725,925 2010-03-17

Publications (2)

Publication Number Publication Date
WO2011116106A2 WO2011116106A2 (fr) 2011-09-22
WO2011116106A3 true WO2011116106A3 (fr) 2012-01-12

Family

ID=44647093

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/028689 Ceased WO2011116106A2 (fr) 2010-03-17 2011-03-16 Boîtier-système utilisant des substrats sans renforcement intérieur à matrice intégrée et procédés de fabrication associés

Country Status (7)

Country Link
US (1) US8891246B2 (fr)
EP (1) EP2548225B1 (fr)
KR (1) KR101374463B1 (fr)
CN (1) CN102812550B (fr)
SG (1) SG183401A1 (fr)
TW (1) TWI546904B (fr)
WO (1) WO2011116106A2 (fr)

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US8891246B2 (en) 2010-03-17 2014-11-18 Intel Corporation System-in-package using embedded-die coreless substrates, and processes of forming same

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WO2011116106A2 (fr) 2011-09-22
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KR101374463B1 (ko) 2014-03-17
US8891246B2 (en) 2014-11-18
CN102812550B (zh) 2015-08-12
KR20120127500A (ko) 2012-11-21
CN102812550A (zh) 2012-12-05
US20110228464A1 (en) 2011-09-22
SG183401A1 (en) 2012-09-27
EP2548225B1 (fr) 2018-02-28
EP2548225A2 (fr) 2013-01-23
TWI546904B (zh) 2016-08-21

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