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WO2011033921A1 - Integrated circuit - Google Patents

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Publication number
WO2011033921A1
WO2011033921A1 PCT/JP2010/064602 JP2010064602W WO2011033921A1 WO 2011033921 A1 WO2011033921 A1 WO 2011033921A1 JP 2010064602 W JP2010064602 W JP 2010064602W WO 2011033921 A1 WO2011033921 A1 WO 2011033921A1
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WO
WIPO (PCT)
Prior art keywords
transmission
integrated circuit
current
coils
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2010/064602
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French (fr)
Japanese (ja)
Inventor
忠広 黒田
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Keio University
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Keio University
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Filing date
Publication date
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0266—Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B5/00—Near-field transmission systems, e.g. inductive or capacitive transmission systems
    • H04B5/20—Near-field transmission systems, e.g. inductive or capacitive transmission systems characterised by the transmission technique; characterised by the transmission medium
    • H04B5/24—Inductive coupling
    • H04B5/26—Inductive coupling using coils
    • H04B5/266—One coil at each side, e.g. with primary and secondary coils
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H01L2225/06531—Non-galvanic coupling, e.g. capacitive coupling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present invention relates to an integrated circuit capable of suitably performing communication between chips such as an IC (Integrated Circuit) bare chip mounted in a stacked manner.
  • chips such as an IC (Integrated Circuit) bare chip mounted in a stacked manner.
  • Patent Document 1 Large Scale Integration
  • FIG. 17 is a diagram showing a configuration of a transmission side circuit of a conventional integrated circuit.
  • FIG. 17A is a circuit diagram of the transmission side circuit of the first conventional example
  • FIG. 17B is a layout diagram of the transmission coil of the first conventional example
  • FIG. 17C is a transmission of the second conventional example
  • FIG. 17D is a layout diagram of the transmission coil of the second conventional example.
  • the coil diagram shows a top view of the coil formed by the wiring on the chip as viewed from above the chip.
  • the solid line indicates the wiring on the chip surface, and the broken line indicates the wiring on the lower layer.
  • an H bridge circuit composed of transistors T11 to T14 is driven by transmission data Txdata and its inverted signal to change the current i flowing through the transmission coil L11.
  • the figure also shows the parasitic resistance of the transmission coil L11.
  • the transmission current pulse width current change time
  • an inverter composed of transistors T15 and T16 is driven by transmission data Txdata, and the current i flowing through the transmission coil L12 whose other end is connected to the power supply voltage VDD is changed (Patent Document 1). (See FIG. 6).
  • the transmission current pulse width current change time
  • the layout area of a transmission circuit becomes small.
  • the power consumption of the transmission circuit is approximately halved compared to the H bridge drive.
  • An object of the present invention is to provide an integrated circuit including a transmission circuit that operates at a lower voltage and lower power consumption than the conventional transmission circuit and can be laid out in a small area.
  • An integrated circuit includes first and second transmission coils formed by wiring on a substrate, and transmission in which a unipolar current corresponding to a transmission signal is passed through the first and second transmission coils.
  • a first substrate having a circuit, a receiving coil that is formed by wiring on the substrate, and inductively couples to each of the first and second transmitting coils through which the unipolar current flows, in reverse polarity, and the reception
  • a second substrate having a receiving circuit connected to the coil and obtaining a reception signal corresponding to the transmission signal.
  • the integrated circuit of the present invention according to claim 2 is characterized in that the first and second transmission coils are connected to drains of first and second NMOSs, respectively.
  • the integrated circuit according to claim 3 is characterized in that one of the first and second transmitter coils is connected to the drain of the NMOS and the other is connected to the drain of the PMOS. To do.
  • the first and second transmission coils are connected between complementary transistors of the first and second CMOS, respectively, so that a through current of the CMOS flows.
  • the transmission circuit allows the unipolar current to flow in the first and second transmission coils so as to change in time complementary to each other.
  • the transmission circuit allows the unipolar current to flow to either one of the first or second transmission coils according to the transmission signal.
  • the integrated circuit of the present invention according to claim 7 is characterized in that the transmission circuit does not flow the unipolar current through any of the first and second transmission coils during standby in which communication is suspended. To do.
  • an integrated circuit including a transmission circuit that operates at a lower voltage and lower power consumption and can be laid out in a smaller area than a conventional transmission circuit.
  • FIG. 1 is a diagram illustrating a configuration of a transmission side of an integrated circuit according to a first embodiment of the present invention.
  • FIG. 2 is a diagram showing operation waveforms of each part of the integrated circuit according to the first embodiment of the present invention.
  • FIG. 3 is a diagram showing a configuration of another part of the integrated circuit according to the first embodiment of the present invention.
  • FIG. 4 is a diagram showing the configuration of the transmission side of the integrated circuit according to the second embodiment of the present invention.
  • FIG. 5 is a diagram showing the configuration of the transmission side of the integrated circuit according to the third embodiment of the present invention.
  • FIG. 6 is a diagram showing a configuration of a receiving circuit of an integrated circuit according to the third embodiment of the present invention.
  • FIG. 1 is a diagram illustrating a configuration of a transmission side of an integrated circuit according to a first embodiment of the present invention.
  • FIG. 2 is a diagram showing operation waveforms of each part of the integrated circuit according to the first embodiment of the present invention.
  • FIG. 7 is a diagram showing the configuration of the transmission side of the integrated circuit according to the fourth embodiment of the present invention.
  • FIG. 8 is a diagram showing a configuration of a receiving circuit of an integrated circuit according to the fourth embodiment of the present invention.
  • FIG. 9 is a diagram showing the configuration of the transmission side of the integrated circuit according to the fifth embodiment of the present invention.
  • FIG. 10 is a diagram illustrating the configuration of the transmission side of the integrated circuit according to the sixth embodiment of the present invention.
  • FIG. 11 is a diagram illustrating operation waveforms of each part of the integrated circuit according to the sixth embodiment of the present invention.
  • FIG. 12 is a diagram illustrating the configuration of the transmission side of the integrated circuit according to the seventh embodiment of the present invention.
  • FIG. 13 is a diagram illustrating the configuration of the transmission side of the integrated circuit according to the eighth embodiment of the present invention.
  • FIG. 14 is a diagram illustrating operation waveforms of respective parts of the integrated circuit according to the seventh embodiment of the present invention.
  • FIG. 15 is a diagram illustrating the configuration of the transmission side of the integrated circuit according to the eighth embodiment of the present invention.
  • FIG. 16 is a diagram showing operation waveforms of each part of the integrated circuit according to the eighth embodiment of the present invention.
  • FIG. 17 is a diagram showing a configuration of a transmission side circuit of a conventional integrated circuit.
  • FIG. 1 is a diagram showing a configuration of a transmission side of an integrated circuit according to the first embodiment of the present invention.
  • 1A is a circuit diagram
  • FIG. 1B is a layout diagram of a transmission coil
  • FIG. 1C is an equivalent circuit diagram
  • FIG. 1D is a layout diagram of the transmission coil.
  • FIG. 2 shows operation waveforms.
  • the two transmission coils L1 and L2 are arranged so that the winding directions from the terminal connected to the power source VDD to the other end are opposite to each other. This corresponds to connecting the center of one transmission coil to the power source VDD as shown in FIGS. 1 (c) and 1 (d).
  • the transmission coils L1 and L2 are connected to the drains of NMOS T1 and T2 whose sources are grounded, respectively, and are driven by the transmission data Txdata and its inverted signal.
  • induced voltages having opposite polarities are generated in the receiving coil (which will be described in detail later) by currents IT + and IT ⁇ flowing in the transmitting coils L1 and L2. That is, the receiving coil is inductively coupled with the transmitting coils L1 and L2 in opposite polarities.
  • the resistance of each of the transmission coils L1 and L2 with the number of turns halved becomes 100 ⁇ , which is 1/2 that of the conventional example, and the inductance is proportional to the square of the number of turns, so that it becomes 1/4 nH. .
  • a maximum current i of 1.2 V / 150 ⁇ 8 mA flows.
  • the transmission data Txdata changes from 0 to 1
  • the current iT + flowing through the transmission coil L1 changes by +8 mA from 0 mA to +8 mA.
  • the current iT- flowing through the transmission coil L2 changes by -8 mA from +8 mA to 0 mA.
  • the current flowing through the two transmission coils L1 and L2 changes by 8 mA from 0 mA to +8 mA.
  • the inductance of the transmission coil and the change over time of the transmission current do not change, so the maximum received signal voltage does not change.
  • two MOS transistors existing in the transmission current path, PMOS and NMOS are necessary in the conventional H-bridge drive, but in this embodiment, the number is reduced to one NMOS.
  • the power supply voltage is 1.2 V
  • the voltage across the transmission coil is 0.8 V
  • the VDS (voltage between the drain and source) of the PMOS and NMOS is 0.2 V, respectively.
  • the voltage across the transmission coil is also 0.8V, but the VDS of NMOS is 0.4V. Therefore, if the channel width is designed to be sufficiently large so that it operates in the saturation region until the NMOS VDS becomes 0.2 V, in this embodiment, the power supply voltage is lowered by 0.2 V and the NMOS VDS is reduced to 0. Even if it becomes 2V, the same output current as H bridge drive can be sent. However, since the amount of current is doubled from 4 mA to 8 mA, the channel width of the transistor needs to be doubled.
  • the layout area of the transmission circuit is twice as large as that of the NMOS, a PMOS having a current driving capability lower than that of the NMOS is not required, so that it is smaller than that of the H-bridge driving.
  • the NMOS channel width is typically 25 ⁇ m and the channel length is approximately 0.06 ⁇ m
  • the PMOS channel width is approximately 75 ⁇ m and the channel length is approximately 0.06 ⁇ m. Therefore, the double channel width NMOS layout area is the PMOS + NMOS layout area. Smaller than.
  • the drive current of the transmission coil is determined by both the PMOS and NMOS devices, whereas in this embodiment, the drive current of the transmission coil is determined only by the NMOS, which causes manufacturing variations in threshold voltage.
  • the design margin can be reduced. As a result, it is possible to operate with a lower power supply voltage and to reduce power consumption.
  • FIG. 2 is a diagram showing operation waveforms of each part of the integrated circuit according to the first embodiment of the present invention.
  • the currents IT + and IT ⁇ flowing through the transmission coils L1 and L2 change to opposite polarities. Since the transmission coils L1 and L2 are inductively coupled to the reception coil in opposite polarities, an induction voltage VR is eventually induced in the reception coil.
  • the differential input threshold value of the receiving circuit has a hysteresis characteristic as shown by a dotted line in FIG. 2 so that the receiving circuit does not malfunction due to noise. Thereby, the reception data Rxdata can be stably restored.
  • FIG. 3 is a diagram showing a configuration of another part of the integrated circuit according to the first embodiment of the present invention.
  • FIG. 3A shows a circuit for accurately inverting the phase of transmission data Txdata (rotating 180 °).
  • the phase of the transmission data Txdata can be accurately inverted by the inverter 11.
  • FIG. 3B is a diagram showing a configuration of the receiving circuit of the integrated circuit according to the first embodiment of the present invention.
  • the amount of branching of the current flowing through the current source 14 to the resistors 19 and 20 changes according to the differential reception signal input to the transistor pair 15 and 18, and the voltage signal of the output Rxdata changes. For example, when a voltage signal higher than that of the transistor 18 is input to the transistor 15, the current flowing through the resistor 19 becomes larger than the current flowing through the resistor 20, and the potential of the output Rxdata becomes higher than the potential of the output Rxdata ( ⁇ ).
  • the gate potential of the transistor 16 is higher than the gate potential of the transistor 17, and the current flowing through the resistor 19 through the transistor 16 is larger than the current flowing through the resistor 20 through the transistor 17.
  • the potential of the output Rxdata becomes higher than the potential of the output Rxdata ( ⁇ ).
  • the differential input threshold value of the receiving circuit has a hysteresis characteristic as shown by a dotted line in FIG.
  • FIG. 4 is a diagram showing the configuration of the transmission side of the integrated circuit according to the second embodiment of the present invention.
  • a current always flows through one of the transmission coils according to the transmission data Txdata. Therefore, in the present embodiment, no current flows when the transmission function is not used (during standby).
  • both the NMOSs T1 and T2 are turned off when the standby signal is on. As a result, the power consumption of the transmission circuit can be effectively reduced by setting the standby state after burst transfer of data at once.
  • FIG. 5 is a diagram showing the configuration of the transmission side of the integrated circuit according to the third embodiment of the present invention.
  • FIG. 5A is a circuit diagram
  • FIG. 5B shows operation waveforms.
  • the first embodiment is a synchronous method. Except for the difference between synchronous and asynchronous, the operation principle and effect of the transmission circuit are the same as in the first embodiment.
  • the circuit outputs a signal Q synchronized with the transmission clock Txclk with respect to the transmission data Txdata by the flip-flop 26.
  • FIG. 6 is a diagram showing a configuration of a receiving circuit of an integrated circuit according to the third embodiment of the present invention.
  • the receiving circuit includes a receiving coil 31, resistors 32 and 33, transistors 34 to 46, NAND circuits 47 and 48, and inverters 49 and 50, and constitutes a comparator with a latch as a whole.
  • a reception clock (synchronization signal) Rxclk is taken from the outside, and reception data Rxdata is output.
  • Transistors 36 and 37 form a differential pair of a differential amplifier and receive a signal VR from the receiving coil 31.
  • NAND circuits 47 and 48 form a latch.
  • Data received by the differential amplifier is sampled in synchronization with the reception clock Rxclk input to the transistors 34, 43, and 46, latched by the NAND circuits 47 and 48, and the reception signal Rxdata is restored.
  • the transistors 35, 38, and 39 function in the same manner as the transistors 13, 16, and 17 in FIG. 3 (b), and the differential input threshold value has hysteresis characteristics as shown by the dotted line in FIG. 5 (b).
  • FIG. 7 is a diagram showing the configuration of the transmission side of the integrated circuit according to the fourth embodiment of the present invention.
  • FIG. 7A is a circuit diagram
  • FIG. 7B shows operation waveforms.
  • the circuit includes an inverter delay line 51, a NAND circuit 52, and an inverter 53 in addition to the first embodiment, and has a pulse width determined by the propagation delay of the inverter delay line 51 in synchronization with the rising edge of the transmission clock Txclk.
  • a pulse generation circuit that generates a pulse Txp, a flip-flop 54 that outputs a data signal Q corresponding to transmission data Txdata and its inverted signal in synchronization with the transmission clock Txclk, NAND circuits 55 and 56, and inverters 57 and 58 are provided.
  • the current flowing through the transmission coil is pulsed.
  • the power consumption of the transmission circuit can be greatly reduced. Even when the same transmission data Txdata is subsequently transmitted, a transmission pulse is transmitted every time. Therefore, if data is received in synchronization with the timing, it becomes strong against noise and it is not necessary to provide the receiver with hysteresis.
  • FIG. 8 is a diagram illustrating a configuration of a receiving circuit of an integrated circuit according to the fourth embodiment of the present invention.
  • the receiving circuit includes a receiving coil 61, resistors 62 and 63, transistors 64 to 73, NAND circuits 74 and 76, and inverters 76 and 77, and constitutes a comparator with a latch as a whole.
  • a reception clock (synchronization signal) Rxclk is taken from the outside, and reception data Rxdata is output.
  • Transistors 65 and 66 form a differential pair of a differential amplifier, and receive signal VR from receiving coil 61.
  • NAND circuits 74 and 75 form a latch.
  • Data received by the differential amplifier is sampled in synchronization with the reception clock Rxclk input to the transistors 64, 70, and 73, latched by the NAND circuits 74 and 75, and the reception signal Rxdata is restored. It is necessary to align the timing of the reception pulse when the transmission data is 0 and the timing of the reception pulse when the transmission data is 1. That is, it is necessary to align signal delays in the path from the rising edge of the transmission clock Txclk to the rising edges of the VX + and VX ⁇ signals. In the circuit of FIG. 7, since both signal paths are formed of the same circuit, signals can be easily aligned. In this circuit, iT + and iT ⁇ are not complementary.
  • the inductance of the coil can only be seen as 2.5nH, which is 1/4.
  • the received signal voltage is halved compared to the first to third embodiments.
  • the reception signal voltage can be made equal. Even in that case, there is a possibility that the transmission power can be reduced as compared with the first and second embodiments.
  • FIG. 9 is a diagram showing the configuration of the transmission side of the integrated circuit according to the fifth embodiment of the present invention.
  • the same operation as that of the fourth embodiment is realized more simply, and the pulse Txp generated by the pulse generation circuit including the inverter delay line 81, the NAND circuit 82, and the inverter 83 is input to the gate of the transistor 85. To do.
  • the peripheral circuit can be simplified as compared with the fourth embodiment.
  • FIG. 10 is a diagram showing the configuration of the transmission side of the integrated circuit according to the sixth embodiment of the present invention.
  • FIG. 10A is a circuit diagram
  • FIG. 10B is a layout diagram of the transmission coil.
  • FIG. 11 shows operation waveforms.
  • the circuit connects the transmission coil L3 and NMOST3 in series between the power supply and ground, connects the transmission coil L4 and PMOST4 in series between the power supply and ground, and inputs transmission data to the gates of NMOST3 and PMOST4. It is.
  • this embodiment is functionally the same as the embodiment 1, the phase inversion circuit as shown in FIG. 3A is unnecessary, and the layout area is reduced accordingly, and the power consumption of the circuit is reduced. Also lower.
  • FIG. 12 is a diagram showing the configuration of the transmission side of the integrated circuit according to the seventh embodiment of the present invention.
  • the present embodiment is the same as the second embodiment with respect to the sixth embodiment, and prevents the current from flowing when the transmission function is not used (in standby mode).
  • the transmission data Txdata and the standby signal or its inverted signal By inputting the transmission data Txdata and the standby signal or its inverted signal to the NOR circuits 87 and 88, both the NMOS T3 and the PMOS T4 are turned off when the standby signal is on.
  • the power consumption of the transmission circuit can be effectively reduced by setting the standby state after burst transfer of data at once.
  • FIG. 13 is a diagram showing the configuration of the transmission side of the integrated circuit according to the eighth embodiment of the present invention.
  • FIG. 14 shows operation waveforms.
  • a CMOS through current is passed through the transmission coil.
  • the circuit includes transmission coils L1 and L2, a flip-flop 91, transistors 92 to 96, T5 to T8, and inverters 97 to 99.
  • the operation starts when the reset signal is turned off.
  • the signal Q synchronized with the transmission clock Txclk with respect to the transmission data Txdata changes from 0 to 1, A changes from 0 to 1, and Vx + changes from 1. 0.
  • the signal Q goes from 1 to 0, B goes from 1 to 0, C goes from 1 to 0, and Vx- goes from 0 to 1.
  • Vx + is alternately inverted whenever the signal Q changes from 0 to 1
  • Vx ⁇ is alternately inverted whenever the signal Q changes from 1 to 0.
  • a through current IT + flows whenever the potential of Vx + is inverted, and a through current IT ⁇ flows whenever the potential of Vx ⁇ is inverted. Since this through current has a short pulse shape, the consumption of the transmission current can be reduced. As a result, a bipolar pulse whose phase is alternately inverted with respect to the logical transition of the signal Q is induced in the reception coil, and the reception signal Rxdata is restored.
  • the signal Q is changed from 0 to 1
  • the potential of Vx ⁇ may be changed from ground to VDD and may be changed from VDD to ground. It is necessary to design the signal propagation of the transmission circuit.
  • the signal Q changes from 1 to 0 it is necessary to design so that the received pulse can be obtained at the same timing as when the signal Q changes from 0 to 1.
  • FIG. 15 is a diagram illustrating the configuration of the transmission side of the integrated circuit according to the eighth embodiment of the present invention.
  • FIG. 16 shows operation waveforms.
  • the flip-flop 101, the NAND circuit 102, and the NOR circuit 103 are used to simplify the peripheral circuit of the seventh embodiment.
  • This embodiment frequently generates through currents IT + and IT ⁇ , but also has an advantage that signal propagation from the transmission clock Txclk to Vx + and Vx ⁇ can be easily designed equally.
  • this invention is not limited to the said Example.

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Hardware Design (AREA)
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  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Near-Field Transmission Systems (AREA)

Abstract

Disclosed is an integrated circuit wherein chips that are mounted by being stacked communicate with each other by means of inductive coupling. In order to provide the integrated circuit provided with a transmitting circuit, which operates with a low voltage and low power consumption and can be laid out in a small area, two transmission coils (L1, L2) are disposed such that respective winding directions from concentric terminals, which are connected to a power supply (VDD), to the other ends are opposite to each other. The drains of NMOS (T1, T2) having the sources thereof grounded are connected to the transmission coils (L1, L2), respectively, and the coils are driven by means of transmission data (Txdata) and the inversion signals thereof.

Description

集積回路Integrated circuit

　本発明は、積層実装されるＩＣ（Integrated Circuit）ベアチップなどのチップ間の通信を好適に行うことができる集積回路に関する。 The present invention relates to an integrated circuit capable of suitably performing communication between chips such as an IC (Integrated Circuit) bare chip mounted in a stacked manner.

　本発明者らは、ＬＳＩ（Large Scale Integration）チップのチップ上の配線により形成されるコイルを介して積層実装されるチップ間で誘導結合による通信を行う電子回路を提案している（特許文献１～１２、非特許文献１～８参照。）。 The present inventors have proposed an electronic circuit that performs communication by inductive coupling between chips stacked and mounted via a coil formed by wiring on a chip of an LSI (Large Scale Integration) chip (Patent Document 1). To 12, and non-patent documents 1 to 8).

　図１７は、従来の集積回路の送信側回路の構成を示す図である。図１７(a)は第１の従来例の送信側回路の回路図、図１７(b)は第１の従来例の送信コイルのレイアウト図、図１７(c)は第２の従来例の送信側回路の回路図、図１７(d)は第２の従来例の送信コイルのレイアウト図である。コイルの図はチップ上の配線により形成されるコイルをチップの上から見た上面図を示すものであり、実線はチップ表面の配線、破線は下層の配線を示す。第１の従来例は、トランジスタＴ11～Ｔ14から成るＨブリッジ回路を送信データＴxdata及びその反転信号によって駆動して送信コイルＬ11に流れる電流ｉを変化させるものである。図には送信コイルＬ11の寄生抵抗も示した。典型的な設計値としては、送信コイルのインダクタンスＬ＝１０ｎＨ、送信コイルの寄生抵抗Ｒ＝２００Ω、ＮＭＯＳやＰＭＯＳのオン抵抗ＲM＝５０Ω、電源電圧が１.２Ｖである。送信電流経路にある抵抗値の総和が２００Ω＋２＊５０Ω＝３００Ωになるので、１.２Ｖ／３００Ω＝４ｍＡの最大電流ｉが流れる。例えば送信データＴxdataが０から１に変化すると、コイルを流れる電流ｉは、－４ｍＡから＋４ｍＡに８ｍＡ変化する。送信電流パルス幅（電流変化の時間）を１００ｐｓにすると、ｄｉ／ｄｔは、簡単化のため電流が直線的に変化するとして、８ｍＡ／１００ｐｓ＝８０［ｍＡ／ｎｓ］になる。 FIG. 17 is a diagram showing a configuration of a transmission side circuit of a conventional integrated circuit. FIG. 17A is a circuit diagram of the transmission side circuit of the first conventional example, FIG. 17B is a layout diagram of the transmission coil of the first conventional example, and FIG. 17C is a transmission of the second conventional example. FIG. 17D is a layout diagram of the transmission coil of the second conventional example. The coil diagram shows a top view of the coil formed by the wiring on the chip as viewed from above the chip. The solid line indicates the wiring on the chip surface, and the broken line indicates the wiring on the lower layer. In the first conventional example, an H bridge circuit composed of transistors T11 to T14 is driven by transmission data Txdata and its inverted signal to change the current i flowing through the transmission coil L11. The figure also shows the parasitic resistance of the transmission coil L11. Typical design values are a transmission coil inductance L = 10 nH, a transmission coil parasitic resistance R = 200Ω, an NMOS or PMOS on-resistance RM = 50Ω, and a power supply voltage of 1.2V. Since the sum of the resistance values in the transmission current path is 200Ω + 2 * 50Ω = 300Ω, a maximum current i of 1.2 V / 300Ω = 4 mA flows. For example, when the transmission data Txdata changes from 0 to 1, the current i flowing through the coil changes by 8 mA from -4 mA to +4 mA. When the transmission current pulse width (current change time) is set to 100 ps, di / dt becomes 8 mA / 100 ps = 80 [mA / ns] assuming that the current changes linearly for simplification.

　第２の従来例は、トランジスタＴ15、Ｔ16から成るインバータを送信データＴxdataによって駆動して、他端が電源電圧ＶDDに接続される送信コイルＬ12に流れる電流ｉを変化させるものである（特許文献１図６参照）。この場合、送信電流経路にある抵抗値の総和が２００Ω＋５０Ω＝２５０Ωになるので、１.２Ｖ／２５０Ω＝４.８ｍＡの最大電流ｉが流れる。例えば送信データＴxdataが０から１に変化すると、コイルを流れる電流ｉは、０ｍＡから＋４.８ｍＡに４.８ｍＡ変化する。送信電流パルス幅（電流変化の時間）を１００ｐｓにすると、ｄｉ／ｄｔは、簡単化のため電流が直線的に変化するとして、４.８ｍＡ／１００ｐｓ＝４８［ｍＡ／ｎｓ］になる。 In the second conventional example, an inverter composed of transistors T15 and T16 is driven by transmission data Txdata, and the current i flowing through the transmission coil L12 whose other end is connected to the power supply voltage VDD is changed (Patent Document 1). (See FIG. 6). In this case, since the sum of the resistance values in the transmission current path is 200Ω + 50Ω = 250Ω, a maximum current i of 1.2 V / 250Ω = 4.8 mA flows. For example, when the transmission data Txdata changes from 0 to 1, the current i flowing through the coil changes by 4.8 mA from 0 mA to +4.8 mA. When the transmission current pulse width (current change time) is set to 100 ps, di / dt becomes 4.8 mA / 100 ps = 48 [mA / ns] assuming that the current changes linearly for simplification.

　このように、インバータ駆動は、Ｈブリッジ駆動に比べて、送信出力は４８／８０＝６０％に低下する。一方、回路素子が少ないので送信回路のレイアウト面積が小さくなる。また、送信データＴxdataが０の間は送信電流が流れないので、送信回路の消費電力がＨブリッジ駆動に比べておよそ半減する。 Thus, in the inverter drive, the transmission output is reduced to 48/80 = 60% compared to the H bridge drive. On the other hand, since there are few circuit elements, the layout area of a transmission circuit becomes small. In addition, since the transmission current does not flow while the transmission data Txdata is 0, the power consumption of the transmission circuit is approximately halved compared to the H bridge drive.

特開２００５－２２８９８１号公報JP 2005-228981 A 特開２００５－３４８２６４号公報JP 2005-348264 A 特開２００６－０５０３５４号公報JP 2006-050354 A 特開２００６－０６６４５４号公報JP 2006-066644 A 特開２００６－１０５６３０号公報JP 2006-105630 A 特開２００６－１７３９８６号公報JP 2006-173986 A 特開２００６－１７３４１５号公報JP 2006-173415 A 国際公開第２００９／０６９５３２号International Publication No. 2009/069532 特開２００９－１８８４６８号公報JP 2009-188468 A 特開２００９－２６６１０９号公報JP 2009-266109 A 特開２００９－２９５６９９号公報JP 2009-295699 A 特開２０１０－１５３７５４号公報JP 2010-153754 A

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　本発明は、上記従来の送信回路よりも、低電圧・低消費電力で動作し、小面積でレイアウトできる送信回路を備える集積回路を提供することを目的とする。 An object of the present invention is to provide an integrated circuit including a transmission circuit that operates at a lower voltage and lower power consumption than the conventional transmission circuit and can be laid out in a small area.

　請求項１記載の本発明の集積回路は、基板上の配線により形成される第１及び第２送信コイルと、該第１及び第２送信コイルに送信信号に応じた単極性の電流を流す送信回路とを有する第１基板と、基板上の配線により形成され、前記単極性の電流が流れる前記第１及び第２送信コイルに対して、逆極性にそれぞれと誘導結合する受信コイルと、該受信コイルに接続され、前記送信信号に応じた受信信号を得る受信回路とを有する第２基板とを備えることを特徴とする。 An integrated circuit according to a first aspect of the present invention includes first and second transmission coils formed by wiring on a substrate, and transmission in which a unipolar current corresponding to a transmission signal is passed through the first and second transmission coils. A first substrate having a circuit, a receiving coil that is formed by wiring on the substrate, and inductively couples to each of the first and second transmitting coils through which the unipolar current flows, in reverse polarity, and the reception And a second substrate having a receiving circuit connected to the coil and obtaining a reception signal corresponding to the transmission signal.

　また、請求項２記載の本発明の集積回路は、前記第１及び第２送信コイルは、それぞれ第１及び第２ＮＭＯＳのドレインに接続されていることを特徴とする。 The integrated circuit of the present invention according to claim 2 is characterized in that the first and second transmission coils are connected to drains of first and second NMOSs, respectively.

　また、請求項３記載の本発明の集積回路は、前記第１及び第２送信コイルの内、一方はＮＭＯＳのドレインに接続されており、他方はＰＭＯＳのドレインに接続されていることを特徴とする。 The integrated circuit according to claim 3 is characterized in that one of the first and second transmitter coils is connected to the drain of the NMOS and the other is connected to the drain of the PMOS. To do.

　また、請求項４記載の本発明の集積回路は、前記第１及び第２送信コイルは、それぞれ第１及び第２ＣＭＯＳの相補のトランジスタ間に接続されていて、該ＣＭＯＳの貫通電流が流れることを特徴とする。 Further, in the integrated circuit of the present invention according to claim 4, the first and second transmission coils are connected between complementary transistors of the first and second CMOS, respectively, so that a through current of the CMOS flows. Features.

　また、請求項５記載の本発明の集積回路は、前記送信回路は、前記単極性の電流を、前記第１及び第２送信コイルにおいて互いに相補的に時間変化するように流すことを特徴とする。 In the integrated circuit of the present invention according to claim 5, the transmission circuit allows the unipolar current to flow in the first and second transmission coils so as to change in time complementary to each other. .

　また、請求項６記載の本発明の集積回路は、前記送信回路は、前記単極性の電流を、前記第１又は第２送信コイルの内、前記送信信号に応じたいずれか一方に流すことを特徴とする。 Further, in the integrated circuit of the present invention according to claim 6, the transmission circuit allows the unipolar current to flow to either one of the first or second transmission coils according to the transmission signal. Features.

　また、請求項７記載の本発明の集積回路は、前記送信回路は、通信を休止するスタンバイ時に、前記第１及び第２送信コイルのいずれにも前記単極性の電流を流さないことを特徴とする。 The integrated circuit of the present invention according to claim 7 is characterized in that the transmission circuit does not flow the unipolar current through any of the first and second transmission coils during standby in which communication is suspended. To do.

　本発明によれば、従来の送信回路よりも、低電圧・低消費電力で動作し、小面積でレイアウトできる送信回路を備える集積回路を提供することができる。 According to the present invention, it is possible to provide an integrated circuit including a transmission circuit that operates at a lower voltage and lower power consumption and can be laid out in a smaller area than a conventional transmission circuit.

図１は、本発明の実施例１による集積回路の送信側の構成を示す図である。FIG. 1 is a diagram illustrating a configuration of a transmission side of an integrated circuit according to a first embodiment of the present invention. 図２は、本発明の実施例１による集積回路各部の動作波形を示す図である。FIG. 2 is a diagram showing operation waveforms of each part of the integrated circuit according to the first embodiment of the present invention. 図３は、本発明の実施例１による集積回路の他の部分の構成を示す図である。FIG. 3 is a diagram showing a configuration of another part of the integrated circuit according to the first embodiment of the present invention. 図４は、本発明の実施例２による集積回路の送信側の構成を示す図である。FIG. 4 is a diagram showing the configuration of the transmission side of the integrated circuit according to the second embodiment of the present invention. 図５は、本発明の実施例３による集積回路の送信側の構成を示す図である。FIG. 5 is a diagram showing the configuration of the transmission side of the integrated circuit according to the third embodiment of the present invention. 図６は、本発明の実施例３による集積回路の受信回路の構成を示す図である。FIG. 6 is a diagram showing a configuration of a receiving circuit of an integrated circuit according to the third embodiment of the present invention. 図７は、本発明の実施例４による集積回路の送信側の構成を示す図である。FIG. 7 is a diagram showing the configuration of the transmission side of the integrated circuit according to the fourth embodiment of the present invention. 図８は、本発明の実施例４による集積回路の受信回路の構成を示す図である。FIG. 8 is a diagram showing a configuration of a receiving circuit of an integrated circuit according to the fourth embodiment of the present invention. 図９は、本発明の実施例５による集積回路の送信側の構成を示す図である。FIG. 9 is a diagram showing the configuration of the transmission side of the integrated circuit according to the fifth embodiment of the present invention. 図１０は、本発明の実施例６による集積回路の送信側の構成を示す図である。FIG. 10 is a diagram illustrating the configuration of the transmission side of the integrated circuit according to the sixth embodiment of the present invention. 図１１は、本発明の実施例６による集積回路各部の動作波形を示す図である。FIG. 11 is a diagram illustrating operation waveforms of each part of the integrated circuit according to the sixth embodiment of the present invention. 図１２は、本発明の実施例７による集積回路の送信側の構成を示す図である。FIG. 12 is a diagram illustrating the configuration of the transmission side of the integrated circuit according to the seventh embodiment of the present invention. 図１３は、本発明の実施例８による集積回路の送信側の構成を示す図である。FIG. 13 is a diagram illustrating the configuration of the transmission side of the integrated circuit according to the eighth embodiment of the present invention. 図１４は、本発明の実施例７による集積回路各部の動作波形を示す図である。FIG. 14 is a diagram illustrating operation waveforms of respective parts of the integrated circuit according to the seventh embodiment of the present invention. 図１５は、本発明の実施例８による集積回路の送信側の構成を示す図である。FIG. 15 is a diagram illustrating the configuration of the transmission side of the integrated circuit according to the eighth embodiment of the present invention. 図１６は、本発明の実施例８による集積回路各部の動作波形を示す図である。FIG. 16 is a diagram showing operation waveforms of each part of the integrated circuit according to the eighth embodiment of the present invention. 図１７は、従来の集積回路の送信側回路の構成を示す図である。FIG. 17 is a diagram showing a configuration of a transmission side circuit of a conventional integrated circuit.

　以下、添付図面を参照しながら本発明を実施するための形態について詳細に説明する。 Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings.

　図１は、本発明の実施例１による集積回路の送信側の構成を示す図である。図１(a)は回路図、図１(b)は送信コイルのレイアウト図、図１(c)は等価回路図、図１(d)はその送信コイルのレイアウト図である。図２に動作波形を示す。まず、送信コイルＬ1、Ｌ2を２つにして、同心かつ電源ＶDDに接続される端子から他端への巻き方向が互いに逆になるように配置する。これは、図１(c)、図１(d)に示すように、１つの送信コイルの中央を電源ＶDDに接続したことにも相当する。この送信コイルＬ1、Ｌ2にそれぞれ、ソースが接地されるＮＭＯＳＴ1、Ｔ2のドレインを接続して、送信データＴxdata及びその反転信号によって駆動する。この場合、送信コイルＬ1、Ｌ2に流れる電流ＩT+、ＩT-によって受信コイル（後に詳述する）に互いに逆極性の誘導電圧を発生する。すなわち、受信コイルは送信コイルＬ1、Ｌ2のそれぞれと互いに逆極性に誘導結合する。そして、巻き数が半分になった各送信コイルＬ1、Ｌ2の抵抗は従来例の１／２の１００Ωになり、インダクタンスは、巻き数の２乗に比例するので１／４の２.５ｎＨになる。送信電流経路にある抵抗値の総和が１００Ω＋５０Ω＝１５０Ωになるので、１.２Ｖ／１５０Ω＝８ｍＡの最大電流ｉが流れる。例えば送信データＴxdataが０から１に変化すると、送信コイルＬ1を流れる電流ｉT+は、０ｍＡから＋８ｍＡに＋８ｍＡ変化する。同時に送信コイルＬ2を流れる電流ｉT-は、＋８ｍＡから０ｍＡに－８ｍＡ変化する。電流の極性も考え合わせると、２つの送信コイルＬ1、Ｌ2全体に流れる電流が０ｍＡから＋８ｍＡに８ｍＡ変化する。送信電流が変化する時間を１００ｐｓにすると、ｄｉ／ｄｔは、簡単化のため電流が直線的に変化するとして、８ｍＡ／１００ｐｓ＝８０［ｍＡ／ｎｓ］になる。送信コイルＬ1、Ｌ2全体に流れる電流が変化するので、送信コイルＬ1、Ｌ2全体の等価的なインダクタンスは１０ｎＨであり従来例と変わらない。 FIG. 1 is a diagram showing a configuration of a transmission side of an integrated circuit according to the first embodiment of the present invention. 1A is a circuit diagram, FIG. 1B is a layout diagram of a transmission coil, FIG. 1C is an equivalent circuit diagram, and FIG. 1D is a layout diagram of the transmission coil. FIG. 2 shows operation waveforms. First, the two transmission coils L1 and L2 are arranged so that the winding directions from the terminal connected to the power source VDD to the other end are opposite to each other. This corresponds to connecting the center of one transmission coil to the power source VDD as shown in FIGS. 1 (c) and 1 (d). The transmission coils L1 and L2 are connected to the drains of NMOS T1 and T2 whose sources are grounded, respectively, and are driven by the transmission data Txdata and its inverted signal. In this case, induced voltages having opposite polarities are generated in the receiving coil (which will be described in detail later) by currents IT + and IT− flowing in the transmitting coils L1 and L2. That is, the receiving coil is inductively coupled with the transmitting coils L1 and L2 in opposite polarities. The resistance of each of the transmission coils L1 and L2 with the number of turns halved becomes 100Ω, which is 1/2 that of the conventional example, and the inductance is proportional to the square of the number of turns, so that it becomes 1/4 nH. . Since the sum of the resistance values in the transmission current path is 100Ω + 50Ω = 150Ω, a maximum current i of 1.2 V / 150Ω = 8 mA flows. For example, when the transmission data Txdata changes from 0 to 1, the current iT + flowing through the transmission coil L1 changes by +8 mA from 0 mA to +8 mA. At the same time, the current iT- flowing through the transmission coil L2 changes by -8 mA from +8 mA to 0 mA. Considering the polarity of the current, the current flowing through the two transmission coils L1 and L2 changes by 8 mA from 0 mA to +8 mA. If the time when the transmission current changes is set to 100 ps, di / dt becomes 8 mA / 100 ps = 80 [mA / ns] assuming that the current changes linearly for simplification. Since the current flowing through the entire transmission coils L1 and L2 changes, the equivalent inductance of the entire transmission coils L1 and L2 is 10 nH, which is the same as the conventional example.

　本実施例は、従来のＨブリッジ駆動（図１７(a)）に比べて、送信コイルのインダクタンスも送信電流の時間変化も変わらないので、最大受信信号電圧は変わらない。しかし、送信電流経路に存在するＭＯＳトランジスタが、従来のＨブリッジ駆動ではＰＭＯＳとＮＭＯＳの２つ必要であったが、本実施例ではＮＭＯＳの１つに減っている。その結果、より低い電源電圧で動作できる。例えば、Ｈブリッジ駆動では、電源電圧を１.２Ｖとして、送信コイルの両端電圧は０.８Ｖになり、ＰＭＯＳとＮＭＯＳのＶＤＳ（ドレインとソースの間の電圧）はそれぞれ０.２Ｖであった。一方、本実施例では、送信コイルの両端電圧は同じく０.８Ｖだが、ＮＭＯＳのＶＤＳが０.４Ｖになる。したがって、ＮＭＯＳのＶＤＳが０.２Ｖになるまで飽和領域で動作するようにそのチャネル幅を十分に大きく設計してあれば、本実施例で電源電圧を０.２Ｖ下げてＮＭＯＳのＶＤＳが０.２Ｖになっても、Ｈブリッジ駆動と同じ出力電流を流すことができる。ただし、電流量は４ｍＡから８ｍＡに２倍になっているので、トランジスタのチャネル幅は２倍大きくする必要がある。送信回路のレイアウト面積は、ＮＭＯＳが２倍大きくなるが、ＮＭＯＳよりも電流駆動力の低いＰＭＯＳが不要になるので、Ｈブリッジ駆動と比べても小さくなる。例えば典型的にはＮＭＯＳのチャネル幅２５μｍ、チャネル長０.０６μｍ程度に対して、ＰＭＯＳのチャネル幅７５μｍ、チャネル長０.０６μｍ程度であるので、２倍チャネル幅ＮＭＯＳのレイアウト面積はＰＭＯＳ＋ＮＭＯＳのレイアウト面積よりも小さい。また、Ｈブリッジ駆動では、送信コイルの駆動電流がＰＭＯＳとＮＭＯＳの両デバイスによって決まるのに対して、本実施例では送信コイルの駆動電流はＮＭＯＳだけで決まるので、しきい値電圧の製造ばらつきに対して設計マージンを小さくすることができる。その結果、より低い電源電圧で動作することができて、低消費電力化できる。 In this embodiment, compared to the conventional H-bridge drive (FIG. 17 (a)), the inductance of the transmission coil and the change over time of the transmission current do not change, so the maximum received signal voltage does not change. However, two MOS transistors existing in the transmission current path, PMOS and NMOS, are necessary in the conventional H-bridge drive, but in this embodiment, the number is reduced to one NMOS. As a result, it is possible to operate with a lower power supply voltage. For example, in the H-bridge driving, the power supply voltage is 1.2 V, the voltage across the transmission coil is 0.8 V, and the VDS (voltage between the drain and source) of the PMOS and NMOS is 0.2 V, respectively. On the other hand, in this embodiment, the voltage across the transmission coil is also 0.8V, but the VDS of NMOS is 0.4V. Therefore, if the channel width is designed to be sufficiently large so that it operates in the saturation region until the NMOS VDS becomes 0.2 V, in this embodiment, the power supply voltage is lowered by 0.2 V and the NMOS VDS is reduced to 0. Even if it becomes 2V, the same output current as H bridge drive can be sent. However, since the amount of current is doubled from 4 mA to 8 mA, the channel width of the transistor needs to be doubled. Although the layout area of the transmission circuit is twice as large as that of the NMOS, a PMOS having a current driving capability lower than that of the NMOS is not required, so that it is smaller than that of the H-bridge driving. For example, the NMOS channel width is typically 25 μm and the channel length is approximately 0.06 μm, whereas the PMOS channel width is approximately 75 μm and the channel length is approximately 0.06 μm. Therefore, the double channel width NMOS layout area is the PMOS + NMOS layout area. Smaller than. In the H-bridge drive, the drive current of the transmission coil is determined by both the PMOS and NMOS devices, whereas in this embodiment, the drive current of the transmission coil is determined only by the NMOS, which causes manufacturing variations in threshold voltage. On the other hand, the design margin can be reduced. As a result, it is possible to operate with a lower power supply voltage and to reduce power consumption.

　図２は、本発明の実施例１による集積回路各部の動作波形を示す図である。送信データＴxdataが０１１００と変化するときの論理遷移時に、送信コイルＬ1、Ｌ2に流れる電流ＩT+、ＩT-が互いに逆極性に変化する。そして、送信コイルＬ1、Ｌ2は、互いに逆極性に受信コイルと誘導結合しているので、結局受信コイルには誘導電圧ＶRが誘起される。その際に、受信回路がノイズで誤動作しないように、受信回路の差動入力しきい値に、図２に点線で示すようなヒステリシス特性を持たせている。これにより安定的に受信データＲxdataを復元することができる。 FIG. 2 is a diagram showing operation waveforms of each part of the integrated circuit according to the first embodiment of the present invention. At the time of logical transition when the transmission data Txdata changes to 01100, the currents IT + and IT− flowing through the transmission coils L1 and L2 change to opposite polarities. Since the transmission coils L1 and L2 are inductively coupled to the reception coil in opposite polarities, an induction voltage VR is eventually induced in the reception coil. At this time, the differential input threshold value of the receiving circuit has a hysteresis characteristic as shown by a dotted line in FIG. 2 so that the receiving circuit does not malfunction due to noise. Thereby, the reception data Rxdata can be stably restored.

　図３は、本発明の実施例１による集積回路の他の部分の構成を示す図である。図３(a)は送信データＴxdataを正確に位相反転（１８０°回転）させる回路を示す。インバータ１１によって送信データＴxdataを正確に位相反転させるとができる。 FIG. 3 is a diagram showing a configuration of another part of the integrated circuit according to the first embodiment of the present invention. FIG. 3A shows a circuit for accurately inverting the phase of transmission data Txdata (rotating 180 °). The phase of the transmission data Txdata can be accurately inverted by the inverter 11.

　図３(b)は、本発明の実施例１による集積回路の受信回路の構成を示す図である。トランジスタ対１５、１８に入力する差動受信信号に応じて、電流源１４が流す電流の抵抗１９、２０への分岐量が変化し、出力Ｒxdataの電圧信号が変化する。例えば、トランジスタ１５にトランジスタ１８よりも高い電圧信号が入力すると、抵抗１９に流れる電流は抵抗２０に流れる電流よりも大きくなり、出力Ｒxdataの電位は出力Ｒxdata(-)の電位よりも高くなる。 FIG. 3B is a diagram showing a configuration of the receiving circuit of the integrated circuit according to the first embodiment of the present invention. The amount of branching of the current flowing through the current source 14 to the resistors 19 and 20 changes according to the differential reception signal input to the transistor pair 15 and 18, and the voltage signal of the output Rxdata changes. For example, when a voltage signal higher than that of the transistor 18 is input to the transistor 15, the current flowing through the resistor 19 becomes larger than the current flowing through the resistor 20, and the potential of the output Rxdata becomes higher than the potential of the output Rxdata (−).

　その場合、トランジスタ１６のゲート電位はトランジスタ１７のゲート電位よりも高くなり、トランジスタ１６を介して抵抗１９に流れる電流は、トランジスタ１７を介して抵抗２０に流れる電流よりも大きくなる。その結果、出力Ｒxdataの電位は出力Ｒxdata(-)の電位よりも更に高くなる。その状態から次に先ほどと逆の受信信号がコイル１２に誘起された場合、すなわちトランジスタ１８にトランジスタ１５よりも高い電圧信号が入力すると、抵抗２０に流れる電流は抵抗１９に流れる電流よりも大きくなるが、先ほどトランジスタ１６を介して抵抗１９に流れる電流はトランジスタ１７を介して抵抗２０に流れる電流よりも大きくなっていたので、出力Ｒxdataの電圧信号が大きく変化しない限り、入力に対する出力の変化は鈍くなったと言える。つまり、ノイズで誤動作しないように、入力しきい値が期待される信号の方向に高くなったと言える。このことにより、受信回路の差動入力しきい値に、図２に点線で示すようなヒステリシス特性を持たせている。 In that case, the gate potential of the transistor 16 is higher than the gate potential of the transistor 17, and the current flowing through the resistor 19 through the transistor 16 is larger than the current flowing through the resistor 20 through the transistor 17. As a result, the potential of the output Rxdata becomes higher than the potential of the output Rxdata (−). When a reception signal opposite to the previous one is induced in the coil 12 from that state, that is, when a voltage signal higher than the transistor 15 is input to the transistor 18, the current flowing through the resistor 20 becomes larger than the current flowing through the resistor 19. However, since the current flowing through the resistor 19 via the transistor 16 is larger than the current flowing through the resistor 20 via the transistor 17, the change in the output relative to the input is slow unless the voltage signal of the output Rxdata changes greatly. It can be said that it became. In other words, it can be said that the input threshold value increases in the direction of the expected signal so as not to malfunction due to noise. Thereby, the differential input threshold value of the receiving circuit has a hysteresis characteristic as shown by a dotted line in FIG.

　図４は、本発明の実施例２による集積回路の送信側の構成を示す図である。実施例１の送信回路は、送信データＴxdataに応じて必ずどちらか一方の送信コイルに電流が流れ続ける。そこで、送信機能を使わないとき（スタンバイ時）は電流が流れないようにしたのが本実施例である。ＮＯＲ回路２１、２２にstandby信号及び送信データＴxdata又はその反転信号を入力することにより、standby信号がオンのときにＮＭＯＳＴ1、Ｔ2の両方をオフにする。これにより、データを一気にバースト転送した後にスタンバイ状態にすれば、送信回路の消費電力を有効に低下できる。 FIG. 4 is a diagram showing the configuration of the transmission side of the integrated circuit according to the second embodiment of the present invention. In the transmission circuit of the first embodiment, a current always flows through one of the transmission coils according to the transmission data Txdata. Therefore, in the present embodiment, no current flows when the transmission function is not used (during standby). By inputting the standby signal and transmission data Txdata or its inverted signal to the NOR circuits 21 and 22, both the NMOSs T1 and T2 are turned off when the standby signal is on. As a result, the power consumption of the transmission circuit can be effectively reduced by setting the standby state after burst transfer of data at once.

　図５は、本発明の実施例３による集積回路の送信側の構成を示す図である。図５(a)は回路図であり、図５(b)は動作波形を示す。本実施例は、実施例１を同期方式にしたものである。同期か非同期かの違いを除いて、送信回路の動作原理と効果は、実施例１と等しい。回路はフリップフロップ２６によって送信データＴxdataに対して送信クロックＴxclkに同期した信号Ｑを出力するものである。 FIG. 5 is a diagram showing the configuration of the transmission side of the integrated circuit according to the third embodiment of the present invention. FIG. 5A is a circuit diagram, and FIG. 5B shows operation waveforms. In this embodiment, the first embodiment is a synchronous method. Except for the difference between synchronous and asynchronous, the operation principle and effect of the transmission circuit are the same as in the first embodiment. The circuit outputs a signal Q synchronized with the transmission clock Txclk with respect to the transmission data Txdata by the flip-flop 26.

　図６は、本発明の実施例３による集積回路の受信回路の構成を示す図である。受信回路は、受信コイル３１、抵抗３２、３３、トランジスタ３４～４６、ＮＡＮＤ回路４７、４８、及びインバータ４９、５０から成り、全体としてラッチつき比較器を構成している。外部から受信クロック（同期信号）Ｒxclkをとり、受信データＲxdataを出力する。トランジスタ３６、３７が差動アンプの差動対をなし、受信コイル３１からの信号ＶRを受ける。ＮＡＮＤ回路４７、４８はラッチを形成している。差動アンプで受信したデータはトランジスタ３４、４３、４６へ入力される受信クロックＲxclkに同期してサンプリングされ、ＮＡＮＤ回路４７、４８によりラッチされ、受信信号Ｒxdataが復元される。トランジスタ３５、３８、３９は、図３(b)のトランジスタ１３、１６、１７と同じに機能し、差動入力しきい値に、図５(b)に点線で示すようなヒステリシス特性を持たせて、同じ送信データが続くとき、送信パルス電流が変化せず、受信パルス信号が誘起されないので、そのときに同期受信器が誤動作をしないようにしている。 FIG. 6 is a diagram showing a configuration of a receiving circuit of an integrated circuit according to the third embodiment of the present invention. The receiving circuit includes a receiving coil 31, resistors 32 and 33, transistors 34 to 46, NAND circuits 47 and 48, and inverters 49 and 50, and constitutes a comparator with a latch as a whole. A reception clock (synchronization signal) Rxclk is taken from the outside, and reception data Rxdata is output. Transistors 36 and 37 form a differential pair of a differential amplifier and receive a signal VR from the receiving coil 31. NAND circuits 47 and 48 form a latch. Data received by the differential amplifier is sampled in synchronization with the reception clock Rxclk input to the transistors 34, 43, and 46, latched by the NAND circuits 47 and 48, and the reception signal Rxdata is restored. The transistors 35, 38, and 39 function in the same manner as the transistors 13, 16, and 17 in FIG. 3 (b), and the differential input threshold value has hysteresis characteristics as shown by the dotted line in FIG. 5 (b). When the same transmission data continues, the transmission pulse current does not change and the reception pulse signal is not induced, so that the synchronous receiver does not malfunction at that time.

　図７は、本発明の実施例４による集積回路の送信側の構成を示す図である。図７(a)は回路図であり、図７(b)は動作波形を示す。回路は、実施例１に加えて、インバータ遅延線５１、ＮＡＮＤ回路５２、及びインバータ５３から成り、送信クロックＴxclkの立ち上がりエッジに同期して、インバータ遅延線５１の伝播遅延で決定されるパルス幅のパルスＴxpを発生するパルス発生回路、送信クロックＴxclkに同期して送信データＴxdataに応じたデータ信号Ｑ及びその反転信号を出力するフリップフロップ５４、ＮＡＮＤ回路５５、５６、及びインバータ５７、５８を備える。本実施例は、送信コイルに流れる電流をパルス状にしている。直流電流が流れた実施例１～実施例３と比べると、送信回路の消費電力を大幅に低減できる。同じ送信データＴxdataが続いて送信される場合も、毎回送信パルスを送信するので、そのタイミングに同期してデータを受信すれば、雑音に強くなり、受信器にヒステリシスを持たせる必要がなくなる。 FIG. 7 is a diagram showing the configuration of the transmission side of the integrated circuit according to the fourth embodiment of the present invention. FIG. 7A is a circuit diagram, and FIG. 7B shows operation waveforms. The circuit includes an inverter delay line 51, a NAND circuit 52, and an inverter 53 in addition to the first embodiment, and has a pulse width determined by the propagation delay of the inverter delay line 51 in synchronization with the rising edge of the transmission clock Txclk. A pulse generation circuit that generates a pulse Txp, a flip-flop 54 that outputs a data signal Q corresponding to transmission data Txdata and its inverted signal in synchronization with the transmission clock Txclk, NAND circuits 55 and 56, and inverters 57 and 58 are provided. In this embodiment, the current flowing through the transmission coil is pulsed. Compared with the first to third embodiments in which a direct current flows, the power consumption of the transmission circuit can be greatly reduced. Even when the same transmission data Txdata is subsequently transmitted, a transmission pulse is transmitted every time. Therefore, if data is received in synchronization with the timing, it becomes strong against noise and it is not necessary to provide the receiver with hysteresis.

　図８は、本発明の実施例４による集積回路の受信回路の構成を示す図である。受信回路は、受信コイル６１、抵抗６２、６３、トランジスタ６４～７３、ＮＡＮＤ回路７４、７６、及びインバータ７６、７７から成り、全体としてラッチつき比較器を構成している。外部から受信クロック（同期信号）Ｒxclkをとり、受信データＲxdataを出力する。トランジスタ６５、６６が差動アンプの差動対をなし、受信コイル６１からの信号ＶRを受ける。ＮＡＮＤ回路７４、７５はラッチを形成している。差動アンプで受信したデータはトランジスタ６４、７０、７３へ入力される受信クロックＲxclkに同期してサンプリングされ、ＮＡＮＤ回路７４、７５によりラッチされ、受信信号Ｒxdataが復元される。送信データが０のときの受信パルスのタイミングと、送信データが１のときの受信パルスのタイミングを揃える必要がある。すなわち、送信クロックＴxclkの信号立ち上がりから、ＶX+及びＶX-の信号立ち上がりまでの経路の信号遅延を揃える必要がある。図７の回路では、両信号経路が同じ回路で構成されているので、信号を揃えることが容易にできる。また、この回路では、ｉT+とｉT-が相補でない。したがって、コイルのインダクタンスは１／４の２.５ｎＨにしか見えない。その結果、受信信号電圧は実施例１～実施例３に対して半分になる。しかし、送信電流を２倍にすれば、受信信号電圧を等しくすることができる。その場合でも、実施例１や実施例２に比べて送信電力を小さくすることができる可能性がある。 FIG. 8 is a diagram illustrating a configuration of a receiving circuit of an integrated circuit according to the fourth embodiment of the present invention. The receiving circuit includes a receiving coil 61, resistors 62 and 63, transistors 64 to 73, NAND circuits 74 and 76, and inverters 76 and 77, and constitutes a comparator with a latch as a whole. A reception clock (synchronization signal) Rxclk is taken from the outside, and reception data Rxdata is output. Transistors 65 and 66 form a differential pair of a differential amplifier, and receive signal VR from receiving coil 61. NAND circuits 74 and 75 form a latch. Data received by the differential amplifier is sampled in synchronization with the reception clock Rxclk input to the transistors 64, 70, and 73, latched by the NAND circuits 74 and 75, and the reception signal Rxdata is restored. It is necessary to align the timing of the reception pulse when the transmission data is 0 and the timing of the reception pulse when the transmission data is 1. That is, it is necessary to align signal delays in the path from the rising edge of the transmission clock Txclk to the rising edges of the VX + and VX− signals. In the circuit of FIG. 7, since both signal paths are formed of the same circuit, signals can be easily aligned. In this circuit, iT + and iT− are not complementary. Therefore, the inductance of the coil can only be seen as 2.5nH, which is 1/4. As a result, the received signal voltage is halved compared to the first to third embodiments. However, if the transmission current is doubled, the reception signal voltage can be made equal. Even in that case, there is a possibility that the transmission power can be reduced as compared with the first and second embodiments.

　図９は、本発明の実施例５による集積回路の送信側の構成を示す図である。本実施例は、実施例４と同じ動作をより簡素に実現するものであり、インバータ遅延線８１、ＮＡＮＤ回路８２、及びインバータ８３から成るパルス発生回路が発生するパルスＴxpをトランジスタ８５のゲートに入力する。これにより、実施例４と比べて、周辺回路をより簡単にすることができる。 FIG. 9 is a diagram showing the configuration of the transmission side of the integrated circuit according to the fifth embodiment of the present invention. In the present embodiment, the same operation as that of the fourth embodiment is realized more simply, and the pulse Txp generated by the pulse generation circuit including the inverter delay line 81, the NAND circuit 82, and the inverter 83 is input to the gate of the transistor 85. To do. Thereby, the peripheral circuit can be simplified as compared with the fourth embodiment.

　図１０は、本発明の実施例６による集積回路の送信側の構成を示す図である。図１０(a)は回路図、図１０(b)は送信コイルのレイアウト図である。図１１に動作波形を示す。回路は、送信コイルＬ3とＮＭＯＳＴ3を電源とアースの間に直列に接続し、送信コイルＬ4とＰＭＯＳＴ4とを電源とアースの間に直列に接続し、送信データをＮＭＯＳＴ3とＰＭＯＳＴ4のゲートに入力するものである。本実施例は、機能的には、実施例１と同じであるが、図３(a)に示したような位相反転回路が不要であり、その分、レイアウト面積が小さくなり、回路の消費電力も低くなる。 FIG. 10 is a diagram showing the configuration of the transmission side of the integrated circuit according to the sixth embodiment of the present invention. FIG. 10A is a circuit diagram, and FIG. 10B is a layout diagram of the transmission coil. FIG. 11 shows operation waveforms. The circuit connects the transmission coil L3 and NMOST3 in series between the power supply and ground, connects the transmission coil L4 and PMOST4 in series between the power supply and ground, and inputs transmission data to the gates of NMOST3 and PMOST4. It is. Although this embodiment is functionally the same as the embodiment 1, the phase inversion circuit as shown in FIG. 3A is unnecessary, and the layout area is reduced accordingly, and the power consumption of the circuit is reduced. Also lower.

　図１２は、本発明の実施例７による集積回路の送信側の構成を示す図である。本実施例は、実施例６に対して、実施例２と同じ趣旨で、送信機能を使わないとき（スタンバイ時）は電流が流れないようにしたものである。ＮＯＲ回路８７、８８に送信データＴxdata及びstandby信号又はその反転信号を入力することにより、standby信号がオンのときにＮＭＯＳＴ3とＰＭＯＳＴ4の両方をオフにする。これにより、データを一気にバースト転送した後にスタンバイ状態にすれば、送信回路の消費電力を有効に低下できる。 FIG. 12 is a diagram showing the configuration of the transmission side of the integrated circuit according to the seventh embodiment of the present invention. The present embodiment is the same as the second embodiment with respect to the sixth embodiment, and prevents the current from flowing when the transmission function is not used (in standby mode). By inputting the transmission data Txdata and the standby signal or its inverted signal to the NOR circuits 87 and 88, both the NMOS T3 and the PMOS T4 are turned off when the standby signal is on. As a result, the power consumption of the transmission circuit can be effectively reduced by setting the standby state after burst transfer of data at once.

　図１３は、本発明の実施例８による集積回路の送信側の構成を示す図である。図１４に動作波形を示す。本実施例は、送信コイルにＣＭＯＳの貫通電流を流すものである。回路は、送信コイルＬ1、Ｌ2、フリップフロップ９１、トランジスタ９２～９６、Ｔ5～Ｔ8、インバータ９７～９９を備える。その動作は、まずreset信号がオフになることで動作が始まり、送信データＴxdataに対して送信クロックＴxclkに同期した信号Ｑが０から１になると、Ａが０から１になり、Ｖx+が１から０になる。つぎに、信号Ｑが１から０になると、Ｂが１から０になり、Ｃが１から０になり、Ｖx-が０から１になる。以下、信号Ｑが０から１に変化する度に、Ｖx+の電位を交互に反転させ、信号Ｑが１から０に変化する度に、Ｖx-の電位を交互に反転させる。Ｖx+の電位が反転する度に、貫通電流ＩT+が流れ、Ｖx-の電位が反転する度に、貫通電流ＩT-が流れる。この貫通電流は短いパルス状になるので、送信電流の消費を小さくできる。これにより受信コイルでは信号Ｑの論理遷移に対して交互に位相が反転する双極性のパルスが誘起され、受信信号Ｒxdataが復元される。一方、信号Ｑが０から１になるときには、Ｖx-の電位が接地からＶDDになる場合とＶDDから接地になる場合があるが、いずれの場合もその結果生じる受信パルスのタイミングが等しくなるように送信回路の信号伝播を設計する必要がある。同様に信号Ｑが１から０になるときも、０から１になるときと等しいタイミングで受信パルスが得られるように設計する必要がある。 FIG. 13 is a diagram showing the configuration of the transmission side of the integrated circuit according to the eighth embodiment of the present invention. FIG. 14 shows operation waveforms. In this embodiment, a CMOS through current is passed through the transmission coil. The circuit includes transmission coils L1 and L2, a flip-flop 91, transistors 92 to 96, T5 to T8, and inverters 97 to 99. The operation starts when the reset signal is turned off. When the signal Q synchronized with the transmission clock Txclk with respect to the transmission data Txdata changes from 0 to 1, A changes from 0 to 1, and Vx + changes from 1. 0. Next, when the signal Q goes from 1 to 0, B goes from 1 to 0, C goes from 1 to 0, and Vx- goes from 0 to 1. Thereafter, the potential of Vx + is alternately inverted whenever the signal Q changes from 0 to 1, and the potential of Vx− is alternately inverted whenever the signal Q changes from 1 to 0. A through current IT + flows whenever the potential of Vx + is inverted, and a through current IT− flows whenever the potential of Vx− is inverted. Since this through current has a short pulse shape, the consumption of the transmission current can be reduced. As a result, a bipolar pulse whose phase is alternately inverted with respect to the logical transition of the signal Q is induced in the reception coil, and the reception signal Rxdata is restored. On the other hand, when the signal Q is changed from 0 to 1, the potential of Vx− may be changed from ground to VDD and may be changed from VDD to ground. It is necessary to design the signal propagation of the transmission circuit. Similarly, when the signal Q changes from 1 to 0, it is necessary to design so that the received pulse can be obtained at the same timing as when the signal Q changes from 0 to 1.

　図１５は、本発明の実施例８による集積回路の送信側の構成を示す図である。図１６に動作波形を示す。本実施例は、フリップフロップ１０１、ＮＡＮＤ回路１０２、及びＮＯＲ回路１０３を用いて、実施例７の周辺回路をより簡素にしたものである。本実施例は、貫通電流ＩT+、ＩT-が頻繁に発生するが、送信クロックTxclkからVx+及びVx-への信号伝播を等しく設計し易いという利点もある。
　なお、本発明は上記実施例に限定されるものではない。 FIG. 15 is a diagram illustrating the configuration of the transmission side of the integrated circuit according to the eighth embodiment of the present invention. FIG. 16 shows operation waveforms. In this embodiment, the flip-flop 101, the NAND circuit 102, and the NOR circuit 103 are used to simplify the peripheral circuit of the seventh embodiment. This embodiment frequently generates through currents IT + and IT−, but also has an advantage that signal propagation from the transmission clock Txclk to Vx + and Vx− can be easily designed equally.
In addition, this invention is not limited to the said Example.

　明細書、特許請求の範囲及び図面を含む２００９年　９月１５日に出願の日本特許出願２００９－２１３３４４の開示は、そのまま参考として、ここにとり入れるものとする。
　本明細書で引用したすべての刊行物、特許及び特許出願は、そのまま参考として、ここにとり入れるものとする。 The disclosure of Japanese Patent Application No. 2009-213344 filed on September 15, 2009, including the specification, claims and drawings, is incorporated herein by reference as it is.
All publications, patents and patent applications cited herein are hereby incorporated by reference in their entirety.

　Ｌ1～Ｌ4、Ｌ11、Ｌ12　送信コイル
　Ｔ1～Ｔ8、Ｔ11～Ｔ16　トランジスタ
　２６、５４、８４、９１、１０１　フリップフロップ
　３１、６１　受信コイル
　１９、２０、３２、３３、６２、６３　抵抗
　３４～４６、６４～７３、８５、９２～９６　トランジスタ
　５１、８１　インバータ遅延線
  L1-L4, L11, L12 Transmitting coils T1-T8, T11-T16 Transistors 26, 54, 84, 91, 101 Flip-flops 31, 61 Receiving coils 19, 20, 32, 33, 62, 63 Resistors 34-46, 64 73, 85, 92-96 Transistor 51, 81 Inverter delay line

Claims (7)

　基板上の配線により形成される第１及び第２送信コイルと、
　該第１及び第２送信コイルに送信信号に応じた単極性の電流を流す送信回路と
を有する第１基板と、
　基板上の配線により形成され、前記単極性の電流が流れる前記第１及び第２送信コイルに対して、逆極性にそれぞれと誘導結合する受信コイルと、
　該受信コイルに接続され、前記送信信号に応じた受信信号を得る受信回路と
を有する第２基板と
を備えることを特徴とする集積回路。 First and second transmission coils formed by wiring on a substrate;
A first substrate having a transmission circuit for passing a unipolar current corresponding to a transmission signal to the first and second transmission coils;
A receiving coil that is formed by wiring on a substrate and that is inductively coupled to each of the first and second transmitting coils through which the unipolar current flows;
An integrated circuit comprising: a second substrate having a reception circuit connected to the reception coil and obtaining a reception signal corresponding to the transmission signal. 　前記第１及び第２送信コイルは、それぞれ第１及び第２ＮＭＯＳのドレインに接続されていることを特徴とする請求項１記載の集積回路。 The integrated circuit according to claim 1, wherein the first and second transmission coils are connected to drains of first and second NMOSs, respectively. 　前記第１及び第２送信コイルの内、一方はＮＭＯＳのドレインに接続されており、他方はＰＭＯＳのドレインに接続されていることを特徴とする請求項１記載の集積回路。 2. The integrated circuit according to claim 1, wherein one of the first and second transmitting coils is connected to the drain of the NMOS and the other is connected to the drain of the PMOS. 　前記第１及び第２送信コイルは、それぞれ第１及び第２ＣＭＯＳの相補のトランジスタ間に接続されていて、該ＣＭＯＳの貫通電流が流れることを特徴とする請求項１記載の集積回路。 The integrated circuit according to claim 1, wherein the first and second transmission coils are connected between complementary transistors of the first and second CMOS, respectively, and a through current of the CMOS flows. 　前記送信回路は、前記単極性の電流を、前記第１及び第２送信コイルにおいて互いに相補的に時間変化するように流すことを特徴とする請求項１乃至４いずれかに記載の集積回路。 The integrated circuit according to any one of claims 1 to 4, wherein the transmission circuit allows the unipolar current to flow in the first and second transmission coils so as to change in time complementary to each other. 　前記送信回路は、前記単極性の電流を、前記第１又は第２送信コイルの内、前記送信信号に応じたいずれか一方に流すことを特徴とする請求項１乃至４いずれかに記載の集積回路。 5. The integrated circuit according to claim 1, wherein the transmission circuit causes the unipolar current to flow through one of the first and second transmission coils according to the transmission signal. 6. circuit. 　前記送信回路は、通信を休止するスタンバイ時に、前記第１及び第２送信コイルのいずれにも前記単極性の電流を流さないことを特徴とする請求項１乃至６いずれかに記載の集積回路。
  The integrated circuit according to claim 1, wherein the transmission circuit does not allow the unipolar current to flow through any of the first and second transmission coils during standby in which communication is suspended.
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WO1998032247A1 (en) * 1997-01-22 1998-07-23 Advantest Corporation Optical pulse transmission system, optical pulse transmitting method, and optical pulse detecting method
JP2003523147A (en) * 2000-02-14 2003-07-29 アナログ デバイセス インコーポレーテッド Isolators that send logic signals through an isolation barrier

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WO1998032247A1 (en) * 1997-01-22 1998-07-23 Advantest Corporation Optical pulse transmission system, optical pulse transmitting method, and optical pulse detecting method
JP2003523147A (en) * 2000-02-14 2003-07-29 アナログ デバイセス インコーポレーテッド Isolators that send logic signals through an isolation barrier

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