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WO2011022079A3 - Système et procédé de stockage d'informations en mémoire cache - Google Patents

Système et procédé de stockage d'informations en mémoire cache Download PDF

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Publication number
WO2011022079A3
WO2011022079A3 PCT/US2010/002317 US2010002317W WO2011022079A3 WO 2011022079 A3 WO2011022079 A3 WO 2011022079A3 US 2010002317 W US2010002317 W US 2010002317W WO 2011022079 A3 WO2011022079 A3 WO 2011022079A3
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WO
WIPO (PCT)
Prior art keywords
item
cache
duration
stored
subject
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2010/002317
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English (en)
Other versions
WO2011022079A2 (fr
WO2011022079A4 (fr
Inventor
Timo Burkard
David Presotto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Google LLC
Original Assignee
Google LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Google LLC filed Critical Google LLC
Priority to EP10810295.5A priority Critical patent/EP2467784B1/fr
Priority to CN201080047230.3A priority patent/CN102576350B/zh
Priority to JP2012525535A priority patent/JP5592489B2/ja
Priority to AU2010284682A priority patent/AU2010284682B2/en
Priority to EP16188263.4A priority patent/EP3125131B1/fr
Priority to EP20178341.2A priority patent/EP3722962B1/fr
Priority to CA2771599A priority patent/CA2771599C/fr
Priority to DK10810295.5T priority patent/DK2467784T3/en
Publication of WO2011022079A2 publication Critical patent/WO2011022079A2/fr
Publication of WO2011022079A3 publication Critical patent/WO2011022079A3/fr
Publication of WO2011022079A4 publication Critical patent/WO2011022079A4/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/122—Replacement control using replacement algorithms of the least frequently used [LFU] type, e.g. with individual count value
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/50—Network services
    • H04L67/56—Provisioning of proxy services
    • H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
    • H04L67/5683—Storage of data provided by user terminals, i.e. reverse caching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/26—Using a specific storage system architecture
    • G06F2212/264—Remote server
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7209—Validity control, e.g. using flags, time stamps or sequence numbers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Information Transfer Between Computers (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)

Abstract

L'invention concerne un système (100) et un procédé (Figures 5-6), dans lesquels, sous un aspect, une information demandée actuellement (143) est stockée dans une mémoire cache (140) sur la base de savoir si elle a ou non été préalablement requise et, dans l'affirmative, le moment de la requête précédente. Si l'information n'a pas été été préalablement requise, elle ne peut pas être stockée dans la mémoire cache. Si l'information en objet a été préalablement requise, elle peut ou non être stockée dans la mémoire cache sur la base d'une comparaison de durées, à savoir (1) la durée entre la requête courante et la requête précédente, pour l'information en objet et (2) pour chaque autre information dans la mémoire cache, la durée entre la requête courante et la requête précédente pour l'autre information. Si la durée associée à l'information en objet est inférieure à la durée de l'autre information dans la mémoire cache, l'information en objet peut être stockée dans la mémoire cache.
PCT/US2010/002317 2009-08-21 2010-08-20 Système et procédé de stockage d'informations en mémoire cache Ceased WO2011022079A2 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
EP10810295.5A EP2467784B1 (fr) 2009-08-21 2010-08-20 Système et procédé de stockage d'informations en mémoire cache
CN201080047230.3A CN102576350B (zh) 2009-08-21 2010-08-20 高速缓存信息的系统及方法
JP2012525535A JP5592489B2 (ja) 2009-08-21 2010-08-20 キャッシング情報のシステム及び方法
AU2010284682A AU2010284682B2 (en) 2009-08-21 2010-08-20 System and method of caching information
EP16188263.4A EP3125131B1 (fr) 2009-08-21 2010-08-20 Système et procédé de mise en antémémoire d'informations
EP20178341.2A EP3722962B1 (fr) 2009-08-21 2010-08-20 Système et procédé de mise en antémémoire d'informations
CA2771599A CA2771599C (fr) 2009-08-21 2010-08-20 Systeme et procede de stockage d'informations en memoire cache
DK10810295.5T DK2467784T3 (en) 2009-08-21 2010-08-20 System and method of caching information

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/545,225 2009-08-21
US12/545,225 US8566531B2 (en) 2009-08-21 2009-08-21 System and method of selectively caching information based on the interarrival time of requests for the same information

Publications (3)

Publication Number Publication Date
WO2011022079A2 WO2011022079A2 (fr) 2011-02-24
WO2011022079A3 true WO2011022079A3 (fr) 2011-06-16
WO2011022079A4 WO2011022079A4 (fr) 2011-08-11

Family

ID=43606203

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/002317 Ceased WO2011022079A2 (fr) 2009-08-21 2010-08-20 Système et procédé de stockage d'informations en mémoire cache

Country Status (10)

Country Link
US (7) US8566531B2 (fr)
EP (3) EP3125131B1 (fr)
JP (2) JP5592489B2 (fr)
CN (2) CN102576350B (fr)
AU (1) AU2010284682B2 (fr)
CA (3) CA2771599C (fr)
DE (1) DE202010018478U1 (fr)
DK (3) DK2467784T3 (fr)
FI (1) FI3722962T3 (fr)
WO (1) WO2011022079A2 (fr)

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Also Published As

Publication number Publication date
DK2467784T3 (en) 2016-11-21
CA2942418A1 (fr) 2011-02-24
US20140214999A1 (en) 2014-07-31
US8825961B2 (en) 2014-09-02
US20140047191A1 (en) 2014-02-13
CA2942418C (fr) 2019-03-12
EP3722962A1 (fr) 2020-10-14
EP3125131A3 (fr) 2017-05-31
US20140047171A1 (en) 2014-02-13
AU2010284682B2 (en) 2015-05-07
US9104605B1 (en) 2015-08-11
EP3125131A2 (fr) 2017-02-01
US8904116B2 (en) 2014-12-02
JP5592489B2 (ja) 2014-09-17
CN102576350B (zh) 2015-05-27
US20110302362A1 (en) 2011-12-08
US8566531B2 (en) 2013-10-22
EP2467784A4 (fr) 2014-09-10
JP5814436B2 (ja) 2015-11-17
CA3026715C (fr) 2021-03-02
CA3026715A1 (fr) 2011-02-24
US20110047317A1 (en) 2011-02-24
DE202010018478U1 (de) 2016-12-29
EP2467784A2 (fr) 2012-06-27
JP2014211909A (ja) 2014-11-13
WO2011022079A2 (fr) 2011-02-24
FI3722962T3 (fi) 2024-12-03
CN102576350A (zh) 2012-07-11
CA2771599C (fr) 2016-11-01
US8572327B2 (en) 2013-10-29
US20140040559A1 (en) 2014-02-06
CA2771599A1 (fr) 2011-02-24
DK3722962T3 (da) 2025-01-06
JP2013502641A (ja) 2013-01-24
WO2011022079A4 (fr) 2011-08-11
DK3125131T3 (da) 2020-10-12
AU2010284682A1 (en) 2012-04-12
EP2467784B1 (fr) 2016-10-19
US8825960B2 (en) 2014-09-02
US8812791B2 (en) 2014-08-19
CN104915319A (zh) 2015-09-16
CN104915319B (zh) 2018-06-01
EP3125131B1 (fr) 2020-07-15
EP3722962B1 (fr) 2024-10-09

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