WO2011013042A1

WO2011013042A1 - Germanium n-mosfet devices and production methods

Info

Publication number: WO2011013042A1
Application number: PCT/IB2010/053354
Authority: WO
Inventors: Daniele Caimi; Athanasios Dimoulas; Jean Fompeyrine; Chiara Marchiori; Christophe P. Rossel; Marilyne Sousa; Axelle M. Tapponnier; David J. Webb
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 2009-07-29
Filing date: 2010-07-23
Publication date: 2011-02-03
Anticipated expiration: 2012-01-29

Abstract

An n-MOSFET device (11) has an n-type channel (2) between a substrate (1) and a gate structure (7, 8), the channel (2) being formed by a layer of n-doped germanium of a thickness such that the channel (2) is fully-depleted with no applied gate voltage whereby the device (11) is operative in accumulation mode. The germanium channel can be δ-doped with n-dopant and can be formed with a δ-doped buried layer (3) of n-dopant.

Description

GERMANIUM N-MOSFET DEVICES AND PRODUCTION METHODS

This invention relates to germanium n-MOSFET (metal-oxide-semiconductor field effect transistor) devices, and to methods for producing such devices.

In order to continue CMOS (complementary metal oxide semiconductor)

downscaling, innovative device structures and new materials with higher charge carrier mobilities than silicon are desired. Germanium is one attractive candidate, having a charge carrier mobility of between two and three times that of silicon. Germanium p-MOSFETs, that is MOSFETs having a p-type germanium channel, have indeed been demonstrated to give improved performance compared to their Si-based counterparts. However, the corresponding n-channel device, the Ge n-MOSFET, remains a challenge.

Conventionally, Ge n-MOSFETs have always worked in inversion mode. This mode makes use of minority carriers to turn on the channel which is normally off with no applied gate voltage (i.e. zero gate voltage bias). In more detail, the channel is formed by applying a positive gate bias voltage to repel holes from a surface layer of bulk p-doped germanium. The resulting "inversion layer" is left n-type due to minority carriers. This inversion layer forms the n-type channel. These inversion mode MOSFET devices all underperform compared to the Si universal mobility curve (see Bai et al, Electron Device Letters, IEEE (2006); Saraswat et al, IEDM 2007 Proceedings, p723 (2007); Hennessy et al, IEEE 67^th DRC Proceedings, p257 (2009)). The cause of the poor performance of Ge n-MOSFETs is still under debate and a variety of explanations have been proposed. One suggestion is that, when a thin silicon interlayer is used between the Ge channel and the high-k dielectric of the gate structure, a high density of states in the upper part of the band gap (close to the conduction band) can lead to strong electron scattering, http://cis.stanford.edu/~saraswat/research.html (project description of PhD Shyam Sunder Raghunathan) suggests that mobility degradation due to poor quality of the Ge-dielectric interface might not be expected to occur in a depletion mode Ge n-MOSFET since carriers are physically separated from the interface. (A depletion mode device is a normally-on MOSFET (i.e. the channel is conductive with no applied gate voltage) in which the channel is formed in bulk n-type semiconductor and conductivity is modulated by applying a negative gate bias voltage to produce a depletion layer in the semiconductor surface which restricts the usable width of the channel). Another possible explanation for poor Ge n-MOSFET performance is that the charge neutrality levels for germanium, which lie close to the valence band, could make the interface difficult to invert. A further reason is that, because of the fast n-type dopant diffusion in germanium, the formation of a shallow-junction for source and drain contacts in the germanium n-channel is challenging. Finally, epilayers of Germanium always turn out to be unintentionally doped p- type because defects in germanium always act as electron acceptors.

Whatever the underlying reason, a complementary n-channel MOS technology using germanium-only has proved difficult to develop. International Patent Application publication no. WO 03/088360A1 proposes using a different crystal orientation and direction for a Ge n- FET and p-FET fabricated on the same wafer to optimize carrier transport in each device. However, for the 22nm technology node and beyond, circuits using two types of transistors are under serious consideration. While Germanium could be used for pFETs, strained-Si or even compound semiconductors would be used to fabricate nFETs. Such a solution presents drawbacks in terms of integration cost, technology complexity, and so on. A viable n- MOSFET in germanium is therefore still of interest.

One aspect of the present invention provides an n-MOSFET device having an n-type channel between a substrate and a gate structure, the channel being formed by a layer of n- doped germanium of a thickness such that the channel is fully-depleted with no applied gate voltage whereby the device is operative in accumulation mode.

By forming the channel as a thin Ge layer doped with n-dopant, embodiments of this invention offer efficient Ge n-MOSFET operation in the accumulation mode. In particular, unlike depletion mode operation, the Ge layer is thin enough that the channel is fully- depleted at zero applied gate voltage and so no current flows. The device is therefore off when no gate bias voltage is applied, as in conventional inversion mode devices. However, unlike inversion mode devices, when a gate bias is applied to switch the device on, the current flow is due to majority carriers. Compared to prior devices where the on/off characteristics are determined by properties of p-n junctions and interfaces in the

semiconductor, in embodiments of this invention the on/off characteristics can be highly efficiently tuned by controlling properties of the thin Ge channel layer. Effective Ge n- MOSFET operation can therefore be achieved while obviating problems associated with prior devices discussed above. Embodiments of the invention thus offer a viable solution for future integration based on complementary germanium p- and n-MOSFET devices.

In preferred embodiments, the germanium layer is formed by (5-doping germanium with n-dopant. (5-doping is a generally known technique for applying very small quantities of dopant in a very thin layer. Specifically, (5-doping applies a total amount of dopant which is equivalent to less than one monolayer of germanium taken in planes perpendicular to the crystal growth direction (in number of atoms/cm²). The (5-doping can be performed, for example, by interrupting deposition of the germanium layer, growing a (5-doped layer of n- dopant, and completing deposition of the germanium. The extent to which the dopant diffuses depends on the processing employed, and especially the application of heat, e.g. during deposition and annealing stages. In some embodiments the dopant could diffuse completely to give a substantially uniform doping profile. However, in preferred embodiments, a buried (5-doped layer of n-dopant is formed in the germanium. That is, the process is controlled such that diffusion of the n-dopant is limited, leaving a layer of n-dopant buried in the germanium layer. To this end, the Ge layer is preferably deposited using molecular beam epitaxy (MBE), since MBE techniques enable deposition at relatively low temperatures. The use of a buried (5-doped layer in the Ge channel has various advantages discussed further below. Moreover, while a single (5-doped buried layer is advantageous for some embodiments, for others it may be desirable to form a plurality of (5-doped buried layers of n-dopant in the germanium layer. This technique might be used, for example, to tune device characteristics. This will be discussed further below.

For effective operation, the thickness of the germanium layer should preferably be no more than about 50% of the depletion length for the germanium layer. (The depletion length is defined by a well-known standard scale according to the doping level of a given semiconductor and corresponds to the typical thickness of a depleted region which forms at the semiconductor surface (see S. Sze in "Physics of Semiconductor Devices", 2^nd Edition,

John Wiley & Sons, New York, 1981, pp84-126)) In preferred embodiments, the thickness of the germanium layer is ideally no more than about 20% of the depletion length for the germanium layer.

In general, the germanium layer may be formed directly or indirectly between the substrate and the gate structure. That is, the germanium layer may be contiguous with both the substrate and the gate structure or may be spaced from one or both of these structures by one or more intervening layers. The substrate and the gate structures themselves may have a composite layer structure. For example, the dielectric of the gate structure in particular may comprise a plurality of different material layers. In preferred embodiments, the gate structure comprises a high-K dielectric, composite or otherwise, and a metallic gate contact, typically a pure metal. A high- K dielectric may be defined according to an embodiment of the invention as a material having a high dielectric constant K as compared to silicon dioxide, in particular a dielectric constant of more than 3.9. In some embodiments, the substrate comprises a p- doped semiconductor, preferably germanium, or alternatively silicon or compound semiconductors such as gallium arsenide. In other embodiments the Ge channel may be formed on an insulating substrate. In a particularly preferred embodiment, the germanium channel layer is formed directly between the gate structure and substrate to provide a simple yet effective device structure.

Another aspect of the present invention provides a method for producing an accumulation mode n-MOSFET device. The method comprises:

producing an n-type channel for the device by forming a layer of n-doped germanium on a substrate;

forming a gate structure on the channel; and

forming source and drain structures for the device;

wherein the thickness of the germanium layer is such that the channel is fully- depleted with no applied gate voltage whereby the device is operative in accumulation mode.

The source and drain structures may comprise any desired structure functional as a source and drain respectively for the n-MOSFET. Each of these structures conventionally comprises at least an n+ doped region and a metallic contact.

In general, where features are described herein with reference to devices embodying the invention, corresponding features may be provided in methods embodying the invention, and vice versa.

Preferred embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings in which:

Figure 1 illustrates the channel formation in fabrication of a device embodying the invention;

Figure 2 illustrates a doping profile for the channel in Figure 1 ;

Figures 3a and 3b show capacitance- voltage measurements for channel structures like that of Figure 1 with an undoped germanium layer and an n-doped germanium layer respectively;

Figure 4 shows a Ge n-MOSFET embodying the invention; and

Figures 5 a and 5b illustrate energy band profiles for the Figure 4 device in the off- state and the on- state respectively.

Figure 1 is a schematic illustration of a fabrication stage for a Ge n-MOSFET embodying the invention. This diagram illustrates the channel formation. The first step in fabricating the Ge n-MOSFET is to prepare a substrate surface so that oxide or contaminant are removed. This can be done by standard wet cleaning processes or by vacuum thermal processes. The next step is to grow an epitaxial germanium channel. In this exemplary embodiment, the channel layer is formed by MBE on a p-type germanium substrate 1. An epitaxial layer 2 of germanium is deposited on the substrate 1 by MBE in ultra-high vacuum. The goal here is to keep the residual doping level as low as possible in the germanium epilayer. As mentioned earlier, epitaxial germanium is always residually p-doped because defects in germanium always act as electron acceptors. In the present case, the structural quality of the germanium layer is controlled so as to minimize the residual doping level as far as possible. The germanium is therefore "non-intentionally doped" (n.i.d.) as indicated in the figure.

Approximately half-way through formation of the Ge epilayer, the growth of germanium is interrupted. A precisely controlled amount of n-dopant is then applied to the Ge surface. In particular, a (5-doped layer 3 of n-dopant, in this example arsenic, is formed on the germanium. The (5-doping is performed in generally known manner, again by MBE in ultra-high vacuum. The amount of arsenic in the resulting (5-doped As layer 3 is less than that of one germanium monolayer. The precise density of As can be controlled as desired to give required device characteristics as discussed further below. Typically, however, the doping density will be substantially less than that of one monolayer, for example less than about 10% and more typically about 1%. In this preferred embodiment, the amount of arsenic will be less than 1% of a Ge monolayer.

Following arsenic deposition, growth of germanium layer 2 is resumed. The final Ge layer should be sufficiently thin to provide for transistor operation in accumulation mode as discussed further below. The thickness of the Ge layer should preferably be substantially less than the depletion length for germanium at the doping level employed, preferably no more than about 20% of the depletion length. By way of example, this preferred embodiment uses a Ge layer with a thickness of approximately 5nm.

The deposition process is also controlled in this example so as to limit diffusion of arsenic in the Ge layer 2. In particular, MBE techniques can be performed at low enough temperatures (e.g. in the region of room temperature) so that the As dopant does not completely diffuse through the Ge layer but remains substantially concentrated in and around application layer indicated by the broken line in Figure 1. The general form of the resulting doping profile is indicated to the right of this line in the figure. One possible example of such a profile is indicated schematically in Figure 2. As shown, residual doping of the n.i.d. Ge layer 2 leads to p-type germanium adjacent the upper and lower surfaces of layer 2, the doping changing sharply to n-type at (5-doped As layer 3. The result is an ultra-thin (5-doped layer of As which is buried in (i.e. spaced from the surfaces of) Ge layer 2. During subsequent annealing of the channel structure as described below, the temperature and duration of the annealing process is also controlled so as to limit further diffusion of As and substantially maintain the doping profile just described.

To demonstrate the effect of the As (5-doping, Figures 3 a and 3b show capacitance- voltage characteristics for channel structures corresponding generally to that of Figure 1, but with Figure 3 a showing results for a structure without the As dopant layer and Figure 3b showing results with the As dopant layer. More specifically, Figure 3 a shows the results obtained for a 108nm undoped (n.i.d.) p-type Ge epilayer deposited on a p-type Ge substrate, with a 5nm HfO₂ gate oxide layer and Pt gate electrode on the Ge epilayer. The n.i.d.

germanium layer shows typical p-type behaviour, the capacitance being greater for negative gate voltages as clearly shown in this figure. Figure 3b shows the corresponding results for a 5nm, As (5-doped Ge epilayer, deposited on a p-type Ge substrate. This structure was annealed in Nitrogen at 400⁰C for 30 minutes, and had an HfO₂ gate oxide layer and Pt gate electrode as before. The resulting capacitance- voltage characteristics clearly show n-type behaviour, the (5-doped arsenic layer having compensated for the residual p-dopants and added additional charge carriers to create a majority carrier n-type channel.

After formation of the channel structure described above, various further processing stages are performed to complete fabrication of the MOSFET structure as shown in Figure 4. Firstly, highly-doped n+ source and drain regions 4 and 5 are formed in the Ge channel by implantation or selective growth. Next, a high-K oxide layer 6, here Of HfO₂, is deposited by MBE, chemical- vapor deposition (CVD), atomic layer deposition (ALD) or other related techniques after masking-off regions for passage of the source and drain contacts. The portion OfHfO₂ layer 6 above Ge layer 2 thus provides the gate dielectric. The resulting structure is then annealed as described above, in this example for 30 minutes at 400 ⁰C in a nitrogen atmosphere. Finally, the gate contact 8, and source and drain contacts 9 and 10, are formed by appropriately masking the oxide surface and depositing a layer of metal, in this example Pt, by e-beam evaporation.

The resulting n-MOSFET 11 is operative in the accumulation mode. When no gate voltage is applied (gate bias Vgs = 0), the energy-band profile is as indicated schematically in Figure 5 a. The thin Ge channel layer is fully-depleted so the channel is non-conducting and the MOSFET 11 is in the off-state. When a positive gate bias above a threshold voltage V_T is applied, the depletion region is reduced sufficiently for the channel to conduct. The MOSFET 11 is thus switched on as indicated schematically by the energy-band profile of Figure 5b. MOSFET 11 thus works with majority carriers (electrons), the carriers being confined in the channel by the energy barrier at the interface between the substrate 1 and the Ge channel layer 2. At the other interface, the high-k insulator 7 provides a barrier for gate leakage reduction.

The device 11 provides a highly effective n-channel Ge-MOSFET working with majority carriers in accumulation mode. The delta-doped layer 3 provides carriers while keeping dopant-related defects at a low density level. In the example described, the As scattering sites remain substantially localized in buried layer 3. The thin (5-doped layer obtained using MBE allows very high doping gradients to be achieved as described above. Thus, a very thin n-dopant layer contained on either side by n.i.d. p-doped Ge can be made as close to the surface as desired. This is not possible with ion-implantation for instance. Since the channel is just below the surface, the disturbances caused by electrical defects at the surface are reduced and therefore the mobility improved. On the other hand, since the doping gradients are very abrupt, the conducting channel can still be placed close to the surface to allow maximum control by the gate voltage. The problem of poor surface passivation degrading the quality of the surface-inversion-layer in prior devices is also avoided.

Moreover, the characteristics of devices embodying the invention can be readily tuned by controlling the doping profile in the Ge epilayer and the workfunction of the gate electrode. In particular, the threshold voltage and device on/off characteristics can be adjusted as desired by varying the particular doping profile and the gate metal workfunction. Use of a high-workfunction metal such as Pt helps to maintain the off-state by reinforcing depletion of the channel at zero bias and ensuring that the threshold voltage is positive. Varying the material, density and distribution of n-dopant, as well as thickness of the Ge layer, enables adjustment to optimize the on/off characteristics of the device while preserving a desired threshold voltage. The (5-doping process allows doping to be controlled in general to fractions of 1% of a monolayer. Dopant distribution can be adjusted, for example, by controlling diffusion of dopants in the Ge layer and/or varying the depth of the buried layer described above.

Many changes and modifications can of course be made to the exemplary

embodiment described above. In some embodiments, for instance, two or more (5-doping layers may be formed in the Ge layer to produce a wide variety of doping profiles. This may be desired, for example, to optimise the threshold voltage and on/off characteristics of a particular device. In some embodiments, the n-dopant may be allowed to diffuse throughout the entire germanium epilayer creating an arsenic rich, n-doped Germanium. The diffusion may even be sufficient to produce a substantially uniform doping profile. The (5-doping layer could be deposited by other techniques such as CVD, and some embodiments may dope the Ge layer other than by (5-doping, though (5-doping is highly preferred for the reasons already discussed.

Deposition techniques other than MBE, e.g. CVD or other related techniques, could be used to form the channel structure in some embodiments.

Other semiconductors, such as Si and GaAs, could be used for the device substrate if desired. Moreover, in some embodiments the active Ge channel could be built on an insulator using GeOI (germanium-on-insulator) technology. The underlying insulator then provides a good barrier against off- state leakage currents allowing the channel to be turned off more effectively.

While arsenic is used as the n-dopant above, other electron donor materials may be employed in other embodiments. Phosphorous and antimony provide particular examples here. Where a buried (5-doped layer is to be formed as above, it will generally be desirable to use a dopant with a low diffusion coefficient in Ge. Phosphorus may prove even better than arsenic in this respect.

The particular order of the processing steps may be varied in some embodiments, and additional layers may be formed in the device structure if desired. Moreover, while a single Ge n-MOSFET has been described, in general a MOSFET device embodying the invention may consist of a single transistor or a transistor coupled with one or more other components, and in particular may comprise more than one coupled transistor.

It will be appreciated that many other changes and modifications can be made to the exemplary embodiments described without departing from the scope of the invention.

Claims

1. An n-MOSFET device (11) having an n-type channel (2) between a substrate (1) and a gate structure (7, 8), the channel (2) being formed by a layer of n-doped germanium of a thickness such that the channel (2) is fully-depleted with no applied gate voltage whereby the device (11) is operative in accumulation mode.

2. A device as claimed in claim 1 wherein the germanium layer is formed by (5-doping germanium with n-dopant.

3. A device as claimed in claim 2 wherein the germanium layer has a single (5-doped buried layer (3) of n-dopant.

4. A device as claimed in claim 2 wherein the germanium layer has a plurality of δ- doped buried layers (3) of n-dopant.

5. A device as claimed in any preceding claim wherein the n-dopant comprises one of arsenic, phosphorous and antimony.

6. A device as claimed in any preceding claim wherein the thickness of the germanium layer is no more than about 20% of the depletion length for the germanium layer.

7. A device as claimed in any preceding claim wherein the germanium layer is formed directly between the substrate (1) and the gate structure (7, 8).

8. A device as claimed in any preceding claim wherein the substrate (1) comprises one of: an insulator; p-doped germanium; p-doped silicon; and p-doped gallium arsenide.

9. A device as claimed in any preceding claim wherein the gate structure (7, 8) comprises a high-K dielectric (7) and a metallic gate contact (8).

10. A method for producing an accumulation mode n-MOSFET device (11), the method comprising: producing an n-type channel (2) for the device (11) by forming a layer of n-doped germanium on a substrate (1);

forming a gate structure (7, 8) on the channel (2); and

forming source and drain structures (4, 5) for the device (11);

wherein the thickness of the germanium layer is such that the channel (2) is fully- depleted with no applied gate voltage whereby the device (11) is operative in accumulation mode.

11. A method as claimed in claim 10 wherein the germanium layer is formed by (5-doping germanium with n-dopant.

12. A method as claimed in claim 11 including depositing the germanium layer by molecular beam epitaxy and forming a single (5-doped buried layer (3) of n-dopant in the germanium layer.

13. A method as claimed in claim 11 including depositing the germanium layer by molecular beam epitaxy and forming a plurality of (5-doped buried layers (3) of n-dopant in the germanium layer.

14. A method as claimed in any one of claims 10 to 13 wherein the n-dopant comprises one of arsenic, phosphorous and antimony.

15. A method as claimed in any one of claims 10 to 14 including forming the germanium layer with a thickness of no more than about 20% of the depletion length for the germanium layer.