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WO2011009413A1 - Procédé de gravure profonde de silicium - Google Patents

Procédé de gravure profonde de silicium Download PDF

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Publication number
WO2011009413A1
WO2011009413A1 PCT/CN2010/075435 CN2010075435W WO2011009413A1 WO 2011009413 A1 WO2011009413 A1 WO 2011009413A1 CN 2010075435 W CN2010075435 W CN 2010075435W WO 2011009413 A1 WO2011009413 A1 WO 2011009413A1
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WO
WIPO (PCT)
Prior art keywords
etching
deep silicon
plasma
etched surface
etched
Prior art date
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Ceased
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PCT/CN2010/075435
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English (en)
Chinese (zh)
Inventor
周洋
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Beijing NMC Co Ltd
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Beijing NMC Co Ltd
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Filing date
Publication date
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Publication of WO2011009413A1 publication Critical patent/WO2011009413A1/fr
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process

Definitions

  • the present invention relates to the field of plasma processing technology, and in particular, to a deep silicon etching method. Background technique
  • Microelectromechanical devices and Micro Electromechanical Systems are increasingly used in automotive and consumer electronics, as well as TSV (Through Silicon Via) through Silicon Etch technology.
  • TSV Thin Silicon Via
  • the deep silicon etching process has gradually become one of the most promising processes in the field of MEMS manufacturing and TSV technology.
  • the deep silicon etching process actually belongs to a plasma dry etching process. Compared with the general silicon etching process, the main difference is that the etching depth is much larger than the general silicon etching process.
  • a typical silicon etch process typically has an etch depth of less than 1 micron, while a deep silicon etch process has an etch depth of tens of microns or even hundreds of microns. Therefore, in order to obtain a good deep hole morphology, it is necessary to etch and remove a silicon material having a depth of several tens to hundreds of micrometers, which requires a deep etch process with a faster etch rate, a higher selectivity ratio, and a larger Aspect ratio.
  • the main features of the commonly used deep silicon etching process are as follows: The entire etching process is repeated for one etching unit, and the etching unit includes an etching step and a deposition step. In other words, the entire etching process is an etching step. And an alternating cycle of deposition steps.
  • the etching process of a typical deep silicon etching process is shown in FIGS. 1A to 1G, and FIG. 1A is an unetched state, and the silicon wafer 101 to be etched is covered with a patterned photoresist layer 102; FIG. 1B, FIG. FIG. 1F shows an etching step, FIG. 1C and FIG. 1E show a deposition step, an etching step and a deposition step constitute an etching unit, and FIG. 1G shows that after the etching unit is repeated a plurality of times The resulting deep hole 106 is shaped.
  • the process gas in the etching step is SF 6 , and the gas etching silicon wafer is very high. Etch rate, but since SF 6 is isotropic etching (Fig. 1C, 1E open circles represent the plasma particles) using a CF X other fluorine-containing process gas in subsequent deposition steps in A barrier layer 103 is formed during the etching to protect the sidewalls 104 to control sidewall morphology (ie, a large aspect ratio, less lateral etching); the barrier layer 103 is typically a plasma 110 and The polymer formed by the chemical reaction of the photoresist layer and/or the silicon material is used to prevent lateral etching in the etching step, thereby etching only in the direction of the vertical silicon wafer, and anisotropic etching is realized.
  • the process gas of the deep silicon etching process described above also introduces argon gas, and applies a bias voltage to the silicon wafer during the entire etching process, and the bias of the bias in the etching step makes the plasma have directivity.
  • the solid black circles in Fig. 1B, Fig. 1D and Fig. 1F indicate the particles in the ionic body, etc.
  • the plasma also acts on the photoresist layer under the action of a bias voltage. Etching causes a decrease in the etching selectivity of the photoresist layer.
  • the argon gas is used in the deposition step to form a bombardment effect of the argon plasma on the etched surface barrier layer 103a (see FIG. 1C) under the action of a bias voltage, thereby reducing polymer deposition on the etched surface, which is advantageous for engraving
  • the barrier layer 103a on the etched surface 105 is quickly opened to etch the underlying silicon, but on the other hand, due to the presence of a bias voltage, the plasma chemically reacts with the photoresist layer and/or the silicon material.
  • the polymer is also preferentially deposited on the etched surface 105, resulting in insufficient deposition of the sidewalls 104, which leads to lateral etching in the subsequent etching step, which increases the sidewall roughness, and etches the shape.
  • the appearance is difficult to control.
  • the argon plasma does not actually undergo an etch chemistry, the addition of argon bombardment in both the etching step and the deposition step results in a decrease in overall efficiency.
  • the etching step still uses SF 6 as a process gas, and the bias voltage of the silicon wafer is low frequency pulse power supply, and the power duty ratio is about 10%. ⁇ 90%, because the bias voltage applied by the low-frequency pulse power supply is intermittent, which is beneficial to the formation of anisotropic etching and avoids continuous bombardment of the photoresist layer, thereby effectively improving the etching of the photoresist layer.
  • Corrosion selectivity ratio at the same time, a faster etch rate can be obtained; the deposition step uses C 4 F 8 as the process gas, but does not bias the silicon wafer, which ensures the isotropy of polymer deposition and ensures sidewall deposition Sufficient barrier layer to avoid lateral etching caused by uneven barrier layer It is convenient to control the etching morphology.
  • the improved deep silicon etch process described above has a faster etch rate, a larger etch selectivity to the photoresist layer, and a better etch profile.
  • the present invention provides a deep silicon etching method, which first etches a surface of a silicon wafer not covered by a photoresist layer to form an etched surface and a sidewall substantially perpendicular to the etched surface, and further includes The following steps:
  • a deposition step performing isotropic deposition to cover the etched surface, the sidewall, and the surface of the photoresist layer;
  • a first etching step performing an anisotropic etching to remove the barrier layer covered on the etched surface to expose the etched surface, and the photoresist layer is protected by a barrier layer covered thereon without Etching;
  • a second etching step performing an isotropic etching to etch the exposed etched surface, the sidewall being protected by a barrier layer covered thereon without being etched, and the light The resist layer is not damaged in the isotropic etching;
  • the deposition step, the first etching step, and the second etching step are repeated cyclically until a predetermined etching depth is reached.
  • the process gas used in the deposition step includes C 4 F 8 .
  • the process gas used in the first etching step includes one or a combination of at least two of Ar, He, 0 2 and SF 6 .
  • both a plasma excitation source and a bias source are applied.
  • the process gas used in the second etching step includes SF 6 .
  • the barrier layer is a polymer that is produced by a chemical reaction of a plasma with an etched silicon wafer.
  • the bias source is a DC power source, and the bias source acts to cause the plasma to bombard the silicon wafer during the etching process.
  • the plasma processing apparatus for use in the process includes opposing upper and lower plates, the plasma excitation source being applied through the upper plate, and the bias source being applied through the lower plate.
  • the method comprises an etching unit consisting of three steps of a deposition step, a first etching step and a second etching step, and the etching unit is repeatedly executed throughout the etching process until a predetermined etching depth is reached.
  • the etched surface does not deposit too much barrier layer.
  • the isotropic etching is performed in the second etching step to etch the exposed etched surface, so that the depth of the etched surface is increased, and the sidewall is protected by the barrier layer covered thereon without being etched.
  • the photoresist layer is not damaged in the isotropic etching.
  • the deposition step, the first etching step and the second etching step can be completed in a conventional plasma processing apparatus, and a larger selection ratio to the photoresist layer and a faster etching rate are achieved. And better sidewall protection, no need to use complex equipment such as low-frequency pulse power supply, which is conducive to equipment maintenance and reduce equipment costs.
  • FIGS. 1A to 1G are schematic views showing an etching process of a typical deep silicon etching process
  • FIG. 2 is a flow chart of a deep silicon etching method according to an embodiment of the present invention.
  • FIG. 3A to 3F are schematic views showing a deep silicon etching method according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a plasma processing apparatus used in a deep silicon etching method according to an embodiment of the present invention.
  • the deep silicon etching process requires etching to remove silicon materials having a depth of several tens to hundreds of micrometers. In order to obtain a good deep hole or deep trench topography, the deep silicon etching process is required to have a larger selection ratio of the photoresist layer. Faster etch rate and better sidewall protection.
  • the inventors have found that in the current deep silicon etching process, the bias voltage of the silicon wafer is etched by the etching step using a low frequency pulse power source, and the deposition step is not biased, which is advantageous for forming anisotropic etching.
  • Avoiding continuous bombardment of the photoresist layer can effectively improve the etching selectivity ratio of the photoresist layer, and at the same time, can obtain a faster etching rate, thereby meeting the requirements of the deep silicon etching process.
  • the low frequency pulse power supply needs Connecting the lower electrode of the etch chamber provides a pulsed bias voltage to the plasma in the process chamber, so the overall structure is more complicated than the conventional DC bias power supply, which not only increases the equipment cost, but also gives Etching equipment Maintenance is inconvenient.
  • the present invention provides a deep silicon etching method, which can meet the process requirements without using a low frequency pulse power supply, that is, a larger selection ratio of the photoresist layer, a faster etching rate, and a better Side wall protection effect.
  • a low frequency pulse power supply that is, a larger selection ratio of the photoresist layer, a faster etching rate, and a better Side wall protection effect.
  • Step S1 etching a surface of a silicon wafer not covered by the photoresist layer to form an etched surface and a sidewall substantially perpendicular to the etched surface.
  • the etched surface is the main surface of the etch reaction, which is substantially parallel to the surface of the silicon wafer (horizontal plane) and is not covered by the photoresist layer, and the depth of the etched surface is gradually increased during the deep silicon etching process.
  • Step S2 a deposition step: performing isotropic plasma deposition to cover the surface of the etched surface, the sidewall, and the photoresist layer.
  • the barrier layer is, for example, a polymer which is removed by corrosion.
  • Step S3 a first etching step: performing an anisotropic plasma etching to remove the barrier layer covered on the etched surface to expose the etched surface, and the photoresist layer is covered thereon The barrier layer is protected from etching.
  • anisotropic plasma etching the plasma has a directionality perpendicular to the etched surface, and the etch rate on the horizontal plane is much greater than the etch rate on the vertical plane (e.g., sidewall).
  • Step S4 a second etching step: performing an isotropic plasma etching to etch the exposed etched surface, so that the depth of the etched surface is gradually increased, and the sidewall is blocked by the upper surface thereof.
  • the layer is protected from being etched, and since the etching is isotropic in this step, there is no direct effect on the photoresist layer, so the photoresist layer is not damaged in the isotropic etching.
  • Step S5 repeating the deposition step, the first etching step and the second etching step in sequence until the etching surface reaches a predetermined etching depth, thereby completing the entire deep silicon etching process.
  • FIG. 3A to 3F are schematic views of a deep silicon etching method in the embodiment;
  • FIG. 4 is a deep silicon engraving Schematic diagram of the plasma processing equipment used in the etching method.
  • a silicon wafer 300 is provided.
  • the silicon wafer 300 is covered with a photoresist layer 301 having an etched pattern 301a therein, so that the silicon wafer surface 300 forms an exposed region 300a.
  • the wafer surface 300a that is not covered by the photoresist layer.
  • the photoresist layer 301 can be fabricated by a conventional exposure and development process and will not be described in detail herein.
  • the plasma processing apparatus includes: a process chamber 201, an electrostatic chuck 203 and an inlet nozzle 204 located in the process chamber 201, and the silicon wafer to be processed is adsorbed and fixed by the electrostatic chuck 203.
  • the gas is input into the process chamber 201 by the inlet nozzle 204, and the inlet nozzle 204 is disposed opposite to the electrostatic chuck 203, and the process gas in the space between them is excited by the input power of the upper electrode (not shown).
  • the ionization forms a plasma 205, which also serves as a lower electrode for applying a bias voltage to the plasma.
  • the upper electrode is a system for generating plasma above the nozzle, and its position is close to the nozzle. In addition to the upper air intake, the nozzle can also use the lower air intake or the side air intake.
  • the silicon wafer 300 is transferred into the electrostatic chuck 203 in the process chamber 201, as shown in FIG. 3B and FIG. 2, referring to step S1, the etching is not covered by the photoresist layer.
  • the silicon wafer surface 300a is formed to form an etched surface 302 and a sidewall 303 that is substantially perpendicular to the etched surface 302.
  • the purpose of this step is to open the surface of the silicon wafer 300 to form an etched surface.
  • the etching in this step may be an isotropic plasma etch or an anisotropic plasma etch.
  • a deposition step is performed: performing isotropic plasma deposition to cover the surface of the etched surface 302, the sidewall 303, and the photoresist layer 301 with a barrier layer 304;
  • the process gas in the step is, for example, C 4 F 8 , and the process chamber 201 only adds the input power of the electrode, and the power range is 800 to 2500 W, and the lower electrode does not input the bias power, so that the upper electrode is applied.
  • the plasma 205a excited and maintained by the excitation source is isotropic, and acts on the surfaces of the etched surface 302, the sidewall 303 and the photoresist layer 301 to form the barrier layer 304.
  • the barrier layer 304 For example, a polymer produced by a chemical reaction between a plasma and an etched silicon wafer or photoresist layer is chemically stable and is not easily removed by etching. Hollow circle in Figure 3C The circle represents the particles in the plasma 205a.
  • the first etching step performing an anisotropic plasma etching to remove the barrier layer 304a covered on the etched surface 302 (see FIG. 3C).
  • the etched surface 302 is exposed, and the photoresist layer 301 is protected by the barrier layer 304c covered thereon without being etched; during anisotropic plasma etching, the plasma 205b has a perpendicular to the etched surface.
  • the directionality, the etch rate on the horizontal plane is much greater than the etch rate on the vertical plane (e.g., sidewall), so the barrier layer 304b overlying the sidewall 303 is also not etched away.
  • the solid black circle in Figure 3D represents the particles in the plasma 205b.
  • the process gas used in the first etching step includes one or at least two combinations of Ar, He, 0 2 and SF 6 in which both a plasma excitation source and a bias source are applied, for example, an upper electrode
  • the power range is 300 ⁇ 2500W
  • the lower electrode power is 30 ⁇ 500W
  • the bias source can be a DC power source.
  • the excitation source excites and maintains the plasma 205b
  • the bias source acts as a plasma.
  • 205b physically bombards the silicon wafer to form an anisotropic etch with directionality.
  • step S4 the second etching step: performing isotropic plasma etching to etch the exposed etched surface 302, so that the depth of the etched surface 302 is gradually increased.
  • the sidewall 303 is protected by the barrier layer 304b covered thereon without being etched, and since the etching is isotropic in this step, there is no direct effect on the photoresist layer 301, so the photoresist layer 301 is This isotropic etching is not damaged.
  • the process gas is, for example, SF 6
  • an excitation source is applied to the upper electrode in the process chamber 201, and the power range is 800 to 2500 W, and the lower electrode does not apply a bias source to realize the isotropic plasma.
  • step S5 sequentially repeating the deposition step (step S2), the first etching step (step S3), and the second etching step (step S4) until the etched surface 302 reaches The predetermined etching depth is removed, and the photoresist layer is removed to form deep holes 306 to complete the entire deep silicon etching process.
  • the upper electrode frequency is 13.56 MHz
  • the maximum power is 2500 W
  • the lower electrode frequency is 13.56 MHz
  • the maximum power is 1200 W.
  • a specific process parameter of the deep silicon etching method in the embodiment is: in the deposition step, the flow rate of the process gas 0 ⁇ 8 is 80sccm, the power of the upper electrode is 2500W, the pressure is 20mT, and the processing time is 5s; In the etching step, the flow rate of the process gas Ar is 50 sccm, the power of the upper electrode is 800 W, the power of the lower electrode is 80 W, the pressure of the lower electrode is 7 mT, and the treatment time is 3 s. In the second etching step, the flow rate of the process gas SF 6 is 200 sccm. The electrode power is 2500W, the pressure is 35mT, and the processing time is 12s.
  • Another specific process parameter of the deep silicon etching method in this embodiment is: in the deposition step, the flow rate of the process gas 0 ⁇ 8 is 80sccm, the power of the upper electrode is 2500W, the pressure is 20mT, and the processing time is 5s; In the etching step, the process gas 0 2 flow rate is 50 sccm, the upper electrode power is 400 W, the lower electrode power is 100 W, the pressure is 50 mT, and the processing time is 3 s; in the second etching step, the process gas SF 6 flow rate is 200 sccm, The electrode power is 2500W, the pressure is 35mT, and the processing time is 12s.
  • the process gas used in the first etching step may also be one or a combination of at least two of Ar, He, 0 2 and SF 6 .
  • the deposition step (step S2), the first etching step (step S3), and the second etching step (step S4) actually constitute an etching unit, and the etching is repeatedly performed.
  • the cell completes the entire deep silicon etch process.
  • the etched surface does not deposit too much barrier layer.
  • Isotropic etching in the second etching step to etch the exposed etched surface to make the engraving
  • the depth of the etched surface is increased, the sidewall is protected by the barrier layer overlying it without being etched, and the photoresist layer is not damaged during the isotropic etch.
  • the deposition step, the first etching step and the second etching step can be completed in a conventional plasma processing apparatus, achieving a larger selection ratio of the photoresist layer, a faster etching rate, and Better sidewall protection, eliminating the need for complex equipment such as low-frequency pulsed power supplies, which is beneficial to equipment maintenance and equipment cost reduction.
  • the etch process using the low frequency pulse bias still etches the photoresist layer in a gap manner, and in the second etching step of the method of the present invention
  • the isotropic plasma does not etch the photoresist layer, and the selection ratio of the photoresist layer can be further improved.
  • the above description is only a preferred embodiment of the invention and is not intended to limit the invention in any way. It should be noted that the above embodiment only shows the case of the silicon wafer covering the photoresist layer. Actually, the silicon wafer may further include an etch stop layer, an anti-reflection layer and a hard mask layer, and the like. The deep silicon etching method can be applied to achieve the object of the present invention.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

L'invention porte sur un procédé de gravure profonde de silicium comprenant d'abord la gravure d'une surface (300a) de silicium (300) non recouverte par une couche de résine photosensible (301) pour former une surface gravée (302) et des parois (303) pratiquement verticales par rapport à la surface gravée (302) et comprend en outre les étapes suivantes : une étape de dépôt qui est un dépôt isotrope; une première étape de gravure qui est une étape de gravure anisotrope; une seconde étape de gravure qui est une étape de gravure isotrope; et la répétition de façon cyclique de l'étape de dépôt, la première étape de gravure et la seconde étape de gravure jusqu'à ce qu'une profondeur de gravure prédéfinie soit atteinte. Le procédé ne nécessite pas l'utilisation d'un matériel complexe tel qu'une alimentation électrique pulsée basse fréquence ou similaire et facilite l'entretien du matériel et aide à réduire les coûts du matériel.
PCT/CN2010/075435 2009-07-24 2010-07-23 Procédé de gravure profonde de silicium Ceased WO2011009413A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN 200910089819 CN101962773B (zh) 2009-07-24 2009-07-24 一种深硅刻蚀方法
CN200910089819.9 2009-07-24

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