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WO2011087514A1 - Transistor en couches minces microcristallin à couche d'arrêt de gravure - Google Patents

Transistor en couches minces microcristallin à couche d'arrêt de gravure Download PDF

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Publication number
WO2011087514A1
WO2011087514A1 PCT/US2010/021323 US2010021323W WO2011087514A1 WO 2011087514 A1 WO2011087514 A1 WO 2011087514A1 US 2010021323 W US2010021323 W US 2010021323W WO 2011087514 A1 WO2011087514 A1 WO 2011087514A1
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WO
WIPO (PCT)
Prior art keywords
silicon layer
layer
etch stop
amorphous silicon
depositing
Prior art date
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Ceased
Application number
PCT/US2010/021323
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English (en)
Inventor
Helinda Nominanda
Tae Kyung Won
Soo Young Choi
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Applied Materials Inc
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Applied Materials Inc
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Filing date
Publication date
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Priority to PCT/US2010/021323 priority Critical patent/WO2011087514A1/fr
Priority to TW099103391A priority patent/TW201126613A/zh
Publication of WO2011087514A1 publication Critical patent/WO2011087514A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon

Definitions

  • Embodiments of the present invention generally relate to a thin film transistor (TFT) and methods for its fabrication.
  • TFT thin film transistor
  • LCDs Liquid Crystal Displays
  • TFTs have been used to separately address the pixels of the LCD at very fast rates.
  • the modern display panel there are millions of pixels which each are separately addressed by a corresponding TFT.
  • a bottom gate TFT contains a gate electrode formed over a substrate, a gate dielectric layer formed over the gate electrode, an active material layer such as microcrystalline silicon, a doped amorphous silicon layer as the ohmic contact, and source and drain electrodes.
  • the active material permits the current to pass from the source to the drain electrode whenever the gate electrode is turned on. Once the current passes to the drain electrode, the pixel is addressed.
  • the bottom gate TFT oftentimes has an etch stop structure over the active channel between the source and drain electrodes.
  • the etch stop structure is formed by depositing an etch stop material layer over the active material layer and then etching the etch stop material layer.
  • the etch stop material layer is etched, the underlying microcrystalline silicon layer may be damaged. The damage to the microcrystalline silicon layer may result in a high subthreshold slope for the TFT. [0005] Therefore, there is a need in the art for a bottom gate TFT having an etch stop structure that has a lower subthreshold slope.
  • the present invention generally relates to a TFT and methods for its fabrication.
  • Some TFTs have an etch stop structure formed thereon in the active channel.
  • the etch stop structure is formed by etching a layer of etch stop material. The etching may damage the underlying microcrystalline silicon material. By depositing an amorphous silicon layer over the microcrystalline silicon, the microcrystalline silicon may be protected from damage from the etching. Additionally, the doped amorphous silicon that is used as the ohmic contact may be tailored so that the resistivity is less than 1 ohm-cm. A hydrogen or nitrogen plasma treatment of the amorphous silicon layer may also be used to improve numerous characteristics of the TFT.
  • a TFT fabrication method includes depositing a first microcrystalline silicon layer over the gate dielectric layer, depositing an amorphous silicon layer over the first microcrystalline silicon layer and depositing an etch stop layer over the amorphous silicon layer. The method also includes etching the etch stop layer to form an etch stop structure and expose at least a portion of the amorphous silicon layer. The method also includes depositing a doped amorphous silicon layer over the amorphous silicon layer and the etch stop structure.
  • a metal contact layer may be deposited over the doped amorphous silicon layer, the metal contact layer may be etched to form a source electrode and a drain electrode and the doped amorphous silicon layer may be etched to form a first ohmic contact and a second ohmic contact and expose the etch stop structure.
  • a gate electrode may be formed over a substrate and a gate dielectric layer may be deposited over the gate electrode and the substrate.
  • a TFT fabrication method includes depositing a first microcrystalline silicon layer over the gate dielectric layer, depositing an etch stop layer over the first microcrystalline silicon layer, and etching the etch stop layer to form an etch stop structure.
  • the method also includes depositing a doped amorphous silicon layer over the first microcrystalline silicon layer and the etch stop structure.
  • the doped amorphous silicon layer has a resistivity of less than 1 ohm-cm.
  • a metal contact layer is deposited over the doped amorphous silicon layer, the metal contact layer is etched to form a source electrode and a drain electrode, and the doped amorphous silicon layer is etched to form a first ohmic contact and a second ohmic contact and expose the etch stop structure.
  • a gate electrode is formed over a substrate and a gate dielectric layer is deposited over the gate electrode and the substrate.
  • a TFT fabrication method includes depositing a first microcrystalline silicon layer over the gate dielectric layer, depositing an amorphous silicon layer over the first microcrystalline silicon layer and exposing the amorphous silicon layer to a plasma containing an element selected from the group consisting of hydrogen, nitrogen, and combinations thereof.
  • the method also includes depositing an etch stop layer over the first microcrystalline silicon layer, etching the etch stop layer to form an etch stop structure, and depositing a doped amorphous silicon layer over the etch stop structure.
  • a metal contact layer is deposited over the doped amorphous silicon layer, the metal contact layer is etched to form a source electrode and a drain electrode, and the doped amorphous silicon layer is etched to form a first ohmic contact and a second ohmic contact and expose the etch stop structure.
  • a gate electrode is formed over a substrate and a gate dielectric layer is deposited over the gate electrode and the substrate.
  • FIGS 1A-1G show a TFT 100 at various stages of production according to one embodiment.
  • FIG. 2 is a schematic cross sectional view of a TFT 200 according to another embodiment.
  • Figure 3 is a graph showing the drain current compared to the gate voltage applied for four separate TFTs.
  • Figure 4 is a graph showing the drain current compared to the gate voltage applied for two separate TFTs that have ohmic contact layers with different resistivities.
  • Figure 5 is a graph showing the drain current compared to the gate voltage applied for three separate TFTs having different plasma treatments.
  • the present invention generally relates to a TFT and methods for its fabrication.
  • Some TFTs have an etch stop structure formed thereon in the active channel.
  • the etch stop structure is formed by etching a layer of etch stop material. The etching may damage the underlying microcrystalline silicon material. By depositing an amorphous silicon layer over the microcrystalline silicon, the microcrystalline silicon may be protected from damage from the etching. Additionally, the doped amorphous silicon that is used as the ohmic contact may be tailored so that the resistivity is less than 1 ohm-cm. A hydrogen or nitrogen plasma treatment of the amorphous silicon layer may also be used to improve numerous characteristics of the TFT.
  • PECVD plasma enhanced chemical vapor deposition
  • Figures 1A-1G show a TFT 100 at various stages of production according to one embodiment.
  • the substrate 102 may comprise a semiconductor substrate.
  • the substrate 102 may comprise a silicon substrate.
  • the substrate 102 may comprise germanium.
  • a thermal oxide layer that serves as an insulating material may be present over the substrate.
  • the thermal oxide layer may be about 10,000 angstroms thick.
  • a gate electrode 104 is formed over the substrate (and thermal oxide layer).
  • the gate electrode 104 is formed by depositing a layer, forming a mask thereover, etching the layer and removing the mask to leave the gate electrode 104.
  • the gate electrode 104 may comprise a metal.
  • the gate electrode 104 may comprise a metal selected from the group consisting of chromium, molybdenum, copper, titanium, tungsten, aluminum, and combinations thereof.
  • the layer for producing the gate electrode 104 may be deposited by physical vapor deposition (PVD).
  • the layer for producing the gate electrode 104 may be deposited by evaporation.
  • the layer for producing the gate electrode 104 may be deposited by electroplating. It is to be understood that other deposition methods may be used to deposit the layer for producing the gate electrode 104.
  • the gate electrode 104 may have a thickness of between about 2000 Angstroms to about 3000 Angstroms.
  • a gate dielectric layer 106 is formed over the gate electrode 104.
  • the gate dielectric layer 106 may be deposited by PECVD.
  • the gate dielectric layer 106 may be deposited by other chemical vapor deposition (CVD) methods. It is to be understood that other deposition methods may be utilized to deposit the gate dielectric layer 106.
  • the gate dielectric layer 106 may comprise an insulating material.
  • the gate dielectric layer 106 may comprise silicon nitride.
  • the gate dielectric layer 106 may comprise silicon oxynitride.
  • the gate dielectric layer 106 may comprise silicon oxide.
  • the gate dielectric layer 106 may comprise silicon dioxide. In one embodiment, the gate dielectric layer 106 may have a thickness of between about 1000 Angstroms to about 6000 Angstroms. In another embodiment, the thickness of the gate dielectric layer 106 may be between about 2000 Angstroms and about 4000 Angstroms. In one embodiment, the gate dielectric layer 106 may comprise multiple layers. When multiple layers are used for the gate dielectric layer 106, one of the layers may be a high deposition rate material, such as silicon nitride with poor quality, and another of the layers may comprise a low deposition rate material, such as silicon nitride with high quality, to gain the throughput and the interface quality desired.
  • a microcrystalline silicon layer 108 may be deposited.
  • the microcrystalline silicon layer 108 may be deposited by PECVD. It is to be understood that the microcrystalline silicon layer 108 may be deposited by other deposition methods as well.
  • the microcrystalline silicon layer 108 may have a thickness of between about 300 Angstroms to about 3000 Angstroms.
  • the TFT will likely have a high subthreshold slope because of the etching of the etch stop layer.
  • the subthreshold slope may be lowered.
  • an amorphous silicon layer 110 may be deposited over the microcrystalline silicon layer 108.
  • the amorphous silicon layer 110 may be deposited by PECVD. It is to be understood that the amorphous silicon layer 110 may be deposited by other deposition methods as well.
  • the amorphous silicon layer 110 may have a thickness of between about 300 Angstroms to about 1000 Angstroms.
  • the amorphous silicon layer 110 significantly reduces the subthreshold slope and simultaneously improves the electrical performance of the TFT. Because the amorphous silicon layer 110 prevents the microcrystalline silicon layer 108 from exposure to the wet etching solution, damage to the microcrystalline silicon layer 108 is prevented.
  • an etch stop material layer 112 may be deposited thereover.
  • the etch stop material layer 112 may be formed by blanket depositing, followed by photoresist depositing, followed by pattern developing.
  • the etch stop material layer 112 may be patterned by wet etching to form an etch stop structure 114. It is to be understood that the etch stop material layer 112 may be etched by other etching methods such as dry or plasma etching.
  • the etch stop material layer 112 may comprise silicon nitride.
  • the etch stop material layer 112 may comprise silicon oxynitride.
  • the etch stop material layer 112 may comprise silicon oxide.
  • a doped amorphous silicon layer 1 6 may be deposited thereover.
  • a metal contact layer 118 may be deposited.
  • the metal contact layer 118 may comprise tungsten, molybdenum, titanium, chromium, aluminum, alloys thereof and combinations thereof.
  • the metal contact layer 18 may be deposited by well known deposition methods such as PVD.
  • the metal contact layer 118 is then patterned by forming a mask thereover, etching and removing the mask to leave a source electrode 122A and a drain electrode 122B.
  • the doped amorphous silicon layer 116 may be etched to form a first ohmic contact 120A and a second ohmic contact 120B.
  • FIG. 2 is a schematic cross sectional view of a TFT 200 according to another embodiment.
  • the TFT 200 includes a substrate 202, gate electrode 204, gate dielectric layer 206, microcrystalline silicon layer 210, amorphous silicon layer 212, etch stop structure 214, first ohmic contact 216A, second ohmic contact 216B, source electrode 218A, and drain electrode 218B.
  • the TFT 200 of Figure 2 may be formed in a similar manner to the TFT 100 discussed above and may comprise the same materials for the various layers as discussed above in reference to Figures 1A-1G.
  • the TFT 200 of Figure 2 has a second microcrystalline silicon layer 208.
  • the second microcrystalline silicon layer 208 is the interface microcrystalline silicon layer with general characteristics of no incubation layer and a column structure with high crystalline fraction.
  • Microcrystalline silicon layer 210 is the bulk microcrystalline silicon layer with no specific structure and low crystalline fraction.
  • FIG. 3 is a graph showing the drain current compared to the gate voltage applied for four separate TFTs: single layer microcrystalline silicon without amorphous silicon, single layer microcrystalline silicon with amorphous silicon, multi-layer microcrystalline silicon without amorphous silicon, and multi-layer microcrystalline silicon with amorphous silicon.
  • Figure 3 when an amorphous silicon layer is used, the subthreshold slope is improved. Adding the amorphous silicon controls the damage on the contact areas and significantly reduces the subthreshold slope. The amorphous silicon also improves the electrical performance of the TFT. Table I below shows the values of the subthreshold slope, l off current, l on current, threshold voltage and field effect mobility for each of the TFTs shown in Figure 3. TABLE I
  • Another problem that occurs in microcrystalline silicon based TFTs is a low field effect mobility.
  • a low resistivity (less than 1 ohm-cm) doped amorphous silicon layer may be used for the ohmic contact layer as opposed to one with a higher resistivity ( ⁇ 50 ohm- cm).
  • the average field effect mobility may be increased from 1.0 cm 2 /V-s to 2.1 cm 2 /V-s, for example.
  • a PECVD deposition method may be used whereby SiH 4 , H2, and PH3 may be delivered to the chamber while applying RF power to ignite a plasma.
  • the SiH 4 may be flowed at a rate of between about 10 seem and about 45 seem
  • the H 2 may be flowed at between about 2000 seem and about 3500 seem
  • the PH 3 may be flowed at between about 50 seem and about 85 seem into a chamber having a volume of greater than about 100000 cm 3 .
  • the substrate may be spaced between about 500 mils and about 600 mils from the showerhead.
  • the chamber may be maintained at a pressure of between about 2000 mTorr and about 3500 mTorr and the substrate may be maintained at between about 300 degrees Celsius and about 359 degrees Celsius.
  • the SiH 4 may be flowed at a rate of 30 seem, the H 2 may be flowed at 3000 seem and the PH 3 may be flowed at 70 seem into a chamber having a volume of greater than about 100000 cm 3 .
  • the substrate may be spaced 550 mils from the showerhead.
  • the chamber may be maintained at a pressure of 3000 mTorr and the substrate may be maintained at 325 degrees Celsius.
  • Figure 4 shows the improvement of the microcrystalline silicon TFT with doped amorphous silicon layer that has a resistivity of less than 1 ohm-cm relative to one with a resistivity of about 50 ohm-cm.
  • the relative low mobility of the microcrystalline silicon TFT is improved by using the low resistivity doped amorphous silicon film as the ohmic contact layer.
  • the low resistivity improves the overall source-drain contact resistance of the TFT.
  • Table II shows values of the subthreshold slope, l off current, l on current, threshold voltage and field effect mobility for each of the TFTs shown in Figure 4.
  • the deposition rate for the doped amorphous silicon layer can simply be lowered. However, lowering the deposition rate will affect the substrate throughput.
  • Dual layer or multi-layer doped amorphous silicon may be used. The layer that contacts the topmost microcrystalline silicon layer (or undoped amorphous silicon layer) may be deposited at a high rate and thus have a high resistivity while the layer that is in contact with the source and drain electrodes may be deposited at a low rate to have a low resistivity.
  • the dual or multi-layer doped amorphous silicon has the advantage of making a nice ohmic contact from the topmost microcrystalline silicon layer (or undoped amorphous silicon layer) to the source and drain electrodes.
  • Another method to improve the microcrystalline silicon TFT is to use an H 2 or N 2 plasma pretreatment before the etch stop layer is deposited. Doing so will improve the l 0 ff, subthreshold slope, field effect mobility and threshold voltage. For example, the l 0 ff may be decreased by greater than 30 percent, the subthreshold slope may be decreased by greater than 10 percent, the threshold voltage may be decreased by -2V and the field effect mobility may be improved by greater than 10 percent.
  • the amorphous silicon layer that overlies the topmost microcrystalline silicon layer may be exposed to the plasma.
  • Figure 5 shows the improvement of the drain current versus gate voltage for three scenarios: no plasma treatment of the topmost silicon layer, exposure of the topmost silicon layer to an H 2 plasma, and exposure of the topmost silicon layer to N 2 plasma. Further electrical properties improvement can be achieved by the plasma treatment before the etch stop material layer deposition. The plasma is believed to improve the interface of the contact area between the active layers and the doped amorphous silicon layer used for the ohmic contact.
  • Table III shows the values of the subthreshold slope, l 0 f current, l on current, threshold voltage and field effect mobility for each of the TFTs shown in Figure 5.
  • the H 2 gas may be flowed to the chamber at a rate of between about 5000 seem and about 7000 seem while between about 400 W and about 600 W are applied to the showerhead.
  • the chamber may be maintained at a pressure of between about 1000 mTorr and about 2000 mTorr.
  • the substrate may be spaced between about 500 mils and about 700 mils from the showerhead and be exposed to the plasma for between about 40 seconds and about 75 seconds.
  • the H 2 gas may be flowed to the chamber at a rate of 6000 seem while 500 W is applied to the showerhead.
  • the chamber may be maintained at a pressure of 1500 mTorr.
  • the substrate may be spaced 700 mils from the showerhead and be exposed to the plasma for 60 seconds.
  • the chamber may have a volume of about 100000 cm 3 or more.
  • the N 2 gas may be flowed to the chamber at a rate of between about 2000 seem and about 3000 seem while between about 500 W and about 750 W are applied to the showerhead.
  • the chamber may be maintained at a pressure of between about 1000 mTorr and about 2000 mTorr.
  • the substrate may be spaced between about 800 mils and about 1000 mils from the showerhead and be exposed to the plasma for between about 45 seconds and about 75 seconds.
  • the N 2 gas may be flowed to the chamber at a rate of 2500 seem while 700 W is applied to the showerhead.
  • the chamber may be maintained at a pressure of 1500 mTorr.
  • the substrate may be spaced 900 mils from the showerhead and be exposed to the plasma for 60 seconds.
  • the chamber may have a volume of about 100000 cm 3 or more.
  • the disclosure herein has described numerous techniques to advantageously improve microcrystalline silicon based etch stop TFTs.
  • the microcrystalline silicon TFT may have improved performance.
  • the microcrystalline silicon TFT may have improved performance.
  • the microcrystalline silicon TFT may have improved performance.
  • the microcrystalline silicon TFT may have improved performance.
  • the improved performance includes not only the mobility, but also the subthreshold slope.

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  • Thin Film Transistor (AREA)

Abstract

La présente invention concerne d'une façon générale un transistor en couches minces (TFT) et des procédés pour sa fabrication. Certains TFT ont une structure d'arrêt de gravure formée sur ceux-ci dans le canal actif. La structure d'arrêt de gravure est formée par gravure d'une couche de matière d'arrêt de gravure. La gravure peut endommager la matière en silicium microcristallin sous-jacente. Par le dépôt d'une couche de silicium amorphe sur le silicium microcristallin, le silicium microcristallin peut être protégé d'un endommagement par la gravure. De plus, le silicium amorphe dopé qui est utilisé comme contact ohmique peut être spécialement adapté pour que la résistivité soit inférieure à 1 ohm-cm. Un traitement par plasma d'hydrogène ou d'azote de la couche de silicium amorphe peut également être utilisé pour améliorer de nombreuses caractéristiques du TFT.
PCT/US2010/021323 2010-01-18 2010-01-18 Transistor en couches minces microcristallin à couche d'arrêt de gravure Ceased WO2011087514A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/US2010/021323 WO2011087514A1 (fr) 2010-01-18 2010-01-18 Transistor en couches minces microcristallin à couche d'arrêt de gravure
TW099103391A TW201126613A (en) 2010-01-18 2010-02-04 Etch stop microcrystalline thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2010/021323 WO2011087514A1 (fr) 2010-01-18 2010-01-18 Transistor en couches minces microcristallin à couche d'arrêt de gravure

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6387740B1 (en) * 1999-08-12 2002-05-14 Hannstar Display Corp. Tri-layer process for forming TFT matrix of LCD with reduced masking steps
KR20070105012A (ko) * 2006-04-24 2007-10-30 삼성전자주식회사 표시 장치용 박막 트랜지스터 표시판 및 그 제조 방법
KR20080106148A (ko) * 2008-10-23 2008-12-04 삼성전자주식회사 박막 트랜지스터
US20090236597A1 (en) * 2008-03-20 2009-09-24 Applied Materials, Inc. Process to make metal oxide thin film transistor array with etch stopping layer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6387740B1 (en) * 1999-08-12 2002-05-14 Hannstar Display Corp. Tri-layer process for forming TFT matrix of LCD with reduced masking steps
KR20070105012A (ko) * 2006-04-24 2007-10-30 삼성전자주식회사 표시 장치용 박막 트랜지스터 표시판 및 그 제조 방법
US20090236597A1 (en) * 2008-03-20 2009-09-24 Applied Materials, Inc. Process to make metal oxide thin film transistor array with etch stopping layer
KR20080106148A (ko) * 2008-10-23 2008-12-04 삼성전자주식회사 박막 트랜지스터

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