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WO2011081616A1 - Processeur a priori pour décodeur itératif - Google Patents

Processeur a priori pour décodeur itératif Download PDF

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Publication number
WO2011081616A1
WO2011081616A1 PCT/US2009/006723 US2009006723W WO2011081616A1 WO 2011081616 A1 WO2011081616 A1 WO 2011081616A1 US 2009006723 W US2009006723 W US 2009006723W WO 2011081616 A1 WO2011081616 A1 WO 2011081616A1
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WO
WIPO (PCT)
Prior art keywords
symbol
trellis
data
processor
preamble
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2009/006723
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English (en)
Inventor
Ivonete Markman
Dong-Chang Shiue
Wen Gao
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Thomson Licensing SAS
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Thomson Licensing SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Priority to PCT/US2009/006723 priority Critical patent/WO2011081616A1/fr
Publication of WO2011081616A1 publication Critical patent/WO2011081616A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3905—Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3961—Arrangements of methods for branch or transition metric calculation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6538—ATSC VBS systems

Definitions

  • the present invention generally relates to data communications systems, and more particularly to an a priori processor for a trellis encoded digital television signal.
  • FIG. 1 shows a simplified block diagram of the DTV transmitter and receiver, emphasizing the FEC system.
  • the FEC encoding subsystem consists of a Reed-Solomon encoder, followed by a byte interleaver, and a trellis encoder.
  • the receiver side there is a corresponding trellis decoder, a byte de-interleaver and a Reed-Solomon decoder.
  • the ATSC DTV transmission scheme is not robust enough against Doppler shift and multipath radio interference, and is designed for highly directional fixed antennas, hindering the provision of expanded services to customers utilizing mobile and handheld (M H) devices.
  • M H mobile and handheld
  • the added layer of FEC coding may require decoding techniques such as iterative (turbo) decoding (see, e.g., C. Berrou et al., "Near Shannon Limit
  • the training data will be fully encoded by the legacy ATSC transmitter blocks, implying that at the receiver, one needs to first decode the data stream with the legacy ATSC receiver to retrieve the additional training data and further utilize it to aid the mobile reception.
  • the present invention includes an efficient way to take advantage of the additional a priori training data prior to the legacy ATSC decoder blocks in FIG. 1.
  • an apparatus for decoding received digital data is presented.
  • the received digital data organized in digital symbol blocks of size S, wherein the data stream is encoded at a transmitter by a digital encoder processor that includes a plurality of deterministic digital processing units followed by a trellis encoder.
  • the transmitter adds digital training data bytes to the transmitted data stream prior to the digital encoder processor.
  • the receiver decoding apparatus includes an a priori processor with means for providing a priori information concerning training data bytes to the trellis decoder of the receiver without any feedback from a trellis decoder.
  • the receiver decoding apparatus creates a priori information as the data steam is being received.
  • FIG. 1 is a block diagram of a digital television (DTV) system in accordance with the Advanced Television Systems Committee (ATSC) standard for DTV;
  • FIG. 2 illustrates the format of an ATSC-DTV data frame;
  • DTV digital television
  • ATSC Advanced Television Systems Committee
  • FIG. 3 illustrates the format of a Data Field Sync segment in an ATSC-DTV data frame
  • FIG. 4 is a block diagram of an exemplary DTV M/H System in accordance with the principles of the current invention
  • FIG. 6 shows a plot of the ATSC interleaver output (horizontal axis, left to right) versus time (vertical axis, top to bottom) for a block of 52 input packets;
  • FIG. 7 illustrates a maximum a posteriori (MAP) decoder architecture
  • FIG. 8 illustrates a metric generator of the MAP decoder of Fig. 7
  • FIG. 9 illustrates an a priori processor within the metric generator of FIG. 8 in accordance with the principles of the current invention.
  • FIG. 10 illustrates an a priori processor block diagram in accordance with the principles of the current invention.
  • FIG. 2 shows the format of an ATSC-DTV data frame as transmitted.
  • Each data frame consists of two data fields, each containing 313 data segments.
  • the first data segment of each data field is a unique synchronizing segment (Data Field Sync) shown in greater detail in FIG. 3 and further discussed below.
  • Data Field Sync Data Field Sync
  • the remaining 312 data segments of each data field each carries the equivalent data of one 188-byte MPEG-compatible transport packet and its associated FEC overhead.
  • Each data segment consists of 832 8-VSB symbols.
  • the first four symbols of each data segment including the Data Field Sync segments, form a binary pattern and provide segment synchronization.
  • the first four 8-VSB symbols of each data segment have values of +5, -5, -5, and +5.
  • This four-symbol data segment sync signal also represents the sync byte of each 188-byte MPEG-compatible transport packet conveyed by each of the 312 data segments in each data field.
  • the remaining 828 symbols of each data segment carry data equivalent to the remaining 187 bytes of a transport packet and its associated FEC overhead.
  • FIG. 3 shows a Data Field Sync segment in greater detail.
  • each Data Field Sync segment includes several pseudo random (PN) sequences, a VSB mode field and a reserved field of 104 symbols.
  • PN pseudo random
  • FIG. 4 shows a simplified block diagram of an exemplary transmitter and receiver for a mobile/handheld (M/H) DTV system, hereby called DTV-M/H.
  • an added layer of FEC exemplified by FEC Encoder 2
  • the FEC Encoder 1 is compatible with the ATSC FEC encoder in FIG. 1 .
  • the Iterative FEC Decoder performs turbo decoding placed onto the transmitted signal via the various FEC encoders of the transmitter.
  • the Iterative FEC (Turbo) Decoder is not necessary for this invention, one skilled in the art will understand that the Iterative FEC decoder of FIG.
  • MAP 4 may include a maximum a posteriori (MAP) decoding of the ATSC trellis decoder and the added FEC codes within FEC Encoder 2 which will iteratively interact, each decoder sending extrinsic information to the other.
  • MAP maximum a posteriori
  • the block code is such that for each K packets of data, each with 187 information bytes (assuming MPEG packets), the block code adds N-K parity packets.
  • preamble training data segments also called a priori tracking (APT) packets
  • APT priori tracking
  • This preamble training data is fully encoded by all levels of legacy ATSC FEC coding in the system (FEC encoder 1 ), as well as being interleaved and randomized.
  • the preamble training data is known data which is added to the stream at the level of FEC Encoder 2 and it may or not be fully encoded by FEC Encoder 2.
  • An example of a burst repetitive data structure for transmission of the DTV-M/H data is given in TABLE 1. Observe that the preamble data segments are equivalent to a packet code block of 52 packets or segments.
  • a data burst comprising three data fields, F0, Fl and F2, is repetitively transmitted, each corresponding to 1.5 frame of the legacy ATSC- DTV standard.
  • the aforementioned preamble training data is placed in the first data field F0 as 52 data segments.
  • a DTV-M/H receiver When receiving a data burst such as set forth in TABLE 1, a DTV-M/H receiver will discard the 260 Legacy ATSC data segments in Data Field F0 and process the remaining data including the 52 preamble training data segments.
  • the preamble training data is to be utilized by the DTV-M/H receiver as training data used in order to enhance receiver performance.
  • the FEC Encoder 1 of Figure 4 includes a Reed Solomon (RS) encoder, interleaver, and trellis encoder blocks similar to the blocks of the FEC Encoding Subsystem of the transmitter in Figure 1 .
  • RS Reed Solomon
  • FIG. 4 the byte operations of data randomization, Reed-Solomon (RS) encoding and interleaving are deterministic and, although they will modify the preamble training data, the deterministic nature of the preamble training data will be preserved at the output of these three receiver functional blocks.
  • the trellis encoding operation which operates on each dual-bit of a byte, is not deterministic, since it is a function of the trellis state, which is a function of the data stream prior to the preamble. Hence, at the transmitter output, one cannot easily identify the presence of the preamble in the data stream. [0017] One may observe that, for a preamble (termed P) of 52 packets of 187 bytes, the output of the ATSC randomizer in the transmitter side of FIG.
  • P_R modified preamble
  • the output of the ATSC Reed Solomon (RS) encoder present in the FEC Encoder 1 of FIG. 4 is a modified preamble (termed P_RS) of 52 packets of 207 bytes, where the first 187 bytes of each packet of P RS are the same as P R and the last 20 bytes of each packet of P RS are the RS encoder parity bytes associated with each packet of P R, according to the ATSC RS encoder.
  • P_RS modified preamble
  • the presence of the RS encoder in FEC Encoder 1 of Figure 4 extends the number of preamble bytes by the RS code rate 207/187, and those bytes are also considered preamble bytes for the purpose of using them as training bytes at the receiver. Since the ATSC byte interleaver contained in the FEC Encoder 1 block of in FIG. 4 is a convolutional interleaver, the block of 52 consecutive preamble training data RS encoded (P_RS) packets of 207 bytes at its input is going to be spread over 103 output packets, in an interleaved order of bytes.
  • P_RS preamble training data RS encoded
  • FIG. 6 shows a plot of the ATSC interleaver output bytes in the horizontal axis, from left to right versus number of packets in time in the vertical axis, from top to bottom, for a block of 52 preamble input packets.
  • the horizontal axis shows the number of output bytes per packet, for a total of 207 bytes.
  • the vertical axis shows the number of each output packet in time, for a total of 103.
  • the black arrows identify the input packet 0 and the input packet 25, as an example of how these packets end up appearing in the output stream.
  • the white squares belong to all the 52 preamble packets, identifying the positions where they will be present in the output stream.
  • the remaining squares are bytes belonging to other blocks of packets before and after the preamble which become interleaved with the preamble.
  • the ATSC trellis encoder in the FEC Encoder 1 comprises 12 interleaved trellis codes of code rate 2/3, whereby each encoder sequentially receives one byte at a time and transmits one symbol at a time.
  • Each input byte is split in 4 dual-bits, and each dual-bit will be trellis encoded to form a symbol of 3 bits, of which 2 bits are information bits associated with the dual-bit at its input and the third bit is an encoded bit which is a function of the trellis state and previous inputs.
  • the preamble training data may be inserted prior to the FEC Encoder 2 block and still be traced within the encoded data as discussed above.
  • FIG. 7 shows a simplified block diagram of a MAP decoder 700.
  • the metric generator unit 710 consists of the channel metric (m c ) computation for each 8-VSB input symbol (r), which is given by:
  • the channel metrics (m c ) are then stored for a size of two path memory blocks. This path memory block, L pm , is equivalent to the traceback latency of a Viterbi decoder.
  • the metric generator unit also stores the a priori metric (m apr ) received from a previous iteration for a size of two path memory blocks.
  • the metric generator 710 must then send the m c and m apr stored values to the corresponding alpha 720 (forward processing) and beta 730 (backward processing) units.
  • the alpha values (am c and am apr ) are sent in a first in first out (FIFO) mode, while the beta (bm c and bm apr ) values are sent in a last in first out (LIFO) mode.
  • the metric generator 710 receives a priori information from a previous iteration of the FEC decoder and must send the stored values to the alpha 720 and beta 730 units in a similar fashion.
  • the LLR (log likelihood ratio) 740 unit accepts inputs from the alpha unit 720 and the beta unit 730 and produces soft output values of a symbol decision bit-pair.
  • the MAP controller unit 750 directs the calculations of the metric generator 710, alpha unit 720, beta unit 730, and LLR unit 740 by sending all the necessary control signals.
  • FIG. 8 is a block diagram of the metric generator unit 710 shown in Figure 7.
  • the metric generator 710 is mainly composed of 4 sub-units: the noise power estimator 810, the channel metric calculator 820, the channel metric storage RAM 830 and the a priori metric storage RAM 840.
  • the metric generator 710 outputs the alpha and beta channel and a priori metrics to the alpha 720 and beta 730 units, respectively.
  • the noise power estimator 81 0 may use quantizers to estimate the amount of noise in the input symbols and average the noise to obtain an estimate of the power or variance ⁇ .
  • the channel metric calculator 820 performs the calculation in equation 1 .
  • an a priori processor block 910 takes advantage of the preamble training data prior to MAP decoding in order to influence the iteration chain of FEC decoding from the very first MAP decoder in the chain, improving the chain's performance. This is opposed to the notion that one would wait to FEC decode the first system iteration, before accessing the preamble training data and generating a priori information associated with this data for the following FEC iteration. Since trellis decoders are prone to generating burst errors, it is desirable to use the preamble training data as soon as possible in the FEC iteration chain.
  • the present invention includes an apparatus in a receiver for decoding transmitted digital data, wherein the transmitted digital data is organized in digital symbol blocks of size S, wherein the transmitted data stream is encoded by a digital encoder processor comprising a plurality of deterministic digital processing units followed by a trellis encoder, and wherein digital training data bytes are added to the data stream prior to the digital encoder processor.
  • the preamble training data is fully FEC encoded by FEC Encoder 1 in FIG. 4.
  • the operations of randomization, and RS encoding are deterministic.
  • the placement of the preamble training data is constant within a field structure, as shown in the Field 0 of Table I , the operation of interleaving is also deterministic. This permits the placement of the a priori processor just prior to the metric generator and before FEC decoding because the metric generator is the first block in the FEC decoding chain of a MAP decoder.
  • the a priori processor 910 as an added part of the metric generator 710, as shown together in Figure 9.
  • FIG. 10 shows a simplified block diagram of the a priori processor block 910 of FIG. 9.
  • the a priori processor 910 includes a preamble ROM 1010, a preamble processor 1020, and an a priori multiplexer (mux) 1030.
  • the preamble ROM 1010 contains two sets of information: the preamble dual-bit, which is the information bits (VAL) associated with a particular trellis encoded 8-VSB symbol, and the position of such symbol (LOC) in the field structure of Table 1 after the interleaving and trellis encoding operations.
  • VAL information bits
  • LOC position of such symbol
  • the preamble dual-bits or VAL contain the randomized version of the original preamble data and RS encoder parity bits, which as mentioned before, are all deterministic operations.
  • the control input signals 1040 direct the preamble processor 1020 to read the preamble ROM 1010 contents.
  • the preamble processor 1020 decides, based on the control inputs 1040, internal counters, and by reading the ROM contents, which inputs in the a priori information stream should be replaced.
  • the preamble processor 1020 then creates the a priori information associated with the preamble, to replace that a priori information in the input stream.
  • the preamble processor 1020 can be implemented as a state machine or as a processor unit executing program instructions that performs the operations of the following algorithmic method, which is indicated below for either a state machine procedure or a executable program:
  • a priori information (m apr _p r eambie) based on the preamble ROM contents.
  • the preamble processor reads the dual-bit values (VAL) stored in the preamble ROM associated with the location (LOC) stored in the ROM address (ADDR). This particular a priori information
  • (m ap r_preambie) which is created by the preamble processor is the correct value of a priori information for the corresponding input symbol in the input symbol stream and shall replace the received a priori information (m apr ) for the particular symbol.
  • the dual-bit VAL is "01 "
  • COUNT COUNT + 1
  • COUNT MAX This value COUNT MAX is associated with the size of the preamble ROM and therefore its maximum address ADDR MAX.
  • ADDR ADDR + 1 ).
  • the a priori mux 1030 sends the a priori information from the preamble processor 1020 (m apr _p rea mbie) or the previous iteration of the FEC decoder (maprjn) (i.e. a priori input 1060) to the a priori metric RAM 840 of Figure 9 via the output port of the a priori mux 1030 of Figure 10, depending on the choice of the mux selector SEL, according to the method above.
  • the a priori information from the FEC decoder will be set to 0.
  • the calculated a priori information concerning training data is generated by the preamble processor 1020 and is provided to the metric generator unit and thus to the maximum a posteriori (MAP) decoder via the a priori mux of the metric generator without any feedback from a trellis decoder.
  • MAP maximum a posteriori
  • the Preamble ROM stores a location bit BIT LOC, instead of the location of the dual-bit (LOC). This location bit exists for each position from the beginning of the preamble until the last position that a preamble dual-bit appears in the stream after interleaving.
  • the value of BIT LOC may be T when the dual-bit position corresponds to a preamble dual-bit and '0' otherwise.
  • BIT LOC is ' ⁇
  • VAL the value of the dual-bit
  • the a priori processor 910 of Figures 9 and 10 inputs transmitted digital data organized in digital symbol blocks of size S, wherein the transmitted data stream is encoded by a digital encoder processor that includes a plurality of deterministic digital processing units as in the transmitter side of Figure 1 followed by a trellis encoder.
  • digital training data bytes are added to the data stream prior to the digital encoder processor.
  • elements of the a priori processor of Figure 10 serve to identify which transmitted trellis symbol positions s within a symbol block (0 ⁇ s ⁇ S) are associated with the presence of training data bits at the trellis encoder input.
  • the preamble processor 1020 of the a priori processor 910 can serve to provide a one-to-one mapping between each trellis encoded symbol position s within a symbol block (0 ⁇ s ⁇ S) and the k distinct training data bits which are inputs to the trellis encoder when the corresponding trellis encoded symbol is generated.
  • This one-to one mapping function may be present in the preamble processor 1020 or it may be a separate function such as a lookup table, address decoder, or other memory.
  • the preamble processor 1020 of Figure 10 includes a symbol counter which counts the symbols on each symbol block S and outputs newly generated preamble training data when needed.
  • I is a count of a priori values per symbol.
  • identification of which trellis symbol positions s within a symbol block (0 ⁇ s ⁇ S) are associated with the presence of training data bits at the trellis encoder input includes a memory indication, for example a one bit memory set to 1 or 0 for indicating the presence or absence of training data bits respectively for each trellis encoded symbol position s in a symbol block S.
  • This memory indication may be included in the preamble ROM 1010 memory of Figure 10, or may be a separate memory accessible by the preamble processor 1020.
  • the one-to-one mapping between each trellis encoded symbol position and the k distinct training bits can include a memory containing the k training data bits associated with each trellis encoded symbol position s in a symbol block S for which the memory indicates the presence of training data bytes.
  • the a priori processor architecture for a MAP decoder for the ATSC-DTV trellis code discussed above takes advantage of the encoded preamble training data present in a mobile ATSC-DTV system to enhance the performance of all MAP decoder iterations in an iterative (turbo) decoding receiver implementation.
  • this architecture has been implemented in VHDL and utilized in a prototype for a mobile ATSC-DTV receiver.
  • the concepts used in this invention can be extended to other iteratively decoded systems, and data frame and preamble training structures.
  • the implementations described herein may be implemented in, for example, a method or process, an apparatus, or a combination of hardware and software or hardware and firmware. Even if only discussed in the context of a single form of implementation, the implementation of features discussed may also be implemented in other forms (for example, an apparatus or a program executed in a computer).
  • An apparatus may be implemented in, for example, appropriate hardware, software, and firmware.
  • the methods may be implemented in, for example, an apparatus such as, for example, a processor, which refers to processing devices in general, including, for example, a computer, a microprocessor, an integrated circuit, or a programmable logic device.
  • Processing devices also include communication devices, such as, for example, computers, cell phones, portable/personal digital assistants ("PDAs"), and other devices that facilitate communication of information between end-users.
  • communication devices such as, for example, computers, cell phones, portable/personal digital assistants ("PDAs"), and other devices that facilitate communication of information between end-users.
  • PDAs portable/personal digital assistants
  • Implementations of the various processes and features described herein may be embodied in a variety of different equipment or applications, particularly, for example, equipment or applications associated with data transmission and reception.
  • equipment include video coders, video decoders, video codecs, web servers, set-top boxes, laptops, personal computers, and other communication devices.
  • the equipment may be mobile and even installed in a mobile vehicle.
  • the methods may be implemented by instructions being performed by a processor, and such instructions may be stored on a processor- readable medium such as, for example, an integrated circuit, a software carrier or other storage device such as, for example, a hard disk, a compact diskette, a random access memory ("RAM”), a read-only memory (“ROM”) or any other magnetic optical, or solid state media.
  • the instructions may form an application program tangibly embodied on a processor-readable medium such as any of the media listed above.
  • a processor may include, as part of the processor unit, a processor-readable medium having, for example, instructions for carrying out a process.

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  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
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  • Error Detection And Correction (AREA)

Abstract

L'invention concerne un appareil destiné à décoder des données numériques et comprenant un processeur servant à créer des informations a priori en vue de leur insertion dans un décodeur de type maximum a posteriori (MAP). Le processeur détecte les emplacements de symboles dans le flux de données d'entrée et lit des données en ROM correspondant à l'emplacement. Les données en ROM sont utilisées par le processeur pour générer des informations a priori adaptées à l'emplacement du flux de données d'entrée, et introduit les informations a priori créées dans un décodeur MAP pour contribuer au décodage de données numériques qui sont organisées en blocs de symboles numériques de taille S, le flux de données étant codé par un processeur de codeur numérique comportant une pluralité d'unités de traitement numérique déterministe suivie d'un codeur de type treillis.
PCT/US2009/006723 2009-12-28 2009-12-28 Processeur a priori pour décodeur itératif Ceased WO2011081616A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030021341A1 (en) * 2000-04-24 2003-01-30 Vigil Armando J. Method of effective backwards compatible ATSC-DTV multipath equalization through training symbol induction
US20080049871A1 (en) * 2004-04-09 2008-02-28 Xiaojun Yang Apparatus for and Method of Controlling a Sampling Frequency of a Sampling Device
US20090262799A1 (en) * 2008-04-22 2009-10-22 Samsung Electronics Co., Ltd. Transmitting additional information in the headers of encapsulating data packets in mobile/handheld (m/h) dtv signals

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030021341A1 (en) * 2000-04-24 2003-01-30 Vigil Armando J. Method of effective backwards compatible ATSC-DTV multipath equalization through training symbol induction
US20080049871A1 (en) * 2004-04-09 2008-02-28 Xiaojun Yang Apparatus for and Method of Controlling a Sampling Frequency of a Sampling Device
US20090262799A1 (en) * 2008-04-22 2009-10-22 Samsung Electronics Co., Ltd. Transmitting additional information in the headers of encapsulating data packets in mobile/handheld (m/h) dtv signals

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