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WO2011079298A3 - Système d'interconnexion configurable - Google Patents

Système d'interconnexion configurable Download PDF

Info

Publication number
WO2011079298A3
WO2011079298A3 PCT/US2010/062061 US2010062061W WO2011079298A3 WO 2011079298 A3 WO2011079298 A3 WO 2011079298A3 US 2010062061 W US2010062061 W US 2010062061W WO 2011079298 A3 WO2011079298 A3 WO 2011079298A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
modules
interconnection system
maintaining
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2010/062061
Other languages
English (en)
Other versions
WO2011079298A2 (fr
Inventor
Jon C.R. Bennett
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Violin Memory Inc
Original Assignee
Violin Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Violin Memory Inc filed Critical Violin Memory Inc
Priority to CN2010800592165A priority Critical patent/CN102792288A/zh
Priority to EP10840190.2A priority patent/EP2517110B1/fr
Priority to KR1020127019031A priority patent/KR101839027B1/ko
Publication of WO2011079298A2 publication Critical patent/WO2011079298A2/fr
Publication of WO2011079298A3 publication Critical patent/WO2011079298A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/17—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using twistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System (AREA)
  • Hardware Redundancy (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

La présente invention a trait à un système, à un appareil et à un procédé d'interconnexion permettant à la carte mère d'être équipée avec un nombre moins important de modules par rapport à l'ensemble des modules pour lesquels elle a été conçue et qu'elle peut accepter tout en maintenant une configuration permettant en cas de défaillance d'un module, de défaillance de contrôleur de mémoire ou d'une combinaison de ces dernières, de conserver la connectivité des modules restants. Lorsque des données sont stockées à l'aide d'une organisation RAID de la mémoire sur les modules, les données peuvent être reconstituées en un module de rechange. Le système fournit également une expansion incrémentielle ordonnée de la mémoire en ajoutant des modules de mémoire et des contrôleurs de mémoire supplémentaires, tout en maintenant les propriétés de connectivité.
PCT/US2010/062061 2009-12-23 2010-12-23 Système d'interconnexion configurable Ceased WO2011079298A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2010800592165A CN102792288A (zh) 2009-12-23 2010-12-23 可配置的互连系统
EP10840190.2A EP2517110B1 (fr) 2009-12-23 2010-12-23 Système d'interconnexion configurable
KR1020127019031A KR101839027B1 (ko) 2009-12-23 2010-12-23 설정가능한 상호접속 시스템

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US28981909P 2009-12-23 2009-12-23
US61/289,819 2009-12-23
US12/976,735 US9465756B2 (en) 2009-12-23 2010-12-22 Configurable interconnection system
US12/976,735 2010-12-22

Publications (2)

Publication Number Publication Date
WO2011079298A2 WO2011079298A2 (fr) 2011-06-30
WO2011079298A3 true WO2011079298A3 (fr) 2011-11-17

Family

ID=44196420

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/062061 Ceased WO2011079298A2 (fr) 2009-12-23 2010-12-23 Système d'interconnexion configurable

Country Status (5)

Country Link
US (1) US9465756B2 (fr)
EP (1) EP2517110B1 (fr)
KR (1) KR101839027B1 (fr)
CN (1) CN102792288A (fr)
WO (1) WO2011079298A2 (fr)

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US8554963B1 (en) 2012-03-23 2013-10-08 DSSD, Inc. Storage system with multicast DMA and unified address space
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JP2015072514A (ja) * 2013-10-01 2015-04-16 ソニー株式会社 データバスシステムおよび記録装置
US9619155B2 (en) 2014-02-07 2017-04-11 Coho Data Inc. Methods, systems and devices relating to data storage interfaces for managing data address spaces in data storage devices
US9471428B2 (en) 2014-05-06 2016-10-18 International Business Machines Corporation Using spare capacity in solid state drives
US9471451B2 (en) 2014-06-18 2016-10-18 International Business Machines Corporation Implementing enhanced wear leveling in 3D flash memories
US11983138B2 (en) 2015-07-26 2024-05-14 Samsung Electronics Co., Ltd. Self-configuring SSD multi-protocol support in host-less environment
US11461258B2 (en) 2016-09-14 2022-10-04 Samsung Electronics Co., Ltd. Self-configuring baseboard management controller (BMC)
US10762023B2 (en) 2016-07-26 2020-09-01 Samsung Electronics Co., Ltd. System architecture for supporting active pass-through board for multi-mode NMVe over fabrics devices
US10346041B2 (en) 2016-09-14 2019-07-09 Samsung Electronics Co., Ltd. Method for using BMC as proxy NVMeoF discovery controller to provide NVM subsystems to host
US11144496B2 (en) 2016-07-26 2021-10-12 Samsung Electronics Co., Ltd. Self-configuring SSD multi-protocol support in host-less environment
US10372659B2 (en) 2016-07-26 2019-08-06 Samsung Electronics Co., Ltd. Multi-mode NMVE over fabrics devices
US10210123B2 (en) 2016-07-26 2019-02-19 Samsung Electronics Co., Ltd. System and method for supporting multi-path and/or multi-mode NMVe over fabrics devices
CN114064527A (zh) * 2020-07-30 2022-02-18 苏州库瀚信息科技有限公司 无单一失败点的存储装置
US12019882B2 (en) * 2021-11-15 2024-06-25 VMware LLC Force provisioning virtual objects in degraded stretched clusters

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See also references of EP2517110A4 *

Also Published As

Publication number Publication date
US9465756B2 (en) 2016-10-11
KR101839027B1 (ko) 2018-03-15
WO2011079298A2 (fr) 2011-06-30
EP2517110A2 (fr) 2012-10-31
EP2517110A4 (fr) 2014-08-06
EP2517110B1 (fr) 2015-12-23
KR20120135205A (ko) 2012-12-12
CN102792288A (zh) 2012-11-21
US20110213908A1 (en) 2011-09-01

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