WO2011068359A2 - Inlay having built-in rfid tag, card including same, and method for manufacturing inlay having built-in rfid tag - Google Patents

Abstract

Disclosed is a method for manufacturing an inlay having a built-in RFID tag. The method comprises the steps of: forming a plurality of pattern circuit portions on a non-resin area by plating a surface of a metallic master in which a resin area filled with a resin and the non-resin area having a predetermined pattern are formed; bonding a core film layer on an upper side of the metallic master having the pattern circuit portions; transferring the pattern circuit portions onto the core film layer by separating the core film layer from the metallic master; forming an insulating portion in at least a partial space between the pattern circuit portions; and forming a jump connection line for electrically connecting the pattern circuit portions on the insulating portion. Thereby, the inlay having the built-in RFID tag can be easily manufactured.

Description

RFID tag embedded inlay, card including the same, and manufacturing method of RFID tag embedded inlay

The present invention relates to an RFID tag embedded inlay, and a method for manufacturing a card and an RFID tag embedded inlay including the same, and more particularly, an RFID tag embedded inlay that can be easily manufactured through a plating process using a master, and the same. To a card, and a method for manufacturing an RFID tag embedded inlay.

With the development of wireless technology, RFID (Radio Frequency IDentification) systems or combination smart card systems are being used in various fields, ranging from postpaid high pass cards to transportation cards and bank cards. The combi smart card system refers to a system using a smart card in which the IC chip is exposed on the card surface.

The RFID system basically consists of an RFID tag and an RFID reader. The RFID tag incorporates an antenna circuit pattern. For example, the 13.5 MHz circuit pattern may be manufactured in the form of a coil to induce electrical energy by external electromagnetic waves or to radiate a signal to be transmitted from an RFID IC chip to the outside. Therefore, in manufacturing the RFID tag embedded inlay, the manufacturing process of the circuit pattern and the formation of the pad portion, which is the circuit connection portion of the IC chip, play an important part.

Conventionally, in order to manufacture an inlay circuit pattern embedded with an RFID tag, a coil may be wound directly on a substrate several times to be fixed to the core film layer, or an etching circuit pattern may be fabricated on a substrate in which the core film and copper foil are incorporated. The process was carried out.

However, the method of integrating the coil directly on the substrate has a problem in process and is inadequate for mass production. In addition, in the case of using etching, it is difficult to manufacture inlays while precisely maintaining the spacing of circuit patterns, so that a short phenomenon in which circuit patterns overlap may occur, which makes it difficult to apply RFID tag inlays or combination cards. There was a problem.

In particular, according to the prior art, it has been pointed out that the connection part of the circuit pattern, that is, the pad part, is implemented in a separate process, thereby resulting in poor productivity. Therefore, there is a need for development of a manufacturing method capable of manufacturing an RFID tag embedded inlay having a more precise structure in a more convenient manner.

The present invention has been made to solve the above-described problems, an object of the present invention is to manufacture a circuit pattern of the RFID tag by a plating method using a master including a resin region and a non-resin region, RFID tag embedded inlay conveniently To provide a RFID tag embedded inlay manufacturing method and a RFID tag embedded inlay manufactured by the method and a card comprising the same.

According to an embodiment of the present invention, an RFID tag embedded inlay manufacturing method according to an embodiment of the present invention is plated on a non-resin region by plating a master surface on which a resin region filled with resin and a non-resin region forming a predetermined pattern are formed. Forming a plurality of pattern circuit portions on the substrate, bonding a core film layer on an upper side of the master on which the plurality of pattern circuit portions are formed, and separating the core film layers to transfer the plurality of pattern circuit portions to the core film layer side; Forming an insulating part in a space between the plurality of pattern circuit parts, and forming a jump line electrically connecting the plurality of pattern circuit parts on the insulating part.

Here, the plurality of pattern circuits may include a first conductive portion wound along an edge of the core film layer surface and a second conductive portion formed inside the first conductive portion on the core film layer surface. .

A first outer pad and a first inner pad may be formed at both ends of the first conductive part, respectively, and a second outer pad and a second inner pad may be formed at both ends of the second conductive part.

On the other hand, the RFID tag embedded inlay manufacturing method, forming a coverlay layer for exposing at least a portion of each of the first inner pad and the second inner pad on the plurality of pattern circuit portion and the exposure of the coverlay layer The method may further include disposing an RFID chip electrically connected to each of the first inner pad and the second inner pad.

The insulating part may be formed in a space between the first external pad and the second external pads.

The forming of the jump line may include forming at least a portion of each of the first outer pad and the second outer pad and a mask exposing at least a portion of the insulating portion, and printing a conductive material on the exposed portion. The method may include forming a jump line connecting the first external pad and the second external pad to each other and removing the mask.

The method may further include releasing the non-resin area of the master.

In the above embodiments, the resin may be Teflon.

The RFID tag may be an RFID tag for 13.56 MHz.

On the other hand, RFID tag embedded inlay according to an embodiment of the present invention, the core film layer, the first conductive portion of the form wound along the edge of the surface of the core film layer, the first conductive portion on the surface of the core film layer A second inner portion formed inside, a first inner pad formed at one end of the first conductive portion, a first outer pad formed at the other end of the first conductive portion, a second inner pad formed at one end of the second conductive portion, A second external pad formed at the other end of the second conductive part, an insulating part formed in a space between the first external pad and the second external pad, and formed on the insulating part to form the first external pad and the second external pad; And a jump line for electrically connecting the pads.

On the other hand, the card according to an embodiment of the present invention, the core film layer, the first conductive portion of the form wound along the edge of the surface of the core film layer, formed on the inside of the first conductive portion on the surface of the core film layer A second conductive part, a first inner pad formed at one end of the first conductive part, a first outer pad formed at the other end of the first conductive part, a second inner pad formed at one end of the second conductive part, and the second A second outer pad formed at the other end of the conductive part, an insulating part formed in a space between the first outer pad and the second outer pad, and formed between the first outer pad and the second outer pad. Exposing at least a portion of each of the first inner pad and the second inner pad while covering a front surface of the core film layer on which a jump line electrically connecting the first conductive portion and the second conductive portion are formed. Key may comprise an RFID chip electrically connected to the first internal pad and the second internal pad, respectively in the coverlay layer and the exposed portion.

Preferably, the first conductive portion and the second conductive portion connected by the jump line may constitute a circuit pattern used for an RFID tag for 13.56 MHz.

According to various embodiments of the present disclosure as described above, an RFID tag-embedded inlay and a card including the same may be conveniently and quickly manufactured using a master. In particular, the surface of the master is provided with a resin region and a non-resin region, the plating is performed only in the non-resin region, it is possible to precisely manufacture the RFID circuit pattern. The master can be used repeatedly.

1 is a plan view showing an example of a master configuration for manufacturing an RFID tag embedded inlay according to an embodiment of the present invention;

2 is a cross-sectional view showing a cross section of the master of FIG. 1;

3 to 5 are cross-sectional views illustrating a process of manufacturing an RFID tag embedded inlay using the master of FIG. 1;

6 is a plan view corresponding to the cross-sectional view of FIG. 5;

7 is a plan view illustrating a process of forming an insulation part in a space between a plurality of pattern circuit parts;

8 and 9 are plan views illustrating a process of manufacturing a jump line connecting a plurality of pattern circuit units;

10 and 11 are plan views illustrating a process of completing an RFID tag embedded inlay by mounting a coverlay layer and an RFID chip on an RFID tag circuit pattern.

Explanation of symbols on the main parts of the drawing

100: master 110: resin area

120, 130: non-resin area 141: first pattern circuit portion

142: second pattern circuit portion

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the present invention.

1 is a schematic diagram showing the configuration of a master used in the RFID tag manufacturing method according to an embodiment of the present invention.

1, the resin region 110 and the non-resin regions 120 and 130 are provided on the surface of the master 100. The resin region 110 refers to a portion in which a resin is filled in a groove formed on the surface of the master 100. The non-resin regions 120 and 130 refer to portions of the master 100 that are not filled with resin. In FIG. 1, the non-resin regions 120 and 130 are divided into a first region 120 provided to form the first conductive portion and a second region 130 provided to form the second conductive portion.

On the other hand, the master 100 is a kind of mold for manufacturing a circuit pattern of the RFID tag, that is, a part serving as a mold. That is, a conductive material is formed on the non-resin regions 120 and 130 to form a pattern circuit part. Therefore, the non-resin regions 120 and 130 are manufactured in a shape corresponding to the circuit pattern embedded in the RFID tag.

The master 100 of FIG. 1 may be manufactured in various ways. For example, the master 100 may be a metal etching master manufactured by a photolit-etching method. When the master 100 is implemented in a form containing a metal, it may be referred to as a metal master.

On the other hand, as the resin to be filled in the resin region 110 may be used any material having a property of excellent chemical resistance or excellent non-tackiness after a specific treatment (for example, heat treatment, etc.). Specifically, a fluorine-based polymer resin, in particular, a fluoro ethylene resin can be used. As an example, poly tetra fluoro ethylene resin can be used. Alternatively, a silicone-based polymer resin may be used.

As an example of the fluorine-based polymer resin, in particular, Teflon (trademark) registered by the US DuPont Poly Tetra Fluoro Ethylene (P.T.F.E) resin can be used. Teflon is excellent in heat resistance, chemical resistance, abrasiveness, low temperature resistance, electrical insulation, and high frequency characteristics compared to general plastics, and is suitable for use in fabricating the present pattern structure because of its unique non-tackiness and low friction characteristics.

2 is a cross-sectional view illustrating a cross section taken along line A-B of the master 100 of FIG. 1. According to FIG. 2, the master 100 has grooves of a predetermined shape formed on the surface thereof, and the resin is filled in the grooves to form the resin region 110, and the remaining portions except the resin region 110 are non-resin. Area 120 is formed. The depth and area of the resin region 110 may be variously changed according to the manufacturing process conditions of the master 100.

3 to 5 are cross-sectional views illustrating a method of manufacturing an RFID tag according to an embodiment of the present invention.

As shown in FIG. 3, the surface of the master 100 provided with the resin region 110 and the non-resin regions 120 and 130 is plated to form the pattern circuit portions 141 and 142.

The plating operation may be made of metal such as nickel, silver or copper. Specifically, the pattern circuit portions 141 and 142 may be formed by plating the copper plating bath at about 30 ° C. for about 5 to 15 minutes using a copper plating solution such as a copper sulfate plating solution. In this case, the plating power source may use a direct current or pulse power supply. The thickness of the pattern circuits 141 and 142 can be adjusted through plating time or plating power supply control. That is, the thickness of the pattern circuit portions 141 and 142 can be appropriately adjusted by controlling the application time of the DC or pulse power supply, pulse width modulation, current density, and the like.

The first pattern circuit part 141 of the plurality of pattern circuit parts 141 and 142 means a plating material formed on a portion of the non-resin area corresponding to the first area 120, and the second pattern circuit part 142 is a non-resin resin. The plating material is formed on a portion of the region corresponding to the second region 130.

Accordingly, the first pattern circuit part 141 is formed to be wound along the edge of the master 100, and the second pattern circuit part 142 is formed on the inner side of the first pattern circuit part 141 to form a first pattern. The circuit unit 141 may be spaced apart from the predetermined distance.

Meanwhile, according to another embodiment of the present invention, the surface of the non-resin regions 120 and 130 may be released before plating. That is, after the pattern circuit portions 141 and 142 are formed due to the plating, they must be transferred to the core film layer (not shown) in a subsequent process, so that the separation must be easy. To this end, the surface of the non-resin regions 120 and 130 may be released in advance.

In this state, the core film layer 200 is bonded to the master 100 as shown in FIG. 4.

As shown in FIG. 4, the core film layer 200 includes a binder layer 210 and a support layer 220.

Referring to the bonding process in detail, first, by applying a binder to the surface of the support layer 220 provided separately, the binder layer 210 is formed. Accordingly, the core film layer 200 and the master 100 are bonded to each other so that the formed binder layer 210 faces the master 100 surface.

The bonding process may be performed by bonding a polyester film or a polyvinyl chloride film coated with a binder having physical properties such as a pressure-sensitive adhesive to the pattern circuit portions 141 and 142.

Specifically, polyester-based hot melt liquid or hot melt film may be used as the binder. Such a binder may be implemented in the form of a bonding film through a process such as coating, drying, curing, or laminating on the surface of the material layer, thereby bonding the core film layer 200 to the master 100 side.

In addition, the support layer 220 of the core film layer 200 may be a plastic material commonly used for RFID tags or cards, that is, a polyester film or a polyvinyl chloride film. Various materials such as may be used. However, when using a conductive support layer 220 such as metal, an insulation treatment may be performed on the surface of the support layer 220 so that RF reception and radiation operations in the pattern circuits 141 and 142 may be normally performed.

On the other hand, the bonding process may also be made through a laminating facility. Laminating refers to a process of sandwiching the contents between a thin film such as polyester or a sheet such as glass and then attaching the contents. Specifically, a hot laminating process of applying heat and pressure using a roller, a hot plate, a roller with a built-in hot plate, or the like may be used.

The bonding process may be performed at room temperature in the case of a binder exhibiting physical properties such as an adhesive.

The binder layer 210 and the support layer 220 portions are separated from the master 100 together with the pattern circuit portions 141 and 142 in a subsequent process to support the pattern circuit portions 141 and 142.

In FIG. 4, although the binder layer 210 is shown to be spaced apart from the resin region 110 by a predetermined distance, the binder layer 210 may contact the resin region 110 during the bonding process.

After the core film layer 200 is bonded to the master 100 as shown in FIG. 4, when a predetermined time elapses, the core film layer 200 is separated into the master 100. In this process, the pattern circuit portions 141 and 142 formed on the surface of the master 100 are transferred onto the core film layer 200.

5 is a schematic diagram showing the configuration of the core film layer 200 to which the pattern circuit portions 141 and 142 are transferred. Referring to FIG. 5, the pattern circuit portions 141 and 142 are illustrated as being partially inserted into the binder layer 210, but this is an example, and the pattern circuit portions 141 and 142 are formed on the surface of the binder layer 210. May be fixed, or the pattern circuit parts 141 and 142 may be inserted to reach the surface of the support layer 220.

6 is a plan view corresponding to the cross-sectional view of FIG. 5.

According to FIG. 6, the first pattern circuit part 141 is formed in the form of a plurality of windings along the edge of the core film layer 200, and the second pattern circuit part 142 is formed inside the first pattern circuit part 141. Placed in space. Although the second pattern circuit unit 142 is illustrated as one line in FIG. 6, the second pattern circuit unit 142 may also be implemented in the form of a coil. That is, the second pattern circuit unit 142 may be implemented to be wound at least once along the inner surface of the first pattern circuit unit 141. In addition, two pattern circuit parts need not be formed, and three or more pattern circuit parts may be formed according to embodiments.

A first inner pad 141-a is formed at one end of both ends of the first pattern circuit unit 141 of FIG. 6, and a first outer pad 141-b is formed at the other end thereof. A second inner pad 142-a is formed at one end of both ends of the second pattern circuit unit 142, and a second outer pad 142-b is formed at the other end thereof. That is, each pattern circuit part consists of the line part which comprises a pattern, and the pad provided in the both ends of the line.

As described with reference to FIGS. 3 to 6, the pattern circuit unit may be manufactured in a batch using the master 100. That is, the line portion and the pad portion constituting the pattern can be produced at once. Therefore, the trouble of separately manufacturing the coil and the pad is eliminated.

In FIG. 6, the first and second inner pads 141-a and 142-a are arranged side by side with each other, but the pads 141-a, 142-a, 141-b, and 142-b are respectively disposed. The position and shape of may be changed in various ways.

By performing the plating process using the master 100 as described above, it is possible to collectively take a plurality of the pattern circuit portion, it is possible to easily manufacture the RFID circuit pattern. In particular, since the resin region 110 and the non-resin regions 120 and 130 are precisely manufactured on the master 100 and can be repeatedly used, the number of defect patterns generated in the manufacturing process can be reduced. The RFID circuit pattern can be manufactured economically.

The circuit pattern manufactured in this manner may be a circuit pattern used for an RFID tag for 13.56 MHz, and the final RFID tag manufactured according to this may be an RFID tag for 13.56 MHz.

When the plurality of pattern circuit parts 141 and 142 are formed on the core film layer 200 as shown in FIG. 6, the first and second external pads 141-b provided at one end of each of the pattern circuit parts 141 and 142 are formed. , 142-b) is carried out for electrically connecting. In this case, an insulating part is formed in a region between the first external pad and the second external pads 141-b and 142-b so as not to short with the lines constituting the first pattern circuit part 141.

7 illustrates a configuration above the core film layer 200 in which the insulation 150 is formed.

The insulating part 150 may be made of a conventional insulating material. The insulating part 150 may be implemented in the form of a sticker, and may be formed in a manner of being attached between the first outer pad and the second outer pads 141-b and 142-b.

Alternatively, the insulating liquid may be formed by dropping the insulating liquid into a space between the first outer pad and the second outer pads 141-b and 142-b and then solidifying the insulating liquid.

In FIG. 7, the insulating part 150 is illustrated as being formed only on a part of the entire core film layer 200, but is not necessarily limited thereto. That is, the insulation may be formed on the front surface of the core film layer 200 except for each of the outer pads and the inner pads. Specifically, after the mask is placed on the positions of each of the outer pads and the inner pads, the insulating part may be coated using an insulating solution, or the method of bonding the insulating part using an adhesive to a part except the corresponding parts. Can be formed.

Next, FIGS. 8 and 9 show an example of a process for manufacturing a jump line for electrically connecting the plurality of pattern circuit units 141 and 142.

That is, as shown in FIG. 8, the mask 160 is covered on the entire surface of the core film layer 200. An exposed portion 161 is formed in one region of the mask 160. As shown in FIG. 8, the exposed portion 161 exposes at least a portion of each of the first and second outer pads 141-b and 142-b and at least a portion of the insulating portion 150. In a state where the mask 160 is covered as shown in FIG. 8, the conductive material is coated. Coating of the conductive material may be performed by a process such as printing using a roller, stamping. When the mask 160 is removed in this state, a jump line 170 is formed as shown in FIG. 9. The jump line 170 may be made of a conductive paste.

According to FIG. 9, the jump line 170 is manufactured in the form of electrically connecting the first external pad and the second external pads 141-b and 142-b through the insulating unit 150. The insulating part 150 is prevented from being electrically connected to other parts of the first pattern circuit part 141 except for the first external pads 141-b.

After the jump line 170 is manufactured in this manner, as shown in FIG. 10, the coverlay layer 300 is stacked on the pattern circuit units 141 and 142. The coverlay layer 200 may be made of a plastic or paper material such as a polyester film or a polyvinyl chloride film. Since the coverlay layer 300 is a portion corresponding to the inlay appearance of the RFID tag, the material of the coverlay layer 300 may be made of a material that does not cause a problem in a subsequent process of the card. In addition, the coverlay layer 300 may be bonded to the core film layer 200 above the pattern circuit parts 141 and 142 using an adhesive. The type of adhesive may be the same as that of the binder layer 210 described above, or a different adhesive may be used.

An exposed portion 310 is formed in one region of the coverlay layer 300. The exposed portion 310 is formed in an appropriate size and position so that at least a portion of each of the lower first inner pad 141-a and the second inner pad 142-a may be exposed.

Next, as shown in FIG. 11, the RFID chip is disposed in the exposed part 310. The RFID chip is electrically connected to each of the first inner pad 141-a and the second inner pad 142-a exposed through the exposed part 310. Accordingly, the production of the RFID tag 400 is completed.

On the other hand, after the RFID chip is disposed, it is also possible to perform a surface treatment such as coating a transparent film.

In addition, although the preferred embodiment of the present invention has been shown and described above, the present invention is not limited to the above-described specific embodiment, the technical field to which the invention belongs without departing from the spirit of the invention claimed in the claims. Of course, various modifications can be made by those skilled in the art, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

Claims (10)

In the RFID tag embedded inlay manufacturing method for manufacturing an RFID tag embedded inlay, Plating a master surface on which a resin region filled with resin and a non-resin region forming a predetermined pattern are formed, thereby forming a plurality of pattern circuits on the non-resin region; Bonding a core film layer on an upper side of the master on which the plurality of pattern circuit parts are formed; Separating the core film layer and transferring the plurality of pattern circuit parts to the core film layer side; Forming an insulating part in a space between the plurality of pattern circuit parts; And, And forming a jump line electrically connecting the plurality of pattern circuit parts on the insulation part. The method of claim 1, The plurality of pattern circuits, A first pattern circuit part wound along an edge of the core film layer surface and a second pattern circuit part formed inside the first pattern circuit part on the core film layer surface; First external pads and first internal pads are formed at both ends of the first pattern circuit unit, respectively, and second external pads and second internal pads are formed at both ends of the second pattern circuit unit, respectively. Manufacturing method. The method of claim 2, Forming a coverlay layer on the plurality of pattern circuit parts to expose at least a portion of each of the first inner pad and the second inner pad; And, And arranging an RFID chip on the exposed portion of the coverlay layer, the RFID chip being electrically connected to each of the first inner pad and the second inner pad. The method of claim 3, And the insulating part is formed in a space between the first outer pad and the second outer pad. The method of claim 4, wherein Forming the jump line, Forming at least a portion of each of the first outer pad and the second outer pad and at least a portion of the insulating portion; Printing a conductive material on the exposed portion to form a jump line connecting the first external pad and the second external pad to each other; And, Removing the mask; RFID tag embedded inlay manufacturing method comprising a. The method of claim 1, Releasing the non-resin area of the master; RFID tag embedded inlay manufacturing method further comprising. The method according to any one of claims 1 to 6, The resin is a Teflon RFID tag embedded inlay manufacturing method characterized in that. The method according to any one of claims 1 to 6, The RFID tag embedded inlay manufacturing method of RFID tag embedded inlay, characterized in that used for 13.56MHz combination smart card. A core film layer; A first pattern circuit part wound along an edge of the core film layer surface; A second pattern circuit portion formed inside the first pattern circuit portion on a surface of the core film layer; A first inner pad formed at one end of the first pattern circuit part; A first external pad formed at the other end of the first pattern circuit portion; A second inner pad formed at one end of the second pattern circuit part; A second external pad formed at the other end of the second pattern circuit portion; An insulation part formed in a space between the first external pad and the second external pad; And And an jump line formed on the insulation to electrically connect between the first external pad and the second external pad. A core film layer; A first pattern circuit part wound along an edge of the core film layer surface; A second pattern circuit portion formed inside the first pattern circuit portion on a surface of the core film layer; A first inner pad formed at one end of the first pattern circuit part; A first external pad formed at the other end of the first pattern circuit portion; A second inner pad formed at one end of the second pattern circuit part; A second external pad formed at the other end of the second pattern circuit portion; An insulation part formed in a space between the first external pad and the second external pad; A jump line formed on the insulation to electrically connect between the first external pad and the second external pad; A coverlay layer exposing at least a portion of each of the first inner pad and the second inner pad while covering a front surface of the core film layer on which the first pattern circuit portion and the second pattern circuit portion are formed; And, And an RFID chip electrically connected to each of the first inner pad and the second inner pad in the exposed portion. And the first pattern circuit part and the second pattern circuit part connected by the jump line constitute a circuit pattern used for a 13.56 MHz RFID tag.

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