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WO2011052292A1 - Circuit de mémorisation, dispositif pour circuit intégré et dispositif électronique - Google Patents

Circuit de mémorisation, dispositif pour circuit intégré et dispositif électronique Download PDF

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Publication number
WO2011052292A1
WO2011052292A1 PCT/JP2010/064873 JP2010064873W WO2011052292A1 WO 2011052292 A1 WO2011052292 A1 WO 2011052292A1 JP 2010064873 W JP2010064873 W JP 2010064873W WO 2011052292 A1 WO2011052292 A1 WO 2011052292A1
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Prior art keywords
memory
memory circuit
transistor
resistance state
current
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Ceased
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PCT/JP2010/064873
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English (en)
Japanese (ja)
Inventor
稗田　克彦
青木　修
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JSR Corp
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JSR Corp
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Priority to JP2011538297A priority Critical patent/JP5382381B2/ja
Publication of WO2011052292A1 publication Critical patent/WO2011052292A1/fr
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Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • G11C13/025—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/884—Switching materials based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors
    • H10N70/8845—Carbon or carbides
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/75—Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor

Definitions

  • the present invention relates to a memory circuit, an integrated circuit device, and an electronic device.
  • DRAM Dynamic Random Access Memory
  • the structure of the memory cell is a one-element type (one transistor and one capacitor), the structure of the memory cell itself is simple, and the degree of integration is easy to increase.
  • DRAMs of 1 Gb (Gigabit) class integration are manufactured.
  • Japanese Patent Laid-Open No. 4-3463 discloses a proposal for further increasing the degree of integration of DRAM.
  • DRAM has a property that data in a memory cell is destroyed after a certain period. Therefore, in order to prevent this, a refresh operation is required in which data is periodically read and rewritten.
  • the DRAM is a volatile memory that loses data when the power is turned off.
  • Flash memory uses tunneling current to accumulate electrons in a region called a floating gate, and the threshold voltage of the transistor changes depending on whether or not there is an electron in the floating gate, whereby data representing “1” and “ Data representing “0”.
  • a flash memory having a NAND structure (also referred to as a NAND flash) is a structure in which a floating gate and a control gate are stacked between a bit line and a source line, and 16 or 32 are arranged in the bit line direction.
  • 8 Gb and 16 Gb class flash memories are manufactured.
  • ReRAM Resistivity Change Random Access Memory
  • MRAM Magneticoresistive Random Access Memory
  • PCM Phase Change Memory
  • International Publication No. WO2008 / 021912 discloses a nonvolatile memory using carbon nanotubes as resistance change elements.
  • JP-A-4-3463 which is a DRAM having a NAND structure, can improve the degree of integration, but is a DRAM and is not nonvolatile.
  • the circuit described in International Publication No. WO2008 / 021912 has a problem that the degree of integration cannot be increased because the memory circuit configuration is the same as that of a DRAM.
  • the present invention has been made in view of the above problems. According to some aspects of the present invention, while being non-volatile, it is possible to randomly access each bit or erase data for each block and write to each bit of the block.
  • a memory circuit, an integrated circuit device, and an electronic device with increased degrees can be provided.
  • a memory cell including a transistor and a resistance change element having one end connected to one of a source and a drain of the transistor is configured, and N transistors in which the first to Nth transistors as the transistors are sequentially connected in series
  • a memory block including the memory cell The other of the source and the drain of the first transistor is connected to a bit line, Each gate of the transistors connected in series is connected to a different word line, Either one of the source and the drain of the transistor connected in series is connected to a different program line via the different resistance change element
  • the variable resistance element is It includes a plurality of carbon nanotubes existing between two electrodes, and takes either a low resistance state that is relatively low resistance or a high resistance state that is relatively high resistance, When no voltage and current are applied between the two electrodes, the high resistance state or the low resistance state is maintained, When a voltage and a current are applied between the two electrodes, the state changes to either the high resistance state or the low resistance state.
  • the resistance change includes a plurality of carbon nanotubes existing between two electrodes, and takes either a low resistance state where the resistance is relatively low or a high resistance state where the resistance is relatively high
  • Any one of the source and drain of the transistors connected in series is connected to different program lines through at least different resistance change elements, so that a memory circuit that can be randomly accessed for each bit or
  • one end of the first transistor is connected to the bit line, and the N transistors are 1 Since the bit lines are shared, the degree of circuit integration can be increased.
  • variable resistance element changes from the low resistance state to the high resistance state by changing a distance between the plurality of carbon nanotubes due to heat generated by a first voltage and a first current applied between the two electrodes.
  • the distance between the plurality of carbon nanotubes may be changed from the high resistance state to the low resistance state by a Coulomb force based on a second voltage and a second current applied between the two electrodes. .
  • the first current may be greater than the second current.
  • the first voltage may be larger than the second voltage.
  • variable resistance element may include conductive carbon nanotubes.
  • variable resistance element contains a large amount of conductive (metallic) carbon nanotubes, the difference in resistance value between the low resistance state and the high resistance state increases. Therefore, the difference in reading between data representing “1” and data representing “0” becomes clear, and good memory characteristics can be obtained.
  • variable resistance element may include more single-walled carbon nanotubes than multi-walled carbon nanotubes.
  • Single wall carbon nanotubes are so thin that they tend to bend by force such as an electric field or bend easily by thermal vibration. That is, the distance between the plurality of carbon nanotubes is likely to change. For this reason, the carbon nanotubes between the electrodes of the resistance change element are changed from a high resistance state where the carbon nanotubes are not electrically connected to a low resistance state where the carbon nanotubes are attracted by Coulomb force, or due to heat. It is easy to cause a change from a low resistance state to a high resistance state that is not electrically connected due to vibration. Therefore, the difference in reading between data representing “1” and data representing “0” becomes clear, and good memory characteristics can be obtained.
  • a plurality of the memory blocks may be included.
  • At least one of the first transistors included in the plurality of memory blocks may be connected to a bit line different from the first transistors included in the other memory blocks.
  • One aspect of the integrated circuit device according to the present invention is: Any one of these memory circuits is included.
  • an integrated circuit device including a memory circuit that is nonvolatile and can be accessed randomly for each bit or rewritten for each block, and can increase the degree of circuit integration. it can.
  • One aspect of the electronic device according to the present invention is: Any one of these memory circuits is included.
  • an electronic device including a memory circuit that is nonvolatile and can be accessed randomly for each bit or rewritten for each block, and can increase the degree of circuit integration. .
  • FIG. 1 is a circuit diagram showing a circuit configuration example of the memory circuit according to the present embodiment.
  • FIG. 2 is a circuit diagram illustrating another circuit configuration example of the memory circuit according to the present embodiment.
  • FIG. 3 is a timing chart showing the concept of an operation example of the memory circuit according to the present embodiment.
  • FIG. 4 is a diagram for explaining a first structural example of a memory block which is a main part of the memory circuit according to the present embodiment and a method for manufacturing the memory block.
  • FIG. 5 is a diagram for explaining a first structural example of a memory block, which is a main part of the memory circuit according to the present embodiment, and a manufacturing method thereof.
  • FIG. 1 is a circuit diagram showing a circuit configuration example of the memory circuit according to the present embodiment.
  • FIG. 2 is a circuit diagram illustrating another circuit configuration example of the memory circuit according to the present embodiment.
  • FIG. 3 is a timing chart showing the concept of an operation example of the memory circuit according to the present embodiment.
  • FIG. 4 is
  • FIG. 6 is a diagram for explaining a first structural example of a memory block which is a main part of the memory circuit according to the present embodiment and a method for manufacturing the same.
  • FIG. 7 is a diagram for explaining a first structural example of a memory block which is a main part of the memory circuit according to the present embodiment and a method for manufacturing the same.
  • FIG. 8 is a diagram for explaining a first structural example of a memory block, which is a main part of the memory circuit according to the present embodiment, and a manufacturing method thereof.
  • FIG. 9 is a diagram for explaining a first structure example of a memory block which is a main part of the memory circuit according to the present embodiment and a manufacturing method thereof.
  • FIG. 10 is a diagram for explaining a first structural example of a memory block, which is a main part of the memory circuit according to the present embodiment, and a manufacturing method thereof.
  • FIG. 11 is a diagram for explaining a second structural example of a memory block which is a main part of the memory circuit according to the present embodiment and a manufacturing method thereof.
  • FIG. 12 is a diagram for explaining a second structural example of the memory block which is a main part of the memory circuit according to the present embodiment and a manufacturing method thereof.
  • FIG. 13 is a diagram for explaining a second structure example of the memory block, which is a main part of the memory circuit according to the present embodiment, and a manufacturing method thereof.
  • FIG. 11 is a diagram for explaining a second structural example of a memory block which is a main part of the memory circuit according to the present embodiment and a manufacturing method thereof.
  • FIG. 12 is a diagram for explaining a second structural example of the memory block which is a main part of the memory circuit according to the present embodiment and a manufacturing
  • FIG. 14 is a diagram for explaining a second structural example of a memory block which is a main part of the memory circuit according to the present embodiment and a manufacturing method thereof.
  • FIG. 15 is a diagram for explaining a second structure example of the memory block, which is a main part of the memory circuit according to the present embodiment, and a manufacturing method thereof.
  • FIG. 16A shows an example in which one memory cell block shares one bit line contact in the memory block of the first structure example.
  • FIG. 16B shows two memory cell blocks in the second structure example.
  • FIG. 6 is a cross-sectional view showing an example in which one bit line contact is shared by memory cell blocks.
  • FIG. 17 is a configuration example of an integrated circuit device according to this embodiment.
  • FIG. 18A is a configuration example of an electronic apparatus according to this embodiment.
  • FIG. 18B is a configuration example of the electronic apparatus according to the present embodiment.
  • FIG. 18C is a configuration example of the electronic apparatus according to the present embodiment.
  • FIG. 1 is a circuit diagram showing a circuit configuration example of a memory circuit according to the present embodiment.
  • the memory circuit 1 includes a memory cell including a transistor and a resistance change element having one end connected to one of a source and a drain of the transistor, and the first to Nth transistors as the transistors.
  • a memory block 10 including N memory cells connected in series up to transistors is included.
  • the number N of memory cells may be arbitrarily set as an integer of 2 or more.
  • the memory block 10 includes four memory cells Cell-1 to Cell-4.
  • a memory cell Cell ⁇ includes a first transistor T1 and a resistance change element RC1 having one end connected to one of the source and drain of the first transistor T1 (for example, the source; the same shall apply hereinafter).
  • a memory cell Cell-2 including a second transistor T2 and a resistance change element RC2 having one end connected to one of the source and drain of the second transistor T2, and a third transistor T3.
  • a memory cell Cell-3 including a resistance change element RC3 having one end connected to one of the source and the drain of the third transistor T3 is configured, and one of the source and the drain of the fourth transistor T4 and the fourth transistor T4
  • a memory cell Cell-4 having a resistance change element RC4 having one end connected to one end is formed.
  • the other of the source and the drain of the first transistor T1 (for example, the drain; the same applies hereinafter) is connected to the bit line BL1.
  • four transistors from the first transistor T1 to the fourth transistor T4 are connected in series. That is, one of the source and the drain of the first transistor T1 is connected to the other of the source and the drain of the second transistor T2.
  • One of the source and the drain of the second transistor T2 is connected to the other of the source and the drain of the third transistor T3.
  • One of the source and the drain of the third transistor T3 is connected to the other of the source and the drain of the fourth transistor T4.
  • the gates of the first transistor T1 to the fourth transistor T4 connected in series are connected to different word lines.
  • the gate of the first transistor T1 is on the word line WL1
  • the gate of the second transistor T2 is on the word line WL2
  • the gate of the third transistor T3 is on the word line WL3
  • the gate of the fourth transistor T4 is on Each is connected to the word line WL4.
  • any one of the source and drain of the first transistor T1 to the fourth transistor T4 connected in series is connected to different program lines via at least different resistance change elements.
  • one of the source and the drain of the first transistor T1 is connected to the program line PL1 via the resistance change element RC1
  • one of the source and the drain of the second transistor T2 is the resistance change element.
  • One of the source and drain of the third transistor T3 is connected to the program line PL3 via the resistance change element RC3
  • one of the source and drain of the fourth transistor T4 is the resistor through the RC2 to the program line PL2.
  • the change line RC4 is connected to the program line PL4, respectively.
  • the memory circuit 1 includes variable resistance elements RC1 to RC4.
  • the resistance change elements RC1 to RC4 include a plurality of carbon nanotubes existing between two electrodes, and the distance between the plurality of carbon nanotubes is changed, so that the resistance change elements RC1 to RC4 are relatively low resistance and relatively low resistance state. It takes one of the high resistance states that result in high resistance. Details of the resistance change elements RC1 to RC4 will be described later.
  • the memory circuit 1 may include a control circuit 20.
  • the control circuit 20 applies voltage and current between the two electrodes of the resistance change elements RC1 to RC4 by applying voltage and current to at least one of the bit line BL1, the word lines WL1 to WL4, and the program lines PL1 to PL4. Then, the state of the resistance change elements RC1 to RC4 is changed to either the low resistance state or the high resistance state.
  • the control circuit 20 can apply different voltages and currents to the bit line BL1, the word lines WL1 to WL4, and the program lines PL1 to PL4 at different timings. That is, the bit line BL1, the word lines WL1 to WL4, and the program lines PL1 to PL4 are independent control lines.
  • control circuit 20 includes a BL control circuit 202 for applying a voltage to the bit line BL1, a WL control circuit 204 for applying a voltage to the word lines WL1 to WL4, and a voltage to the program lines PL1 to PL4. And a PL control circuit 206 for applying a current.
  • FIG. 2 is a circuit diagram illustrating another circuit configuration example of the memory circuit according to the present embodiment. Although the memory circuit 2 shown in FIG. 2 shows an example having two memory blocks 11 and 12, the memory circuit 2 may have three or more memory blocks.
  • the memory circuit 2 may include a control circuit 21.
  • the control circuit 21 applies voltage and current to at least one of the bit lines BL1 and BL2, the word lines WL1 to WL4, and the program lines PL1 to PL4, so that the resistance change elements RC11 to RC14 and RC21 to RC24 are connected between the two electrodes.
  • a voltage and a current are applied to the resistance change elements RC11 to RC14 and RC21 to RC24 to change the state between the low resistance state and the high resistance state.
  • the control circuit 21 can apply different voltages and currents to the bit lines BL1 and BL2, the word lines WL1 to WL4, and the program lines PL1 to PL4 at different timings.
  • the bit lines BL1 and BL2, the word lines WL1 to WL4, and the program lines PL1 to PL4 are independent control lines.
  • the control circuit 21 includes a BL control circuit 212 for applying a voltage to the bit lines BL1 and BL2, a WL control circuit 214 for applying a voltage to the word lines WL1 to WL4, and program lines PL1 to PL4.
  • a PL control circuit 216 for applying a voltage and a current is included.
  • the memory block 11 includes four memory cells Cell-11 to Cell-14.
  • the memory cell Cell-11 including the first transistor T11 and the resistance change element RC11 having one end connected to either the source or the drain of the first transistor T11 is configured, and the second transistor T12 And a memory cell Cell-12 having a resistance change element RC12 having one end connected to one of the source and drain of the second transistor T12, and the third transistor T13 and the source and drain of the third transistor T13.
  • a memory cell Cell-14 including the element RC14 is configured. That.
  • the memory block 11 four transistors from the first transistor T11 to the fourth transistor T14 are sequentially connected in series. That is, one of the source and the drain of the first transistor T11 is connected to the other of the source and the drain of the second transistor T12. One of the source and the drain of the second transistor T12 is connected to the other of the source and the drain of the third transistor T13. One of the source and the drain of the third transistor T13 is connected to the other of the source and the drain of the fourth transistor T14.
  • the memory block 12 includes four memory cells Cell-21 to Cell-24.
  • a memory cell Cell-21 including a first transistor T21 and a resistance change element RC21 having one end connected to either the source or the drain of the first transistor T21 is configured, and the second transistor T22 And a memory cell Cell-22 having a resistance change element RC22 having one end connected to one of the source and drain of the second transistor T22, and the third transistor T23 and the source and drain of the third transistor T23.
  • a memory cell Cell-24 including the element RC24 is configured. That.
  • the memory block 12 four transistors from the first transistor T21 to the fourth transistor T24 are connected in series. That is, one of the source and the drain of the first transistor T21 is connected to the other of the source and the drain of the second transistor T22. One of the source and the drain of the second transistor T22 is connected to the other of the source and the drain of the third transistor T23. One of the source and the drain of the third transistor T23 is connected to the other of the source and the drain of the fourth transistor T24.
  • the resistance change elements RC11 to RC14 and RC21 to RC24 include a plurality of carbon nanotubes existing between two electrodes, and have a low resistance state having a relatively low resistance and a high resistance state having a relatively high resistance. Take one of the states. Details of the resistance change elements RC11 to RC14 and RC21 to RC24 will be described later.
  • At least one of the first transistors included in the plurality of memory blocks may be connected to different bit lines.
  • one of the source and the drain of the first transistor T11 included in the memory block 11 is on the bit line BL1
  • one of the source and the drain of the first transistor T12 included in the memory block 12 is included. The other is connected to the bit line BL2.
  • a bit line, a word line, and a program line may be shared in a plurality of memory blocks.
  • the memory block 11 and the memory block 12 share the word line and the program line.
  • the word line WL1 is the gate of the first transistor T11 and the gate of the first transistor T21
  • the word line WL2 is the gate of the second transistor T12 and the gate of the second transistor T22
  • the word line WL3 is the gate of the third transistor T13 and the gate of the third transistor T13.
  • the word line WL4 is connected to the gate of the third transistor T23 and the gate of the fourth transistor T14 and the gate of the fourth transistor T24, respectively.
  • the program line PL1 is connected to the resistance change elements RC11 and RC21
  • the program line PL2 is connected to the resistance change elements RC12 and RC22
  • the program line PL3 is connected to the resistance change elements RC13 and RC23
  • the program line PL4 is connected to the resistance change elements RC14 and RC24. Each is connected.
  • one bit line may be connected to the first transistors of a plurality of memory cells.
  • the area of the bit line contact can be shared by the two memory blocks, and the area of the memory chip can be reduced.
  • the bit line contact at the center has an advantage that the resistance from the bit line to each transistor is reduced.
  • one end of the first transistor T1 is connected to the bit line BL1, and the four transistors share one bit line, so that one transistor uses one bit line.
  • the degree of circuit integration can be increased.
  • the resistance change elements RC1 to RC4, RC11 to RC14, and RC21 to RC24 include a plurality of carbon nanotubes existing between two electrodes, and are relatively in a low resistance state where the resistance is relatively low.
  • One of the high resistance states in which the resistance is high is obtained. That is, the resistance change elements RC1 to RC4, RC11 to RC14, and RC21 to RC24 in the present embodiment can function as switching elements.
  • variable resistance elements RC1 to RC4, RC11 to RC14, and RC21 to RC24 in the present embodiment the voltage or current is not applied between the two electrodes from the control circuit 20 or the control circuit 21, or the power supply is cut off. In some cases, the high resistance state or the low resistance state is maintained. Further, the resistance change elements RC1 to RC4, RC11 to RC14, and RC21 to RC24 change to either a high resistance state or a low resistance state when a voltage and a current are applied between the two electrodes. That is, the resistance change elements RC1 to RC4, RC11 to RC14, and RC21 to RC24 in this embodiment can function as nonvolatile switching elements.
  • the resistance change elements RC1 to RC4, RC11 to RC14, and RC21 to RC24 in the present embodiment are resistant to heat generated by the first voltage V1 and the first current Ip1 applied between the two electrodes from the control circuit 20 or the control circuit 21.
  • the low resistance state may be changed to the high resistance state by changing the distance between the plurality of carbon nanotubes included in the change elements RC1 to RC4, RC11 to RC14, and RC21 to RC24.
  • the resistance change elements RC1 to RC4, RC11 to RC14, and RC21 to RC24 have resistance by the Coulomb force based on the second voltage V2 and the second current Ip2 applied between the control circuit 20 or the control circuit 21 and the two electrodes.
  • the high resistance state may be changed to the low resistance state by changing the distance between the plurality of carbon nanotubes included in the change elements RC1 to RC4, RC11 to RC14, and RC21 to RC24.
  • the resistance change elements RC1 to RC4, RC11 to RC14, and RC21 to RC24 are included in the resistance change element by the first voltage V1 and the first current Ip1 applied between the two electrodes from the control circuit 20 or the control circuit 21. Due to heat generated by the current flowing through the carbon nanotubes, the distance between the plurality of carbon nanotubes changes from a positional relationship in which the two electrodes are electrically connected to a positional relationship in which the electrodes are not electrically connected. Changes to a high resistance state. Further, the position where the two electrodes are not electrically connected by the Coulomb force generated by the electric field generated by the second voltage V2 and the second current Ip2 applied between the two electrodes from the control circuit 20 or the control circuit 21. By changing from the relationship to a positional relationship in which the electrodes are electrically connected, the high resistance state is changed to the low resistance state.
  • the first current Ip1 may be larger than the second current Ip2.
  • the first voltage V1 may be larger than the second voltage V2.
  • the heat generation is Joule heat generated by the current flowing through the carbon nanotubes, but it may be heat generation by Joule heat generated by the resistance of the heat generation part (electrode, connection portion thereof, etc.) in the region close to the carbon nanotubes.
  • Carbon nanotubes have a good thermal conductivity and easily transmit locally generated heat.
  • the setting of the first current value Ip1 is important. It is desirable to set the current value according to the size of the circuit, the internal resistance of the incorporated transistor, the resistance of the wiring portion, and the like.
  • the first current Ip1 is set so that Ip1> Ip2 is satisfied when the current flowing through the variable resistance element is the second current Ip2.
  • Such resistance change elements RC1 to RC4, RC11 to RC14, and RC21 to RC24 in this embodiment can operate as a high-speed switch element as compared with a method of storing charges such as a DRAM or a flash memory. Therefore, the memory circuit 1 and the memory circuit 2 that can read and write at high speed can be realized.
  • the resistance change elements RC1 to RC4, RC11 to RC14, and RC21 to RC24 in the present embodiment are not affected by the amount of charge compared to a method of storing charges such as DRAM and flash memory, so that the memory is miniaturized. In this case, the amount of stored charge does not decrease. For this reason, even if the memory circuit is miniaturized, the retention period of the stored state is longer than that of the charge storage type nonvolatile memory.
  • the structure itself for storing charges becomes smaller as the structure becomes finer. Therefore, less charge is used for storing data representing “1” and data representing “0” (ON and OFF) in the nonvolatile memory. As a result, the difference between the data representing “1” and the data representing “0” (ON and OFF) due to the amount of charge becomes small, and the difference between the data representing “1” and the data representing “0” is unclear. Therefore, there is a limit to miniaturization while maintaining reliability.
  • the ON / OFF mechanism the switching principle between the low resistance state and the high resistance state
  • the resistance change element in the present embodiment is not related to the amount of charge. Therefore, it is possible to eliminate the limitation of miniaturization in the structure of the conventional flash memory.
  • the memory circuit 1 and the memory circuit 2 that can hold data for a long period of time can be realized even if the memory circuit is miniaturized and highly integrated.
  • the resistance change elements RC1 to RC4, RC11 to RC14, and RC21 to RC24 in the present embodiment are more resistant to state changes than a configuration in which electrons pass through the insulating oxide film of a transistor, such as a flash memory. high. Therefore, the memory circuit 1 and the memory circuit 2 having a long rewrite life can be realized.
  • the resistance change elements RC1 to RC4, RC11 to RC14, and RC21 to RC24 in the present embodiment may include conductive carbon nanotubes. Furthermore, it is preferable that the resistance change elements RC1 to RC4, RC11 to RC14, and RC21 to RC24 contain more metallic (conductive) carbon nanotubes than semiconducting carbon nanotubes. By including many metallic carbon nanotubes, the difference in resistance value between the low resistance state and the high resistance state increases. Therefore, a difference in reading between data representing “1” and data representing “0” becomes clear, and good memory characteristics with high reliability can be obtained.
  • the resistance change elements RC1 to RC4, RC11 to RC14, and RC21 to RC24 in the present embodiment preferably include more single wall carbon nanotubes than multiwall carbon nanotubes.
  • Metallic single-walled carbon nanotubes are characterized by being easily affected by Coulomb force and being easily bent, and being easily deformed by vibration (lattice scattering) due to Joule heat. Therefore, the difference in resistance value between the low resistance state and the high resistance state becomes large, and good memory characteristics can be obtained.
  • FIG. 3 is a timing chart showing a concept of an operation example of the memory circuit 2 according to the present embodiment. Since FIG. 3 illustrates the concept, it does not take into account each voltage, a margin of current application timing, a time variation of an actual waveform, and the like.
  • 3A is a voltage applied to the bit line BL1 from the BL control circuit 212
  • FIG. 3B is a current flowing through the bit line BL1
  • FIG. 3C is a BL control.
  • 3D is applied to the word line WL1 from the WL control circuit 214
  • FIG. 3E is applied to the word line WL2 from the WL control circuit 214.
  • 3F is a voltage applied to the word line WL3 from the WL control circuit 214, FIG.
  • FIG. 3G is a voltage applied to the word line WL4 from the WL control circuit 214
  • FIG. 3H is a PL control.
  • the voltage applied to the program line PL1 from the circuit 216 FIG. 3I is applied to the program line PL2 from the PL control circuit 216
  • FIG. 3J is applied to the program line PL2 from the PL control circuit 216.
  • Current, 3 (K) is a voltage applied to the program line PL3 from PL control circuit 216
  • FIG. 3 (L) represents a voltage applied to the program line PL4 from PL control circuit 216.
  • the timing chart shown in FIG. 3 shows an example in which a voltage at the time of reading is applied from the PL control circuit 216.
  • the program lines PL1 to PL4 are set to the ground level (0 V), and the selected bit lines BL1 to BL2 are selected. Similarly, data representing “0” and “1” can be read at the current levels of the bit lines BL1 to BL2 even when a read voltage is applied to the side.
  • FIG. 3 shows an operation of writing data to the resistance change element RC12 of the memory cell Cell-12 and an operation of reading data written to the resistance change element RC12.
  • the description will be given with reference. Further, it is assumed that data representing “1” is written in the resistance change element RC12 when the resistance change element RC12 is in the low resistance state, and “0” is represented when the resistance change element RC12 is in the high resistance state. It is assumed that data is written in the resistance change element RC12.
  • a period from time t1 to time t2 is a period in which data representing “0” is written to the resistance change element RC12.
  • a period from time t3 to time t4 is a period in which data representing “0” written in the period from time t1 to time t2 is read from the resistance change element RC12.
  • a period from time t5 to time t6 is a period in which data representing “1” is written to the resistance change element RC12.
  • the period from time t7 to time t8 is a period in which data representing “1” written in the period from time t5 to time t6 is read from the resistance change element RC12.
  • the first voltage V1 and the first current Ip1 are applied to the program line PL2 (FIGS. 3I and 3J), and the word lines WL1 and WL2 have transistors T11 and T12. Is applied (FIGS. 3D and 3E).
  • the transistor T11 only serves as a switch.
  • 0V ground potential
  • 0V is applied to the bit line BL1 and the word lines WL3 and WL4 (FIGS. 3A, 3F, and 3G).
  • T13, T14, T23, and T24 are turned off.
  • the bit line BL2, the program lines PL1, PL3, and PL4 are in a non-selected state (high impedance) (FIGS. 3C, 3H, 3K, and 3L).
  • the state of the resistance change element RC12 once becomes a low resistance state, heat is generated by the current Ip1 flowing between the program line PL2 and the bit line BL1 via the resistance change element RC12, and a change in the distance between the plurality of carbon nanotubes occurs.
  • the carbon nanotubes that are electrically connected between the two electrodes change to a state where they are not electrically connected.
  • the current through the RC 12 does not flow and heat generation stops. That is, the state of the resistance change element RC12 changes from the low resistance state to the high resistance state. As a result, data representing “0” is written to the resistance change element RC12.
  • a read voltage Vr and a very small read current Ipr are applied to the program line PL2 (FIGS. 3I and 3J).
  • the read voltage Vr is a voltage that does not change the state of the resistance change element RC12, and is a voltage lower than the first voltage V1 and the second voltage V2. That is, the magnitude relationship among the first voltage V1, the second voltage V2, and the read voltage Vr is expressed by the inequality V1> V2> Vr.
  • the magnitude relationship among the first current Ip1, the second current Ip2, and the read current Ipr is expressed by the inequality Ip1> Ip2> Ipr.
  • V1, V2, and Vr and the relationship between Ip1, Ip2, and Ipr are preferably optimized as appropriate depending on the values of the transistor internal resistance and the wiring resistance of the memory blocks 11 and 12.
  • a gate voltage Vh at which the transistor T11 and the transistor T12 are turned on (ON state) is applied to the word line WL1 and the word line WL2 (FIGS. 3D and 3E).
  • 0V (ground potential) is applied to the bit line BL1 and the word lines WL3 and WL4 (FIGS. 3A, 3F, and 3G).
  • the bit line BL2, the program lines PL1, PL3, and PL4 are in a non-selected state (high impedance) (FIGS. 3C, 3H, 3K, and 3L).
  • the voltage on the resistance change element side corresponding to the drain side of the transistors T12 and T11 is not high enough to turn on the series transistor because the resistance change element is in a high resistance state, and is connected in series with the transistors T11 and T12.
  • the transistor is not completely turned on, and since the variable resistor is in a high resistance state, the flowing current becomes very small. Accordingly, no large current flows through the bit line BL1 (FIG. 3B).
  • the reference current value Iref is set to satisfy Iref> Ibs, and the current is smaller than the reference current Iref by comparing the reference current value Iref and the current Ibs on the BL control circuit 212 side. It can be determined that the resistance state is high.
  • the state of the resistance change element RC12 does not change by the read voltage Vr and the read current Ipr, the data written in the resistance change element RC12 is not changed without changing all the states of the resistance change elements RC11 to RC14 and RC21 to RC24. Can be read.
  • the second voltage V2 and the second current Ip2 are applied to the program line PL2 (FIGS. 3I and 3J), and the word line WL1 and the word line WL2 have the transistor T11 and A gate voltage Vh that turns on the transistor T12 is applied (FIGS. 3D and 3E).
  • 0V ground potential
  • the bit line BL2, the program lines PL1, PL3, and PL4 are in a non-selected state (high impedance) (FIGS. 3C, 3H, 3K, and 3L).
  • the second current Ip2 is a smaller value than Ip1.
  • the current flowing through the resistance change element RC12 by the current Ip2 applied from the PL control circuit 216 is a second current Ip2 smaller than the first current Ip1.
  • the state of the resistance change element RC12 does not change from the low resistance state to the high resistance state due to a change in the distance between the plurality of carbon nanotubes based on heat generation by the current Ip2 flowing through the resistance change element RC12. Therefore, the state of the resistance change element RC12 becomes a low resistance state. As a result, data representing “1” is written in the resistance change element RC12.
  • a read voltage Vr and a very small read current Ipr are applied to the program line PL2 (FIGS. 3I and 3J).
  • a gate voltage Vh at which the transistor T11 and the transistor T12 are turned on (ON state) is applied to the word line WL1 and the word line WL2 (FIGS. 3D and 3E).
  • 0V (ground potential) is applied to the bit line BL1 and the word lines WL3 and WL4 (FIGS. 3A, 3F, and 3G).
  • the bit line BL2, the program lines PL1, PL3, and PL4 are in a non-selected state (high impedance) (FIGS. 3C, 3H, 3K, and 3L).
  • the voltage on the resistance change element side corresponding to the drain side of the transistors T12 and T11 connected in series is a series transistor on the drain side of the transistors T11 and T12 connected in series because the resistance change element is in a low resistance state. Since the voltage value is sufficient to turn ON, the series transistors T11 and T12 are turned on. Therefore, a large ON current Ibr flows through the bit line BL1 (FIG. 3B).
  • the magnitude relationship between the current Ibr and the current Ibs is expressed by the inequality Ibr> Ibs.
  • the reference current value Iref is set to satisfy Ibr> Iref> Ibs, and the resistance change element RC12 is in the low resistance state by comparing the reference current value Iref and the current Ibr on the BL control circuit 212 side. Can be determined. Thereby, data representing “1” written in the resistance change element RC12 during the period from time t5 to time t6 can be read from the resistance change element RC12. Further, since the state of the resistance change element RC12 does not change with the read voltage Vr, the data written in the resistance change element RC12 can be read without changing all the states of the resistance change elements RC11 to RC14 and RC21 to RC24. .
  • the control circuit 21 applies a predetermined voltage to the bit lines BL1, BL2, the word lines WL1 to WL4, and the program lines PL1 to PL4 so that a voltage and a current are applied between the two electrodes of the variable resistance element to be operated.
  • a current by applying a current, a memory circuit 2 that can be randomly accessed for each bit can be realized.
  • data representing “0” is selectively written into the memory cell Cell-12, data representing “0” is read, data representing “1” is written, and “1” is written.
  • the basic operation of reading out the data representing " is described.
  • an operation of reading data in a memory cell and rewriting it to data representing “0” or data representing “1” can be performed only when the data is to be rewritten. By doing so, the rewriting efficiency can be improved.
  • the memory circuit 1 and the memory circuit 2 according to the present embodiment can read bit by bit without destroying data stored in other memory cells. Therefore, the number of steps for reading (transistor switching operation, etc.) is smaller than that of a conventional NAND flash memory. Therefore, although it is a NAND type memory circuit that can be highly integrated, it can be read at a higher speed than the conventional NAND type flash memory.
  • FIG. 4A is a plan view of a memory block
  • FIG. 4B is a cross-sectional view taken along a dashed line in FIG. 4A.
  • a method for manufacturing a memory block of the memory circuit according to the present embodiment on a silicon substrate will be described.
  • an element isolation film 302 is formed on the main surface side of a P-type silicon substrate 300.
  • the element isolation film 302 may be formed by a known STI (shallow trench isolation) method or a LOCOS (local oxidation of silicon) method.
  • the element isolation film 302 is formed by the STI method.
  • a double well structure in which an N type well or a P type well is formed in an N type well in the P type silicon substrate 300 may be used.
  • a gate insulating film 304 is formed in the element formation region on the surface of the P-type silicon substrate 300.
  • the gate insulating film 304 may be formed by forming a silicon oxide film by thermally oxidizing the surface of the P-type silicon substrate 300.
  • a composite film of a silicon oxide film and a silicon nitride film Si 3 N 4 film may be used.
  • word lines WL 1 to WL 4 are formed on the gate insulating film 304.
  • the word lines WL1 to WL4 may be formed by the following procedure. First, a polysilicon layer is deposited, and a silicon nitride film (Si 3 N 4 film) to be the cap layer 310 is deposited thereon. Thereafter, a desired resist pattern is formed by a photolithography process using a mask, and then patterned using a dry etching method such as a reactive ion etching (RIE) method using the resist pattern as a mask, A desired WL pattern is formed by removing the resist film.
  • RIE reactive ion etching
  • an n-type diffusion layer 306 is formed.
  • an n ⁇ type diffusion region is formed as the n type diffusion layer 306 by implanting phosphorus (P) ions, arsenic (As) ions, or the like by ion implantation using the word lines WL1 to WL4 as a mask.
  • the n-type diffusion layer 306 is not formed in the channel region directly under the gate.
  • sidewall films 308 are formed on both sides of the word lines WL1 to WL4.
  • the sidewall film 308 is formed by depositing a silicon oxide film over the entire surface of the substrate using a CVD method and then etching the entire surface using an anisotropic dry etching method such as a reactive dry etching (RIE) method.
  • RIE reactive dry etching
  • n + -type diffusion region is formed.
  • a region immediately below the gate becomes a low-concentration n ⁇ -type diffusion region, and other regions become high-concentration n + -type diffusion regions.
  • LDD lightly doped drain
  • the cap film 310 formed on the word lines WL1 to WL4 serves to increase the step difference of the gate electrode when forming the sidewall film 308 and to increase the thickness of the mask when ion implantation is performed using the gate electrode as a mask. This has the effect of preventing ions from penetrating into the channel region.
  • an interlayer insulating film 312 is formed on the main surface side of the P-type silicon substrate 300.
  • the interlayer insulating film 312 may be formed of a silicon oxide film formed by a CVD (chemical vapor deposition) method. Thereafter, the interlayer insulating film 312 may be planarized using a CMP (chemical mechanical polishing) method or the like.
  • a contact hole (through hole) that penetrates the interlayer insulating film 312 and reaches the surface of the n + -type diffusion region of the n-type diffusion layer 306 is formed.
  • the contact hole is formed by removing the interlayer insulating film 312 in a desired region by etching using photolithography, RIE, or the like.
  • a titanium film (Ti) and a titanium nitride film (TiN) are deposited on the entire surface of the substrate by PVD (physical vapor deposition) so as to cover the side wall and bottom surface of the contact hole.
  • a tungsten film (W) is deposited using a CVD method, and then a tungsten film, a titanium nitride film, and a titanium film are selectively embedded in the contact hole by a CMP method to form a via 314 serving as a tungsten plug.
  • a lower electrode 316 is formed on the entire surface.
  • the lower electrode 316 may be formed using a titanium nitride film formed by a sputtering method.
  • the via 314 buried in the contact hole and the lower electrode 316 are formed so as to be electrically connected.
  • a carbon nanotube layer 318 is formed on the entire surface of the lower electrode 316.
  • the carbon nanotube layer 318 may be formed by applying a dispersion containing carbon nanotubes by spin coating or the like.
  • the upper electrode 320 is formed on the entire surface of the carbon nanotube layer 318.
  • the upper electrode 320 may be formed of a titanium nitride film formed by a sputtering method.
  • the upper electrode 320, the carbon nanotube layer 318, and the lower electrode 316 are formed in the bit line direction (the bit formed in a later step as shown in FIG. 7A) by using a normal photolithography method and a dry etching method. It is processed into an elongated shape in the longitudinal direction of the line BL1. Thereafter, the resist film (not shown) used for processing is removed.
  • a tungsten film to be the program lines PL1 to PL4 is deposited on the entire surface by a CVD method or the like, the tungsten film, The upper electrode 320, the carbon nanotube layer 318, and the lower electrode 316 are continuously processed.
  • program lines PL1 to PL4 electrically connected to the upper electrode 320 and connected in the longitudinal direction of the word lines WL1 to WL4 are formed.
  • the lower electrode 316, the carbon nanotube layer 318, and the upper electrode 320 are formed independently for each memory cell.
  • Lower electrode 316 is electrically joined to either the source or the drain of the transistor, and upper electrode 320 is electrically connected to program lines PL1 to PL4.
  • an interlayer insulating film 322 is formed so as to cover the program lines PL 1 to PL 4 and the interlayer insulating film 312.
  • the interlayer insulating film 322 may be formed using a silicon oxide film formed by a CVD method.
  • the interlayer insulating film 322 is planarized by a CMP method. Thereafter, a contact hole (through-hole) 324 that penetrates the interlayer insulating film 312 and the interlayer insulating film 322 and reaches the surface of the n + -type diffusion region of the n-type diffusion layer 306 is formed.
  • the contact hole 324 may be formed by removing the interlayer insulating film 312 and the interlayer insulating film 322 in a desired region by a dry etching process using photolithography and an RIE method.
  • the bit line BL 1 electrically connected to the n + -type diffusion region of the n-type diffusion layer 306 through the contact hole 324 is connected to the insulating interlayer film 322.
  • the bit line BL1 may be formed by forming a tungsten film formed by a CVD method and then removing unnecessary portions by photolithography, etching, or the like.
  • an interlayer insulating film 324 is formed so as to cover the bit line BL1 and the interlayer insulating film 322.
  • the interlayer insulating film 324 may be formed using a silicon oxide film formed by a CVD method.
  • an ordinary metal wiring process is performed to form an interlayer insulating film, pad opening, necessary sintering heat treatment, and the like, and an LSI (large scale integration) is completed.
  • the cross-sectional view shown in FIG. 10B of the memory block thus formed is compared with the circuit diagram shown in FIG.
  • the transistor T1 using the word line WL1 as a gate and the n-type diffusion layer 306 as a source or drain, and the word line WL2 as a gate and the n-type diffusion layer 306 as a source or drain It can be seen that the transistor T2, the transistor T3 having the word line WL3 as a gate and the n-type diffusion layer 306 as a source or drain, and the transistor T4 having the word line WL4 as a gate and the n-type diffusion layer 306 as a source or drain are formed. .
  • variable resistance elements RC1 to RC4 each including the lower electrode 316, the carbon nanotube layer 318, and the upper electrode 320 are formed. That is, it can be seen that the configuration shown in FIG. 10B corresponds to the memory block 10 in the circuit diagram shown in FIG.
  • the degree of integration of the memory circuit can be increased.
  • FIGS. 11 to 15 are views for explaining a second structure example of the memory block which is a main part of the memory circuit according to the present embodiment and a manufacturing method thereof.
  • A) in each figure is a plan view of the memory block
  • B) in each figure is a cross-sectional view taken along the alternate long and short dash line in (A) of the figure.
  • symbol is attached
  • a recess is formed by recess etching a part of the tungsten film in the contact hole 314, and a lower electrode 316 is formed in the recess.
  • a titanium nitride film formed by sputtering is deposited on the entire surface, and then planarized by CMP to selectively form the lower electrode 316 in the recess.
  • a carbon nanotube layer 318 is formed on the entire surface so as to be electrically connected to the lower electrode 316 embedded in the recess.
  • the carbon nanotube layer 318 may be formed by applying a dispersion containing carbon nanotubes by spin coating or the like.
  • the upper electrode 320 is formed on the carbon nanotube layer 318.
  • the upper electrode 320 may be formed of a titanium nitride film formed by a sputtering method.
  • the carbon nanotube layer 318 and the upper electrode 320 are processed into a desired shape elongated in the bit line direction (longitudinal direction of the bit line BL1 formed in a later step) by using photolithography, etching, or the like.
  • a tungsten film to be the program lines PL1 to PL4 is deposited on the entire surface by a CVD method or the like, and then the tungsten film, The upper electrode 320 and the carbon nanotube layer 318 are continuously processed.
  • program lines PL1 to PL4 electrically connected to the upper electrode 320 and connected in the longitudinal direction of the word lines WL1 to WL4 are formed.
  • the lower electrode 316, the carbon nanotube layer 318, and the upper electrode 320 are formed independently for each memory cell.
  • Lower electrode 316 is electrically joined to either the source or the drain of the transistor, and upper electrode 320 is electrically connected to program lines PL1 to PL4.
  • an interlayer insulating film 322 is formed so as to cover the program lines PL 1 to PL 4 and the interlayer insulating film 312.
  • the interlayer insulating film 322 may be formed using a silicon oxide film formed by a CVD method.
  • the interlayer insulating film 322 is planarized by a CMP method. Thereafter, a contact hole (through-hole) 324 that penetrates the interlayer insulating film 312 and the interlayer insulating film 322 and reaches the surface of the n + -type diffusion region of the n-type diffusion layer 306 is formed.
  • the contact hole 324 may be formed by removing the interlayer insulating film 312 and the interlayer insulating film 322 in a desired region by photolithography, etching, or the like.
  • the bit line BL 1 electrically connected to the n + -type diffusion region of the n-type diffusion layer 306 through the contact hole 324 is connected to the insulating interlayer film 322.
  • the bit line BL1 may be formed by using a tungsten film formed by a CVD method and removing unnecessary portions by photolithography, etching, or the like.
  • an interlayer insulating film 324 is formed so as to cover the bit line BL1 and the interlayer insulating film 322.
  • the interlayer insulating film 324 may be formed using a silicon oxide film formed by a CVD method.
  • an ordinary metal wiring process is performed to form an interlayer insulating film, pad opening, necessary sintering heat treatment, and the like, thereby completing the LSI.
  • the cross-sectional view shown in FIG. 15B of the memory block thus formed is compared with the circuit diagram shown in FIG. According to the cross-sectional view shown in FIG. 15B, the transistor T1 having the word line WL1 as a gate and the n-type diffusion layer 306 as a source or drain, and the word line WL2 as a gate and the n-type diffusion layer 306 as a source or drain. It can be seen that the transistor T2, the transistor T3 having the word line WL3 as a gate and the n-type diffusion layer 306 as a source or drain, and the transistor T4 having the word line WL4 as a gate and the n-type diffusion layer 306 as a source or drain are formed. .
  • variable resistance elements RC1 to RC4 each including the lower electrode 316, the carbon nanotube layer 318, and the upper electrode 320 are formed. That is, it can be seen that the configuration shown in FIG. 15B corresponds to the memory block 10 in the circuit diagram shown in FIG.
  • a configuration in which one bit line is shared by a plurality of memory cells can increase the degree of integration of the memory circuit. Furthermore, the lower electrode 316 can be miniaturized by embedding the lower electrode 316 in the contact hole.
  • FIG. 16A shows an example in which one memory cell block shares one bit line contact in the memory block of the first structure example.
  • FIG. 16B shows two memory cell blocks in the second structure example.
  • FIG. 6 is a cross-sectional view showing an example in which one bit line contact is shared by memory cell blocks.
  • 16A and 16B are examples in which the memory block 11 and the memory block 12 are connected to the same bit line BL1.
  • the memory block 11 and the memory block 12 are arranged around the bit line contact BC, and the two memory blocks of the memory block 11 and the memory block 12 share one bit line contact BC.
  • FIG. 17 is a configuration example of an integrated circuit device according to this embodiment.
  • An integrated circuit device 500 according to this embodiment includes a memory circuit 2 and an arithmetic processing circuit 550.
  • the memory circuit 2 and the arithmetic processing circuit 550 may be formed on the same semiconductor substrate. Note that the memory circuit 1 may be included instead of the memory circuit 2.
  • the arithmetic processing circuit 500 may perform various arithmetic processes using data stored in the memory circuit 2. Further, the arithmetic processing circuit 500 may store the results of performing various arithmetic processes in the memory circuit 2.
  • an integrated circuit device including a memory circuit that is nonvolatile and can be accessed randomly for each bit or rewritten for each block and can increase the degree of circuit integration. realizable.
  • FIGS. 18A to 18C are configuration examples of electronic devices according to the present embodiment.
  • 18A shows a notebook computer 1000
  • FIG. 18B shows a mobile phone 2000
  • FIG. 18C shows an IC recorder 3000.
  • the notebook personal computer 1000, the mobile phone 2000, and the IC recorder 3000 according to the present embodiment are configured to include the memory circuit 2 as a part of the storage device that each has. Further, the integrated circuit device 500 including the memory circuit 2 may be included.
  • an electronic device including a memory circuit that is nonvolatile and can be randomly accessed for each bit or rewritten for each block and can increase the degree of circuit integration is realized. it can. Further, since a nonvolatile memory circuit is used, low power consumption can be realized.
  • the present invention is not limited to the present embodiment, and various modifications can be made within the scope of the gist of the present invention.
  • the present invention includes substantially the same configuration (for example, a configuration having the same function, method, and result, or a configuration having the same purpose and effect) as the configuration described in the embodiment.
  • the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced.
  • the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object.
  • the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

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Abstract

Le dispositif ci-décrit possède des cellules de mémoire munies de transistors et d'éléments à résistance variable, et contient des blocs de mémoire (10) ayant un nombre N de cellules de mémoire connectées dans l'ordre et en série. L'extrémité d'un premier transistor (T1) est connectée à une ligne de bit (BL1). Les éléments à résistance variable (RC1 à RC4) comportent une pluralité de nanotubes de carbone placés entre deux électrodes. Ils peuvent être dans un état de faible résistance lorsque l'élément à résistance a une résistance relativement faible, ou dans un état de résistance élevée lorsque l'élément à résistance a une résistance relativement élevée, et ils peuvent conserver leur état de résistance élevée ou de faible résistance lorsque ni tension ni courant n'est appliqué entre les deux électrodes.
PCT/JP2010/064873 2009-10-26 2010-09-01 Circuit de mémorisation, dispositif pour circuit intégré et dispositif électronique Ceased WO2011052292A1 (fr)

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