WO2011049054A1 - Insulated gate bipolar transistor and method for designing same - Google Patents

Abstract

Disclosed is an insulated gate bipolar transistor which has a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on the surface layer of the main surface side, a third semiconductor layer of the first conductivity type selectively formed on the surface layer of the second semiconductor layer, a fourth semiconductor layer of the second conductivity type formed on the surface layer of the undersurface side, and a fifth semiconductor layer of the first conductivity type formed between the first and fourth semiconductor layers and having a higher impurity concentration than the first semiconductor layer. A recombination centre lattice defect having a single density distribution peak is disposed in the first semiconductor layer so that the peak position is located within the width of the non-depletion region at the end of turn-off time.

Description

Insulated gate bipolar transistor and design method thereof

This application claims priority to Japanese Patent Application No. 2009-240728, which was filed on October 19, 2009, and the entire contents of the specification of this Japanese patent application are incorporated herein by reference. Captured in the book.
The present invention relates to an insulated gate bipolar transistor and a design method thereof.

Insulated gate bipolar transistors (IGBTs), which are vertical power devices, are disclosed in, for example, Japanese Patent Publication No. 10-50724 (Patent Document 1) and Japanese Patent Publication No. 2004-103982 (Patent Document). 2). An IGBT can be understood as a structure in which a MOS field effect transistor (MOS-FET) and a bipolar transistor (BJT) are combined, and as one of high-current / high-voltage power devices, from industrial to household appliances It has been widely applied.

IGBTs can be roughly classified into so-called punch-through (PT) type IGBTs, non-punch-through (NPT) type IGBTs, and field stop (FS) type IGBTs. A PT-type IGBT (for example, Patent Document 1) uses a thick substrate of P conductivity type (P +) as a collector layer, and inserts an N conductivity type (N +) buffer layer between the N conductivity type (N−) drift layer. It has a structure. An NPT type IGBT (for example, Patent Document 1) has a structure in which a collector layer of P conductivity type (P +) is formed on the back surface of a thin N conductivity type (N−) substrate (body layer) functioning as a drift layer. Yes. In addition, an FS type IGBT (for example, Patent Document 2) inserts a buffer layer designed to have a low N conductivity type carrier concentration called a field stop (FS) layer between a drift layer and a collector layer of an NPT type IGBT, The N-conductivity type (N−) substrate (body layer), which is a drift layer, is further thinned. The IGBT, which is a vertical power device, has been reduced in thickness for the purpose of reducing loss. In recent years, the FS type IGBT that can be thinned most is becoming the mainstream structure.

FIG. 14 is a typical example of the FS type IGBT and is a schematic cross-sectional view of the IGBT 90.

The IGBT 90 shown in FIG. 14 is formed on an N conductivity type (N−) semiconductor substrate 10. The IGBT 90 includes a first semiconductor layer 1 made of an N-conductivity type (N−) semiconductor substrate 10, and a P-conductivity type (P) second semiconductor layer 2 formed in a surface layer portion on the main surface side of the semiconductor substrate 10. And an N conductivity type (N +) third semiconductor layer 3 selectively formed in the surface layer portion of the second semiconductor layer 2. Note that a portion indicated by reference numeral G formed so as to penetrate the second semiconductor layer 2 is a gate electrode (insulating trench gate) having a trench structure, and the second semiconductor layer 2 is a channel formation region called a base layer. The third semiconductor layer 3 is an emitter region. The emitter electrode E is formed on the semiconductor substrate 10 on the main surface side so as to be commonly connected to the second semiconductor layer 2 and the third semiconductor layer 3 via the interlayer insulating film 6.

The IGBT 90 includes a P-conductivity type (P +) fourth semiconductor layer 4 formed in the surface layer portion on the back surface side of the semiconductor substrate 10, and an N formed between the first semiconductor layer 1 and the fourth semiconductor layer 4. The fifth semiconductor layer 5 has a conductivity type (N) and an impurity concentration higher than that of the first semiconductor layer 1. The fourth semiconductor layer 4 is a collector region, and a collector electrode C is formed on the semiconductor substrate 10 on the back surface side so as to be connected to the fourth semiconductor layer 4. The fifth semiconductor layer 5 is a so-called FS layer, and the first semiconductor layer 1 is a carrier drift region in the IGBT 90.

Japanese Patent Laid-Open No. 10-50724 JP 2004-103982 A

15 and 16 are diagrams schematically showing characteristics at the time of turn-off of a general IGBT. FIG. 15 is a diagram illustrating waveforms of the gate voltage Vg, the collector voltage Vc, and the collector current Ic at the time of turn-off, and FIG. 16 is a diagram illustrating a waveform of the work rate Vc × Ic related to the loss at the time of turn-off. .

As shown in FIG. 15, in the IGBT, after the gate is turned off, the collector current Ic decreases with a delay after the discharge of the gate capacitance is completed, and the collector voltage Vc increases accordingly. The collector current Ic suddenly drops to about 20% of the on state, and then begins to tail (start tail). This phenomenon in which the collector current Ic has a tail (tail current) is peculiar to the IGBT and is affected by residual holes in the drift layer. In FIG. 16, the turn-off loss of the IGBT (total loss at turn-off) corresponds to the integrated area of the waveform of the power Vc × Ic, but the tail loss (in the turn-off loss, after the start of the tail) Loss) account for about 40% of the turn-off loss.

In order to reduce the tail current peculiar to the IGBT shown in FIG. 15 and FIG. 16 and to reduce the loss accompanying the tail current and increase the switching speed, various methods have been studied.

For example, Patent Document 1 discusses a method of quickly eliminating residual holes by controlling the lifetime of residual holes in a drift layer that causes a tail current in PT-type IGBTs and NPT-type IGBTs. According to Patent Document 1, an N− type base layer that is a drift layer is formed so that the width of the non-depleted region is 40 μm or more, and then H ²⁺ is irradiated in two portions. Thus, in the N− type base layer, the first low lifetime layer having a relatively deep recombination order at about 20 μm from the P type collector layer is relatively formed at about 60 μm from the P type collector layer. A second low lifetime layer having a shallow recombination order is formed respectively. In this way, almost the entire remaining non-depleted region can be reduced in lifetime, and the tail current at the time of a low power supply voltage can be suppressed without causing deterioration of breakdown voltage or increase in leakage current and on-voltage.

On the other hand, in place of the PT-type IGBT and NPT-type IGBT described in Patent Document 1, the FS-type IGBT, which is becoming a mainstream structure in recent years, has been developed on the premise that lifetime control of residual holes is not performed. This is because it is difficult to realize a complicated lifetime control structure as disclosed in Patent Document 1 in the FS-type IGBT in which thinning is the greatest merit.

As a technique for reducing the tail loss and increasing the device speed in addition to the lifetime control of the residual holes, for example, the P + type collector layer (fourth semiconductor layer 4) and the N type FS layer (fifth semiconductor layer) of the IGBT 90 in FIG. A method of suppressing the hole injection efficiency by appropriately controlling the impurity concentration of the semiconductor layer 5) can be used. However, although the method of suppressing the hole injection efficiency can reduce the tail current, for example, the contact resistance with the collector electrode C is increased by reducing the concentration of the P + type collector layer, or the current driving capability of the IGBT is decreased. Problems occur.

Therefore, the present invention is an insulated gate bipolar transistor and a design method thereof, which has a simple lifetime control structure capable of precisely controlling the lifetime of residual holes, and has high tail switching with low tail loss. It is an object to provide a possible insulated gate bipolar transistor and a design method thereof.

The insulated gate bipolar transistor disclosed in the present application includes a first semiconductor layer formed of a first conductive type semiconductor substrate, a second conductive type second semiconductor layer formed in a surface layer portion on a main surface side of the semiconductor substrate, A third semiconductor layer of a first conductivity type selectively formed in a surface layer portion of the second semiconductor layer; a fourth semiconductor layer of a second conductivity type formed in a surface layer portion on the back surface side of the semiconductor substrate; A fifth semiconductor layer having a first conductivity type formed between the first semiconductor layer and the fourth semiconductor layer and having an impurity concentration higher than that of the first semiconductor layer; The first semiconductor layer includes a recombination center lattice defect having one density distribution peak in a cross-sectional direction of the semiconductor substrate. The recombination center defect is arranged in the first semiconductor layer such that the peak position of the density distribution peak is located inside the width of the non-depleted region at the end of turn-off from the back surface of the semiconductor substrate.

In the IGBT, generally, after the gate is turned off and the collector current Ic is rapidly reduced to about 20% of that at the time of on, a phenomenon (tail current) is generated due to the influence of residual holes in the drift layer. . In order to reduce the tail current, reduce tail loss associated with the tail current, and increase the switching speed, in the IGBT, a recombination center lattice defect having one density distribution peak in the cross-sectional direction of the semiconductor substrate ( The so-called lifetime killer of residual holes is arranged in the first semiconductor layer so that the peak position of the density distribution peak is located inside the width of the non-depleted region at the end of turn-off from the back surface of the semiconductor substrate. . Specifically, the recombination center lattice defect is locally formed by irradiating ions such as proton, deuterium (dutron), and helium from the back side of the semiconductor substrate.

By arranging the peak position of the density distribution peak of the recombination center lattice defect in the first semiconductor layer so as to be located inside the width of the non-depleted region where the electric field intensity at the end of turn-off is zero, the recombination Compared to the case where no center lattice defect is introduced, tail loss can be reduced and switching can be speeded up without increasing the on-voltage. The recombination center lattice defect in the IGBT has a simple structure having one density distribution peak in the cross-sectional direction of the semiconductor substrate, and can be easily realized even in a thin IGBT. The distribution of the recombination center lattice defects and the width of the non-depleted region where the electric field strength at the end of turn-off is zero can be determined accurately by, for example, simulation.

In the insulated gate bipolar transistor (IGBT), for example, the first semiconductor layer is a drift layer (body layer), the second semiconductor layer is a channel formation layer, the third semiconductor layer is an emitter layer, and the fourth semiconductor layer is This is an FS type IGBT having a collector layer and a fifth semiconductor layer as a field stop (FS) layer. The fourth semiconductor layer and the fifth semiconductor layer may be thin layers of about 1 μm.

The lifetime control of the residual holes due to the IGBT recombination center lattice defect is different from the method of suppressing the hole injection efficiency by appropriately controlling the impurity concentration of the fourth semiconductor layer and the fifth semiconductor layer, for example. The contact resistance with the collector electrode to be connected does not increase, and the current drive capability of the IGBT does not decrease.

As described above, the insulated gate bipolar transistor has a simple lifetime control structure capable of precisely controlling the lifetime of residual holes, and has a small tail loss and enables high-speed switching. It can be a bipolar transistor.

In the insulated gate bipolar transistor, the recombination center lattice defect is formed such that a main surface side half-value width position of the density distribution peak is located inside a width of the non-depleted region from the back surface of the semiconductor substrate. It is preferable to arrange in the first semiconductor layer. Furthermore, the recombination center lattice defect is formed in the first semiconductor layer such that the main surface side skirt tip position of the density distribution peak is located inside the width of the non-depleted region from the back surface of the semiconductor substrate. More preferably, they are arranged.

According to this, the distribution of recombination center lattice defects is more surely contained in the non-depleted region, and the tail loss can be reduced and the switching speed can be increased more stably.

As described above, the insulated gate bipolar transistor is suitable when the thickness of the semiconductor substrate is 120 μm or more and 200 μm or less.

The insulated gate bipolar transistor may be a trench gate type IGBT having an insulated trench gate formed so as to penetrate the second semiconductor layer.

The present application also discloses a design method for the insulated gate bipolar transistor according to the design procedure for the insulated gate bipolar transistor.

The present application relates to a first semiconductor layer made of a first conductivity type semiconductor substrate, a second conductivity type second semiconductor layer formed in a surface layer portion on a main surface side of the semiconductor substrate, and a surface layer of the second semiconductor layer. A third semiconductor layer of a first conductivity type selectively formed in a part, a fourth semiconductor layer of a second conductivity type formed in a surface layer part on the back side of the semiconductor substrate, the first semiconductor layer, A fifth semiconductor layer having a first conductivity type formed between the fourth semiconductor layers and having an impurity concentration higher than that of the first semiconductor layer, wherein the first semiconductor layer is arranged in a cross-sectional direction of the semiconductor substrate. A method of designing an insulated gate bipolar transistor including a recombination center lattice defect having one density distribution peak is also disclosed. In this design method, first, in the cross-sectional direction of the semiconductor substrate, the width of a non-depleted region where the electric field strength at the end of turn-off is zero is determined, and then the recombination center lattice defect is determined as the density distribution It arrange | positions in a said 1st semiconductor layer so that the peak position of a peak may be located inside the width | variety of the said non-depletion area | region from the back surface of the said semiconductor substrate. This makes it possible to easily design the insulated gate bipolar transistor disclosed in the present application. The width of the non-depleted region where the electric field strength at the end of turn-off becomes zero can be determined by simulation, for example.

In the above design method, the recombination center lattice defect may be arranged such that the main surface side half-value width position of the density distribution peak is located inside the width of the non-depleted region from the back surface of the semiconductor substrate. You may arrange | position to a semiconductor layer. Further, the recombination center lattice defect is arranged in the first semiconductor layer so that a main surface side skirt tip position of the density distribution peak is located inside a width of the non-depleted region from the back surface of the semiconductor substrate. May be.
In the above design method, the thickness of the semiconductor substrate may be not less than 120 μm and not more than 200 μm. The insulated gate bipolar transistor may be a trench gate type IGBT having an insulated trench gate formed so as to penetrate the second semiconductor layer.

The effect of the insulated gate bipolar transistor designed by the above design method is as described above, and the description thereof is omitted.

As described above, the insulated gate bipolar transistor and the design method thereof are the insulated gate bipolar transistor and the design method thereof, and has a simple lifetime control structure capable of precisely controlling the lifetime of residual holes. Thus, an insulated gate bipolar transistor which has a small tail loss and can be switched at high speed, and a design method thereof are provided.

FIG. 15 is an example of a simulation result of the IGBT shown in FIG. 14 and is a diagram showing a distribution of electric field strength in a cross-sectional direction of a semiconductor substrate 10. It is an example of the simulation result of IGBT shown in FIG. 14, and is a diagram showing the distribution of hole density in the cross-sectional direction of the semiconductor substrate. It is the figure which showed an example of the basic structure of IGBT which concerns on this application, and is typical sectional drawing of IGBT. FIG. 4 is a diagram showing an example of a simulation result of the IGBT shown in FIG. 3, and a recombination center lattice defect having a Gaussian distribution with a constant hole lifetime value at the peak position Dc and the peak position Dc of the recombination center lattice defect D. It is a figure which shows each simulation model at the time of changing the one-side half value width of D. FIG. FIG. 4 shows an example of a result of verifying the coincidence state when the recombination center lattice defect D is formed in the actual IGBT with each simulation model shown in FIG. 4, when helium (He) ions are irradiated as the recombination center lattice defect D. It is the figure which showed the spreading | diffusion resistance value in a silicon (Si) board | substrate. FIG. 5 is a diagram illustrating an example of a simulation result for each model illustrated in FIG. 4, in which the impurity concentration of the fourth semiconductor layer 4 as a collector layer is changed for each model, and the relationship between the on-voltage and the turn-off loss is plotted. . It is the figure which extracted and showed a part of data shown in FIG. 6, and is the figure which showed the relationship between the half value width of one side and the turn-off loss in the ON voltage 2.3V. The figure showing the relationship between the peak position Dc of the recombination center lattice defect D and the turn-off loss. The half-value width on one side is 5 μm, and the hole lifetime values at the peak position Dc are 3.0e ⁻⁸ sec and 6.0e ⁻ , respectively. ^In the case of ⁸ sec, the relationship between the peak position Dc and the turn-off loss when the on-voltage is 2.3V is shown. Each simulation model when the half-value width (and its peak position Dc) is changed by making the main surface side skirt tip position Des of the recombination center lattice defect D coincide with 108 μm which is the end of the non-depleted region. FIG. FIG. 10 is a diagram showing the relationship between the half-value width at one side and the turn-off loss at an ON voltage of 2.3 V, as a result of simulation for each model shown in FIG. 9. The figure shows the relationship between the hole lifetime value at the peak position Dc and the turn-off loss. The hole position when the peak position Dc of the recombination center lattice defect D is 125 μm, the half width at one side is 5 μm, and the ON voltage is 2.3V. The relationship between lifetime value and turn-off loss is shown. A plot of the on-voltage and turn-off loss obtained by simulation for the case where the design target value of the turn-off loss is 9.5 mJ and the structural parameters of the IGBT shown in FIG. 3 and the IGBT shown in FIG. 14 are changed. It is. FIG. 15 is a diagram in which the same simulation as that of FIG. 12 is performed with the design target values of turn-off loss being 8.5 mJ and 9.5 mJ, respectively, and the ON-voltage characteristic variation is compared for the IGBT 100 of FIG. 3 and the IGBT 90 of FIG. . It is a typical example of FS type IGBT and is a schematic sectional view of IGBT. It is the figure which showed the characteristic at the time of turn-off about general IGBT, and is the figure which showed the waveform of the gate voltage Vg at the time of turn-off, the collector voltage Vc, and the collector current Ic. It is the figure which showed typically the characteristic at the time of turn-off about general IGBT, and is the figure which showed the waveform of the work rate VcxIc concerning the loss at the time of turn-off.

Hereinafter, modes for carrying out the present invention will be described with reference to the drawings.

First, in order to analyze the phenomenon (tail current) in which the collector current Ic peculiar to the IGBT described in FIG. 15 and FIG. 16 has a tail, a simulation of the IGBT 90 shown in FIG. 14 was performed.

FIGS. 1 and 2 are examples of simulation results of the IGBT 90. FIG. 1 is a diagram showing the electric field intensity distribution in the cross-sectional direction of the semiconductor substrate 10. FIG. 2 shows the hole density in the cross-sectional direction of the semiconductor substrate 10. FIG. 1 and 2 show the electric field intensity distribution and the hole density distribution at each stage of the collector current Ic = 180, 100, 50, 30, 15, 5, 0 [A] during turn-off, respectively. The collector current Ic when the IGBT 90 is in a conductive state is set to 200 [A]. In the simulations of FIGS. 1 and 2, the thickness of the semiconductor substrate 10 is 165 μm, and the specific resistance of the first semiconductor layer 1 of N conductivity type (N−) which is a carrier drift region is 60 Ωcm. The thicknesses of the fourth semiconductor layer 4 and the fifth semiconductor layer 5 are both 1 μm.

When the IGBT 90 is turned off and Ic decreases, the electric field strength increases from the main surface side to the back surface side of the semiconductor substrate 10 as shown in FIG. 1, and accordingly, as shown in FIG. The depleted region (region where the hole density on the main surface side in each stage of Ic is low) also extends toward the back surface side. That is, when the IGBT 90 is turned off, the gate applied voltage is zero-biased, the injection of electrons from the MOS transistor on the main surface side is stopped, Ic decreases, and the system voltage applied between the collector and emitter of the IGBT 90 As a result, the depletion region expands from the junction surface of the second semiconductor layer 2 of P conductivity type (P) and the first semiconductor layer 1 of N conductivity type (N−) toward the back surface side. At each stage of Ic, in the depletion region, holes are immediately swept out to the emitter on the main surface side by the electric field strength shown in FIG. On the other hand, in the region where the electric field intensity in FIG. 1 on the back side of the semiconductor substrate 10 is zero, holes remain only during the lifetime in silicon (Si) (residual holes). The phenomenon in which the collector current Ic shown in FIG. 15 has a tail (tail current) appears as a tail current until the hole expires after the lifetime.

As can be seen from FIG. 1, in the IGBT 90, even if Ic = 0 [A], a region where the electric field strength indicated by the double-pointed arrow in the figure is zero remains on the back side of the semiconductor substrate 10, and this region is not covered. The width of the depleted region can be strictly defined. In FIG. 1, the depth of the electric field intensity tip at Ic = 0 [A] is 108 μm, and the width of the non-depleted region is 55 μm.

As described above, in the field stop (FS) type IGBT 90 shown in FIG. 14, tail current is generated due to residual holes as in the punch-through (PT) type and non-punch-through (NPT) type IGBTs. I was able to confirm. Therefore, the introduction of lifetime control of residual holes was studied based on the simulation results of FIGS. 1 and 2 for the FS-type IGBT, whose thinning is the greatest merit and it is difficult to realize a lifetime control structure. .

FIG. 3 is a diagram showing a basic structure of an insulated gate bipolar transistor (IGBT) according to the present invention, and is a schematic cross-sectional view of the IGBT 100. In the IGBT 100 shown in FIG. 3, the same reference numerals are given to the same parts as those of the IGBT 90 shown in FIG.

3 is different from the IGBT 90 shown in FIG. 14 in that a recombination center lattice defect (so-called residual hole lifetime killer) D having one density distribution peak is arranged.

That is, the IGBT 100 of FIG. 3 is formed in the first semiconductor layer 1 composed of the N-conductivity type (N−) semiconductor substrate 10 and the surface layer portion on the main surface side of the semiconductor substrate 10 in the same manner as the IGBT 90 of FIG. It has a second semiconductor layer 2 of P conductivity type (P) and a third semiconductor layer 3 of N conductivity type (N +) selectively formed on the surface layer portion of the second semiconductor layer 2. Note that a portion indicated by reference numeral G formed so as to penetrate the second semiconductor layer 2 is a gate electrode (insulating trench gate) having a trench structure, and the second semiconductor layer 2 is a channel formation region called a base layer. The third semiconductor layer 3 is an emitter region. The emitter electrode E is formed on the semiconductor substrate 10 on the main surface side so as to be commonly connected to the second semiconductor layer 2 and the third semiconductor layer 3 via the interlayer insulating film 6.

The IGBT 100 includes a fourth semiconductor layer 4 of P conductivity type (P +) formed in the surface layer portion on the back surface side of the semiconductor substrate 10, and N formed between the first semiconductor layer 1 and the fourth semiconductor layer 4. The fifth semiconductor layer 5 has a conductivity type (N) and an impurity concentration higher than that of the first semiconductor layer 1. The fourth semiconductor layer 4 is a collector region, and a collector electrode C is formed on the semiconductor substrate 10 on the back surface side so as to be connected to the fourth semiconductor layer 4. The fifth semiconductor layer 5 is a so-called FS layer, and the first semiconductor layer 1 is a carrier drift region in the IGBT 90.

On the other hand, the IGBT 100 in FIG. 3 is different from the IGBT 90 in FIG. 14 in that the recombination center lattice defect D having one density distribution peak in the cross-sectional direction of the semiconductor substrate 10 is indicated by a one-dot chain line in the diagram of the recombination center lattice defect D. Is located in the first semiconductor layer 1 so as to be located inside the width W of the non-depleted region at the end of turn-off determined by simulation from the back surface of the semiconductor substrate 10. In FIG. 3, the main surface side half-value width position Dhs and the back surface side half-value width position Dhb of the density distribution peak of the recombination center lattice defect D having a Gaussian distribution are indicated by broken lines in the figure, and the lifetime value of the hole is peaked. The main surface side hem tip position Des and the back surface side skirt tip position Deb, which are 100 times the lifetime value at the position Dc and substantially fail to exhibit the function of the lifetime killer, are indicated by dotted lines in the drawing.

As described above, the IGBT 100 of FIG. 3 has the first semiconductor layer 1 as a drift layer (body layer), the second semiconductor layer 2 as a channel formation layer, the third semiconductor layer 3 as an emitter layer, and the fourth semiconductor layer. 4 is a collector layer and the fifth semiconductor layer 5 is a field stop (FS) layer. The fourth semiconductor layer 4 and the fifth semiconductor layer 5 are thin layers of about 1 μm. Also, the first semiconductor layer 1 that is a drift layer (body layer) may be, for example, 200 μm or less.

As described with reference to FIGS. 15 and 16, in the IGBT, generally, after the gate is turned off and the collector current Ic rapidly decreases to about 20% at the time of on, due to the influence of residual holes in the drift layer, A phenomenon (tail current) that pulls the tail occurs. In order to reduce the tail current, reduce tail loss associated with the tail current, and increase the switching speed, the FS-type IGBT 100 of FIG. 3 has a single density distribution peak in the cross-sectional direction of the semiconductor substrate 10. The bond center lattice defect D is such that the peak position Dc is located on the inner side of the width W of the non-depleted region at the end of turn-off determined from the back surface of the semiconductor substrate 10 by the simulation shown in FIGS. 1 is disposed in the semiconductor layer 1. Specifically, the recombination center lattice defect D is locally formed by irradiating ions such as proton, deuterium (dutron), and helium from the back surface side of the semiconductor substrate 10.

The recombination center lattice defect D in the FS type IGBT 100 of FIG. 3 has a simple structure having one density distribution peak in the cross-sectional direction of the semiconductor substrate 10, and even the thin FS type IGBT 100 can be easily formed. Can be realized. In addition, when the recombination center lattice defect D is formed by ion irradiation as described above, the recombination center lattice defect D having one density distribution peak can be formed by one ion irradiation, so that the cost is low. is there.

The distribution of the recombination center lattice defect D can be accurately determined by simulation as will be described later, and the peak position Dc of the recombination center lattice defect D is determined by the simulation shown in FIGS. As will be described later, the recombination center lattice defect D is introduced by being arranged in the first semiconductor layer 1 so as to be located inside the width W of the non-depleted region where the electric field intensity at the end of turn-off becomes zero. Compared to the case where the on-state voltage is not applied, the tail loss can be reduced and the switching speed can be increased without increasing the on-voltage.

The lifetime control of residual holes due to the recombination center lattice defect D of the FS-type IGBT 100 is different from, for example, a method of appropriately controlling the impurity concentration of the fourth semiconductor layer 4 and the fifth semiconductor layer 5 to suppress the hole injection efficiency. The contact resistance with the collector electrode connected to the fourth semiconductor layer 4 does not increase, and the current driving capability of the FS IGBT does not decrease.

4 to 6 are diagrams showing an example of the simulation of the IGBT 100 shown in FIG.

FIG. 4 shows simulations when the half-value width of the recombination center lattice defect D having a Gaussian distribution is changed while the hole lifetime values at the peak position Dc and the peak position Dc of the recombination center lattice defect D are constant. It is a figure which shows a model. In the simulation of FIG. 4, as in the simulations of FIGS. 1 and 2, the thickness of the semiconductor substrate 10 is set to 165 μm, and the first semiconductor layer 1 of N conductivity type (N−), which is a carrier drift region. The specific resistance is set to 60 Ωcm. The thicknesses of the fourth semiconductor layer 4 and the fifth semiconductor layer 5 are both 1 μm.

FIG. 5 is an example of a result of verifying the coincidence situation when each simulation model shown in FIG. 4 and the recombination center lattice defect D are formed in the actual IGBT 100. It is the figure which showed the spreading | diffusion resistance value in a silicon | silicone (Si) board | substrate when irradiated.

FIG. 6 is a simulation result for each model shown in FIG. 4, in which the impurity concentration of the fourth semiconductor layer 4 as the collector layer is changed for each model, and the relationship between the on-voltage and the turn-off loss is plotted. is there. In FIG. 6, regarding the simulation results of the IGBT 90 in which the recombination center lattice defect D shown in FIGS. 14, 1 and 2 is not arranged, the relationship between the on-voltage and the turn-off loss is shown by a broken line (lifetime). No control).

In each simulation model of FIG. 4, the peak position Dc of the recombination center lattice defect D is set to a position where the depth from the main surface of the substrate is 120 μm, and is determined from the back surface of the semiconductor substrate 10 by the simulations of FIGS. The recombination center lattice defect D is arranged in the first semiconductor layer 1 so that the peak position Dc is located inside the non-depleted region width W = 55 μm at the end of turn-off. Further, assuming that the hole lifetime value τh at the peak position Dc is 3.0e ⁻⁸ sec, the half-width parameters on one side of the Gaussian distribution recombination center lattice defect D are 5.0, 7.5, 10. 0, 12.5, 15.0, 17.5 μm. In FIG. 4, as in FIG. 3, the peak position Dc of the recombination center lattice defect D is indicated by a one-dot chain line, and the main surface side half-value width Dhs when the one-side half-value width is 5.0 μm is indicated by a broken line. The main surface side hem tip position Des when the value width is 5.0 μm is indicated by a dotted line in the drawing.

The spreading resistance value of silicon (Si) when irradiated with helium (He) ions shown in FIG. 5 has a generally Gaussian distribution, the half-value width on one side is about 5 μm, and the resistance value is stabilized from the peak of the spreading resistance value. The distribution up to the main surface side hem tip position is approximately 20 μm, and is approximately in agreement with the distribution of hole lifetime values for the simulation model shown in FIG. Although it is generally difficult to create a distribution of spreading resistance values with a half-value width smaller than 5 μm by He ion irradiation, other simulation models with a half-value width larger than 5.0 μm shown in FIG. As for the distribution of the same spreading resistance value, a distribution of 5 to 15 μm can be formed by changing the He ion irradiation conditions.

As shown in FIG. 6, the on-voltage and the turn-off loss, which are the characteristics of the IGBT, generally have a trade-off relationship, and the turn-off loss increases as the on-voltage decreases. On the other hand, the characteristics of the IGBT are better as it is in the lower left region of FIG. 6 where both the on-voltage and the turn-off loss are lower. As can be seen from FIG. 6, the peak position Dc of the recombination center lattice defect D is located at a depth of 120 μm from the substrate main surface, and the peak position Dc is located inside the non-depleted region width W = 55 μm. With respect to each simulation model of FIG. 4 arranged as described above, any one-sided half-value width simulation model has better characteristics than those without the lifetime control indicated by the broken line in the figure.

As described above, the insulated gate bipolar transistor (IGBT 100) illustrated in FIGS. 3 and 4 is an FS-type insulated gate bipolar transistor that can be thinned, and precisely controls the lifetime of residual holes. Therefore, it is possible to provide an insulated gate bipolar transistor that has a simple lifetime control structure and that can perform high-speed switching with low tail loss.

Next, a more preferred embodiment of the above-described IGBT 100 will be described.

FIG. 7 is a diagram showing a part of the data shown in FIG. 6 and showing the relationship between the half width at one side and the turn-off loss at the on-voltage 2.3V.

As exemplified by the data at an on-voltage of 2.3 V in FIG. 7, in each simulation model of FIG. 4, the turn-off loss is stable at a small value when the half-value width on one side is 10 μm or less. At 12.5 μm or more, the turn-off loss increases as the half width on one side increases.

As shown in FIG. 4, when the half width at one side is 10 μm or less, the main surface side half width position Dhs is inside the width W of the non-depleted region, whereas when the half width at one side is 12.5 μm or more, The main surface side half-value width position Dhs is outside the width W of the non-depleted region. Therefore, the result shown in FIG. 7 shows that when the half width on one side is 10 μm or less, the main surface half width position Dhs is on the inner side of the width W of the non-depleted region, so that the ON resistance does not increase and the turn-off loss is small. When the half-width on one side is 12.5 μm or more, the main surface half-width position Dhs is outside the width W of the non-depleted region, the on-resistance increases, and the turn-off loss increases due to the trade-off relationship. Can be considered.

As described above, in the IGBT 100 described above, the recombination center lattice defect D is such that the main surface side half-value width position Dhs of the density distribution peak is located inside the width W of the non-depleted region from the back surface of the semiconductor substrate 10. In addition, it is preferably disposed in the first semiconductor layer 1. According to this, the distribution of the recombination center lattice defect D is more surely contained in the non-depleted region, and the tail loss can be reduced and the switching speed can be increased more stably.

FIG. 8 is a diagram showing the relationship between the peak position Dc of the recombination center lattice defect D and the turn-off loss. The half-value width at one side is 5 μm, and the hole lifetime value at the peak position Dc is 3.0e ⁻⁸ sec. In the case of 6.0e ⁻⁸ sec, the relationship between the peak position Dc and the turn-off loss when the on-voltage is 2.3V is shown. In the simulation of FIG. 8, the thickness of the semiconductor substrate 10 is 165 μm, and the specific resistance of the first semiconductor layer 1 is 60 Ωcm.

As shown in FIG. 8, if the peak position Dc of the recombination center lattice defect D is within the width W of the non-depleted region, the peak values of the hole lifetime are 3.0e ⁻⁸ sec and 6.0e ⁻⁸ sec. In either case, the turn-off loss can be lower than 10.9 mJ when the lifetime control is not performed. On the other hand, when the peak position Dc of the recombination center lattice defect D is outside the width W of the non-depleted region, the turn-off loss increases rapidly. Thus, the recombination center lattice defect D having one density distribution peak in the cross-sectional direction of the semiconductor substrate 10 is a non-depleted region at the end of turn-off in which the peak position Dc is determined by simulation from the back surface of the semiconductor substrate 10. It is necessary to be disposed in the first semiconductor layer 1 so as to be located inside the width W of the first semiconductor layer 1. In FIG. 8, when the peak position Dc is arranged at a depth of about 125 μm from the main surface of the substrate, the turn-off loss is minimized, and the peak values of the hole lifetime are 3.0e ⁻⁸ sec and 6.0e ⁻⁸ sec. The minimum values are 9.3 mJ and 9.8 mJ, respectively.

FIG. 9 shows a case where the half-value width (and its peak position Dc) is changed by making the main surface side skirt tip position Des of the recombination center lattice defect D coincide with 108 μm which is the end of the non-depleted region. It is a figure which shows each simulation model. FIG. 10 is a simulation result for each model shown in FIG. 9 and shows the relationship between the half-value width at one side and the turn-off loss at an on-voltage of 2.3V.

As shown in FIG. 9, the main surface side skirt tip Des of the recombination center lattice defect D is made to coincide with the end of the non-depleted region, so that the entire recombination center lattice defect D has a width W To be located inside. In this case, as shown in FIG. 10, the turn-off loss hardly changes between 9.2 and 9.3 mJ, and a low turn-off loss having no dependency on the half width on one side can be obtained.

As described above, in the IGBT 100 described above, the recombination center lattice defect D is the first so that the main surface side skirt tip position Des is located inside the width W of the non-depleted region from the back surface of the semiconductor substrate 10. More preferably, it is arranged in the semiconductor layer 1. According to this, the distribution of the recombination center lattice defect D is more surely non-depleted as compared with the case where the main surface half-width position Dhs described in FIG. 7 is located inside the width W of the non-depleted region. Thus, tail loss can be reduced and switching speed can be increased more stably.

FIG. 11 is a diagram showing the relationship between the hole lifetime value and the turn-off loss at the peak position Dc. The peak position Dc of the recombination center lattice defect D is 125 μm, the half width at one side is 5 μm, and the ON voltage is 2.3 V. The relationship between the hole lifetime value and the turn-off loss is shown.

As shown in FIG. 11, with respect to the hole lifetime value at the peak position Dc, if the peak value is in a range of about 2.0e ⁻⁷ sec or less, the turn-off loss is lower than that in the case where lifetime control is not performed. be able to. In addition, a turn-off loss of 9.1 mJ, which is the minimum value, is obtained when the peak value is in the range of 1.0 to 2.0e ⁻⁸ sec. By setting the peak value within this range, a lower turn-off loss can be achieved. It can be realized stably.

As described above, each of the above-described insulated gate bipolar transistors has a simple lifetime control structure capable of precisely controlling the lifetime of residual holes, and has low tail loss and high speed switching. Possible insulated gate bipolar transistors.

As described above, the insulated gate bipolar transistor is intended for a thin FS type IGBT, and is suitable when the thickness of the semiconductor substrate 10 shown in FIG. 3 is 120 μm or more and 200 μm or less. is there.

Further, the insulated gate bipolar transistor may be a trench gate type IGBT having an insulated trench gate G formed so as to penetrate the second semiconductor layer 2 as shown in FIG. 3, for example.

Further, the design method of the insulated gate bipolar transistor according to the design procedure of the insulated gate bipolar transistor described above is as follows. That is, by simulation, first, in the cross-sectional direction of the semiconductor substrate 10 shown in FIG. 3, as described in FIGS. 1 and 2, the width W of the non-depleted region where the electric field strength at the end of turn-off becomes zero is determined. Then, the recombination center lattice defect D is more preferably formed in the non-depleted region so that the peak position Dc of the density distribution peak is located inside the width W of the non-depleted region from the back surface of the semiconductor substrate 10. More preferably, the main surface side hem tip position Des of the density distribution peak is positioned inside the width W of the non-depleted region so that the main surface side half width position Dhs of the density distribution peak is positioned inside the width W. In the first semiconductor layer 1. As a result, it is possible to easily design the above-described insulated gate bipolar transistor that has a small tail loss and can perform high-speed switching.

Next, in the case where the IGBT 100 shown in FIG. 3 and the IGBT 90 shown in FIG. 14 are designed, characteristic variations when the structural parameters are changed to obtain predetermined characteristics will be described.

12 plots the on-voltage and the turn-off loss obtained by the simulation when the design target value of the turn-off loss is 9.5 mJ and the structural parameters of the IGBT 100 in FIG. 3 and the IGBT 90 in FIG. 14 are changed. FIG.

In the IGBT 100 shown in FIG. 3, the peak position Dc of the recombination center lattice defect D is set to a position where the depth from the substrate main surface is 125 μm, and the half width on one side is 5.0 μm. Each point of the IGBT 100 surrounded by a solid line in the figure is related to the manufacturing process. (1) Carrier concentration variation due to ion implantation of the fourth semiconductor layer 4 as the collector layer and the fifth semiconductor layer 5 as the FS layer: ± 5 %, (2) Ion irradiation depth variation when forming recombination center lattice defect D: ± 7.5 μm, (3) Ion irradiation amount variation when forming recombination center lattice defect D: ± 5% It is a value obtained by carrying out a simulation using an experimental design method with a variation factor and a variation range. In addition, each point of the IGBT 90 surrounded by a broken line in the figure is a value obtained by using only the above (1) as a variation factor and a variation range.

As shown in FIG. 12, the IGBT 100 in which the recombination center lattice defect D for lifetime control is arranged is designed to have the same turn-off loss of 9.5 mJ as compared with the IGBT 90 that is not subjected to lifetime control. Even so, it is possible to reduce both variations in on-voltage and turn-off loss characteristics with respect to variations in manufacturing processes.

FIG. 13 shows simulation results similar to FIG. 12 with the turn-off loss design target values set to 8.5 mJ and 9.5 mJ, respectively, and shows a comparison of on-voltage characteristic variations for the IGBT 100 of FIG. 3 and the IGBT 90 of FIG. It is a figure. The on-voltage variation [%] shown in FIG. 13 is calculated as (maximum value−minimum value) / 2 * average value with respect to each variation of the on-voltage with respect to the IGBT 100 and the IGBT 90 in FIG.

As shown in FIG. 13, as the design target value of the turn-off loss is decreased to increase the speed of the IGBT, the difference in characteristic variation regarding the on-voltage between the IGBT 100 and the IGBT 90 increases. When the design target value of turn-off loss is 9.5 mJ, the characteristic variation of the IGBT 100 can be reduced by 44% with respect to the characteristic variation of the on-voltage of the IGBT 90, whereas the design target value of the turn-off loss is 8.5 mJ. In this case, the characteristic variation of the IGBT 100 can be reduced by 60% with respect to the characteristic variation of the on-voltage of the IGBT 90.

As shown in FIG. 12 and FIG. 13, in the IGBT 100 in which the recombination center lattice defect D for lifetime control is arranged, the IGBT is turned on with respect to variations in the manufacturing process as compared with the IGBT 90 not performing lifetime control. Although both the voltage and turn-off loss characteristic variations can be reduced, it is considered that this is caused by the difference in carrier concentration between the IGBT 100 and the IGBT 90. That is, in the IGBT 90 that is not subjected to lifetime control, in order to suppress the hole injection efficiency, the P-type impurity concentration of the fourth semiconductor layer 4 that is the collector layer is lowered, and the N of the fifth semiconductor layer 5 that is the FS layer is reduced. It is necessary to increase the type impurity concentration. For this reason, the fourth semiconductor layer 4 and the fifth semiconductor layer 5 are designed so that the carrier concentrations are close to each other, and the characteristic variation tends to increase. In contrast, in the IGBT 100 in which the recombination center lattice defect D for lifetime control is arranged, the carrier concentration of the fourth semiconductor layer 4 that is the collector layer is changed to the carrier concentration of the fifth semiconductor layer 5 that is the FS layer. Since it can be set larger than this, it is considered that this reduces the characteristic variation.

As described above, the above-described insulated gate bipolar transistor and its design method are an FS type insulated gate bipolar transistor that can be thinned and its design method, and it is possible to precisely control the lifetime of residual holes. An insulated gate bipolar transistor that has a simple lifetime control structure that can be performed, has low tail loss, and can perform high-speed switching, and a design method thereof.

As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

The technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

Claims (10)

Selected as a first semiconductor layer made of a semiconductor substrate of a first conductivity type, a second semiconductor layer of a second conductivity type formed in a surface layer portion on the main surface side of the semiconductor substrate, and a surface layer portion of the second semiconductor layer First-conductivity-type third semiconductor layer, a second-conductivity-type fourth semiconductor layer formed in a surface layer portion on the back side of the semiconductor substrate, the first semiconductor layer, and the fourth semiconductor An insulated gate bipolar transistor having a first semiconductor type and a fifth semiconductor layer formed between the layers and having an impurity concentration higher than that of the first semiconductor layer,
The first semiconductor layer includes a recombination center lattice defect having one density distribution peak in a cross-sectional direction of the semiconductor substrate;
The recombination center defect is disposed in the first semiconductor layer so that the peak position of the density distribution peak is located inside the width of the non-depleted region at the end of turn-off from the back surface of the semiconductor substrate. Gate bipolar transistor. The recombination center lattice defect is disposed in the first semiconductor layer such that a main surface side half-value width position of the density distribution peak is located inside a width of the non-depleted region from the back surface of the semiconductor substrate. The insulated gate bipolar transistor according to claim 1. The recombination center lattice defect is arranged in the first semiconductor layer so that a main surface side skirt tip position of the density distribution peak is located inside a width of the non-depleted region from the back surface of the semiconductor substrate. The insulated gate bipolar transistor according to claim 2. The insulated gate bipolar transistor according to any one of claims 1 to 3, wherein a thickness of the semiconductor substrate is 120 µm or more and 200 µm or less. 5. The insulation according to claim 1, wherein the insulated gate bipolar transistor is a trench gate type IGBT having an insulated trench gate formed so as to penetrate the second semiconductor layer. 6. Gate bipolar transistor. Selected as a first semiconductor layer made of a semiconductor substrate of a first conductivity type, a second semiconductor layer of a second conductivity type formed in a surface layer portion on the main surface side of the semiconductor substrate, and a surface layer portion of the second semiconductor layer First-conductivity-type third semiconductor layer, a second-conductivity-type fourth semiconductor layer formed in a surface layer portion on the back side of the semiconductor substrate, the first semiconductor layer, and the fourth semiconductor A fifth semiconductor layer having a first conductivity type formed between the layers and having an impurity concentration higher than that of the first semiconductor layer;
The first semiconductor layer is a method for designing an insulated gate bipolar transistor including a recombination center lattice defect having one density distribution peak in a cross-sectional direction of the semiconductor substrate,
First, in the cross-sectional direction of the semiconductor substrate, determine the width of the non-depleted region where the electric field strength at the end of turn-off is zero,
Next, the recombination center lattice defect is disposed in the first semiconductor layer so that the peak position of the density distribution peak is located inside the width of the non-depleted region from the back surface of the semiconductor substrate. Design method of gate bipolar transistor. The recombination center lattice defect is disposed in the first semiconductor layer such that a main surface side half-value width position of the density distribution peak is located inside a width of the non-depleted region from the back surface of the semiconductor substrate. The method for designing an insulated gate bipolar transistor according to claim 6. The recombination center lattice defect is disposed in the first semiconductor layer such that the main surface side skirt tip position of the density distribution peak is located inside the width of the non-depleted region from the back surface of the semiconductor substrate. The method for designing an insulated gate bipolar transistor according to claim 7. The method for designing an insulated gate bipolar transistor according to any one of claims 6 to 8, wherein a thickness of the semiconductor substrate is 120 µm or more and 200 µm or less. 10. The insulation according to claim 6, wherein the insulated gate bipolar transistor is a trench gate type IGBT having an insulated trench gate formed so as to penetrate the second semiconductor layer. Design method of gate bipolar transistor.

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