WO2010136668A1 - Electric circuit simulator - Google Patents

Abstract

The invention relates to an electric circuit simulator, including: a library (6), including circuit components, each having characteristics suitable for simulating the behaviour thereof, at least some of which are associated with a dynamic equation, and/or an input/output equation with a domain delimitation expression defining the possible state parameters for the component in question; a builder (4), arranged so as to calculate a model (16) of a circuit from a representation of said circuit (14) by the components thereof and the interconnections of the latter, forming a triplet of sets of equations which relate to the dynamic equations, to the input/output equations, and to the domain-delimitations of said circuit, respectively; a solver (12), arranged to calculate a subsequent state of a circuit from the model thereof and a prior state; and a simulation engine (8), arranged to invoke the builder (4) with the representation of a circuit, and to run the solver (12) with the model resulting from an initial state of the circuit, and to repeat said execution according to the last subsequent calculated state until fulfilling a condition relating to the number of executions or to the last subsequent calculated state.

Description

 Improved electrical circuit simulator

The invention relates to the simulation of electrical circuits.

Many tools have been developed to model electronic circuits. These tools allow designers to validate their drawings before actual production.

These tools include analog simulation tools, numerical simulation tools, and hybrid tools.

The numerical simulation tools are mainly adapted to the simulation of digital components, they provide a rather "high level" view of the operation, and their simulations do not allow to take into account the interferences that can take place at "low level", between the components analog devices that perform digital functions.

Analog simulation tools are suitable for circuit simulation based on models of the physical behavior of each of the circuit components.

Among these tools, SPICE is the most used and represents a standard that is widely used. However, the solutions provided by SPICE, and more generally the analog simulation tools, depend on the convergence of the Newton-Raphson method applied to a representation of the circuit concerned.

And the method of Newton-Raphson very poorly supports components whose characteristics are non-regular and non-linear.

As a result, for components as simple and basic as a diode, it is necessary to resort to modeling artifacts of these components, which obviously deteriorate the quality of the simulation. This is particularly unsuitable for the simulation of mixed digital-analog type circuits, which by their nature include non-regular and non-linear elements.

Hybrid tools work for their part by characterizing a circuit or a portion of the circuit, and using an analog or digital simulation according to this characterization. These tools are time-consuming and poorly adapted to the simulation of electrical circuits as soon as they begin to be complex. In general, these tools tend to combine the disadvantages of digital and analog simulation tools, without actually combining their advantages.

The invention improves the situation.

To this end, the invention proposes an electric circuit simulator comprising: a library, comprising circuit components, each with characteristics that make it possible to simulate its behavior, at least some of which are associated with a dynamic equation, and / or one input / output equation with a domain delimitation expression defining the possible state parameters for the component concerned, - a constructor, arranged to calculate a model of a circuit, from a representation of this circuit by its components and their interconnections, in the form of a triplet of sets of equations which relate respectively to the dynamic equations, the input / output equations and the domain boundaries of the components of this circuit, - a solver, arranged to compute a posterior state of a circuit, from its model and from a previous state, and

a simulation engine, arranged to call the constructor with the representation of a circuit, and to execute the solver with the resulting model from an initial state of the circuit, and to repeat this execution from the last calculated later state up to a condition relating to the number of executions or the last calculated later state. As will be seen later, this simulator has many advantages, including automatic equation, and improved simulation of switched circuits.

Other features and advantages of the invention will appear better on reading the following description, taken from examples given for illustrative and non-limiting purposes, taken from the drawings in which:

FIG. 1 represents a schematic view of an electric circuit simulator according to the invention,

FIG. 2 represents a general operating diagram of the simulator of FIG. 1,

FIG. 3 represents a general operating diagram of the manufacturer of FIG. 1,

FIG. 4 represents an exemplary implementation of part of the second operation of FIG. 3; FIG. 5 represents an example of implementation of another part of the second operation of FIG. 3;

FIG. 6 represents an exemplary implementation of a third operation of FIG. 3,

FIG. 7 represents an exemplary implementation of an operation of FIG. 2; FIG. 8 represents a part of an operation of FIG.

FIGS. 9 to 13 represent exemplary implementations of functions of FIG. 8,

FIG. 14 represents an exemplary implementation of an operation of FIG. 2,

FIG. 15 represents an exemplary implementation of an operation of FIG. 2; FIG. 16 another exemplary implementation of a function of FIG. 8, and

FIG. 17 represents a circuit whose simulation by the tool of the invention is described as an example.

The drawings and the description below contain, for the most part, elements of a certain character. Thus, they can not only serve to better understand the present invention, but also contribute to its definition, if necessary. This description is likely to involve elements likely to be protected by copyright and / or copyright. The rights holder has no objection to the identical reproduction by anyone of this patent document or its description, as it appears in the official records. For the rest, he reserves his rights in full.

In addition, the detailed description is augmented by Appendix A, which gives the formulation of certain mathematical formulas implemented in the context of the invention. This Annex is set aside for the purpose of clarification and to facilitate referrals. It is an integral part of the description, and can therefore not only serve to better understand the present invention, but also contribute to its definition, if any.

FIG. 1 represents a schematic view of an electric circuit simulator 2 according to the invention.

The simulator 2 comprises a constructor 4, a library 6, and a simulation engine 8. The simulation engine 8 comprises a gearbox 10 and an exploration mechanism 12.

The manufacturer 4 receives circuit data to be simulated 14. The data 14 comprises a description of the components that make up the circuit, as well as their interconnections in this circuit. The data 14 also includes simulation parameters, as well as an initial state of the circuit. As will be seen below, this initial state can be complete or partial.

On the basis of the data 14, the constructor 4 calls the library 6 and retrieves the equations and other characteristics for each of the data components 14. Next, the constructor 4 calculates a representation or model 16 of the circuit from the data taken from the library 6 and interconnections of the data 14. The model 16 is then transmitted to the simulation engine 8, which will perform the actual simulation of the circuit. As will be seen below, the model 16 is a representation of the circuit by a set of vectors in which component identifiers are stored, and not their associated values. Indeed, these components can have complex behaviors, that only the simulation engine 8 will be able to deal adequately.

In a first step, the gearbox 10 performs a time discretization of the model 16, so as to obtain a set of equations whose unknowns are the state parameters of the circuit.

This set of equations will then be designated by the term temporally discretized representation. The purpose of this discretization is to reduce the set of dynamic equations to a set of algebraic equations implementing the simulation parameters at selected moments according to the simulation parameters.

Then, the mechanism 12 starts from the initial state of the circuit, and operates in no time to determine the following states of this circuit. For this, at each time step, the mechanism 12 varies the state parameters of the circuit to obtain a solution that satisfies all the equations of the discretized representation.

Once this solution is obtained, the corresponding set of state parameters constitutes the state of the current circuit, and a new circuit state is calculated in the same way. Each of the circuit states thus calculated is returned to a result file 18 for display and / or post-processing.

The simulation engine 8 stops when a condition which relates to the simulation time, or the state of the circuit is fulfilled.

FIG. 2 represents a general operating diagram of the simulator of FIG. 1. In an operation 20, the simulator receives the data necessary for the simulation. In the example described here, these data are the description of the circuit to be simulated Cir., As well as initialization data Init_Par.

In the example described here, the data Init_Par comprise start state data of the circuit Cir. As will be seen later, this data may be incomplete, and require a first simulation loop to obtain a complete starting state.

In addition, these data may also include parameterization data for the simulation, such as stopping conditions, a simulation time step, convergence tolerances, size identifiers to be observed, and other such data. .

In an operation 22, the constructor 4 uses the data Cir. to build the model 16 that will be used for simulation. The operation of this operation will be detailed with FIGS. 4 and 5.

Once the model 16 has been calculated, the initial simulation state of the circuit is established in an operation 24.

As we have seen above, it is rare that we know the state of each of the elements composing a circuit at the moment when the simulation begins. It is indeed more likely that we know a number of critical inputs, but not all states.

This operation, detailed with FIG. 15, is optional and may be omitted, for example if the state provided in the Init_Par data is sufficiently complete.

Then, a time counter t is initialized in an operation 26. This marks the beginning of the simulation loop carried out by the simulation engine 8. loop, the next state of the circuit is calculated from the current state in an operation 28, based on the model derived from the data 16.

Once the next state has been calculated, a simulation stop condition is tested in an operation 30. This stop condition can for example relate to the total number of executions of the simulation loop, on a stability condition of the state of the circuit or on other conditions.

If the simulation end condition is fulfilled, then the simulation ends with an operation 32, and if not the next time step is simulated with an increment operation of 134 and the return to operation 28.

FIG. 3 represents a generic diagram of implementation of the creation of the model 16 by the controller 4.

As can be seen, this implementation includes three main operations.

In a first operation 40, the data of the circuit Cir. are scanned to automatically determine the components whose parameters will serve as unknowns, as well as to initialize certain elements necessary to calculate the circuit model.

In a second operation 45, the model 16 is calculated. In the embodiment described, the model 16 is a set of identifiers and associated memory spaces that are used by the simulation engine 8 to determine a state of the circuit at each time step.

The model 16 is therefore a kind of shell that the mechanism 8 fills and uses at each iteration. This shell is a set of memory spaces that are selectively filled as described below. Finally, in a third operation 50, the memory spaces required for the model 16 to allow execution of the simulation are reserved.

At this point, it is necessary to take up the theoretical framework in which the invention is inscribed.

The known devices of the prior art are based on what is called "modified nodal analysis" (or MNA, for "Modified Nodal Analysis" in English).

This circuit analysis makes it possible to establish a set of equations according to formula (10) of Appendix A. The formulas (12) to (16) explain the components of formula (10).

In a general way, these equations return to decompose the circuit into its inductive, capacitive, voltage-controlled, current-controlled branches and to order the equations derived from Kirchhoff's voltage and intensity laws, as well as laws specific to each component.

These equations are drawn in part from a principal matrix A, which takes up all Kirchhoff laws by running according to formula (18). The matrix A is then seen according to formula (20).

However, these equations are only valid for regular components.

The work of the Applicant has allowed to modify these equations, to allow to integrate these elements.

For this, any non-regular element is described by a set of equations according to formula (24) of Appendix A. It will be noted that this non-regular element can be linear or not.

indique la portion de la matrice A dont les colonnes correspondent à l'indice k (qui peut être L, C, R, V ou NS), et dont les lignes ont des indices contenus dans le vecteur Nl (défini avec la figure 5). La notation Â_k indique cette même portion, mais dont les lignes ont des indices contenus dans le vecteur N2 (défini avec la figure 5).The Applicant then introduced these equations into those derived from the formula (10), and succeeded in establishing the formula (26), which corresponds to the modified nodal analysis taking into account non-regular and non-linear elements. Formulas (26) and (28) explain the formulation of matrices N and F. In these formulas, the notation

indicates the portion of the matrix A whose columns correspond to the index k (which may be L, C, R, V or NS), and whose lines have indices contained in the vector N1 (defined in FIG. 5) . The notation  _k indicates this same portion, but whose lines have indices contained in the vector N2 (defined in FIG. 5).

The device of the invention makes it possible to perform this equation automatically, and then to simulate the circuit on the basis of this equation.

FIG. 4 represents an exemplary implementation of part of the operation 45.

The operations shown in this figure are intended to prepare a vector Ins and a vector Lns which will receive parameters that make it possible to take into account non-regular and / or non-linear components.

This first part is a loop which begins in an operation 400 by unloading a component of the representation of the circuit Cir., And in an operation 402 by checking in the library 6 to determine if this component is non-regular and / or non-linear.

If the component is non-regular, then in an operation 404, the vector Ins (k) receives the position index of this element in the vector z, and in an operation 406, the vector Lns (k) receives the index position of this element in the lambda vector.

When the component is regular, or after operations 404 and 406 are executed, the loop resumes at 400.

When all the components have been unstacked, this first part ends in an operation 408. FIG. 5 represents an exemplary implementation of a second part of the operation 45.

As we saw above, this operation aims to establish the vectors x and z which are the unknowns of the simulation, and to prepare some other vectors for the future.

In an operation 500, the constructor receives the data Cir. Then, in an operation 502, a spanning tree ST is calculated for the capacitive branches of the circuit.

This tree, as well as its complement N_ST in the set of capacitive branches, is computed by means of a function ST (), which takes the data Cir. as an argument and browsing them by calling the library 6 to determine the trees ST and N_ST.

Surprisingly, the Applicant has discovered that the generation of the matrix N from an algorithm using the recovery tree makes it possible to obtain an invertible matrix on which the simulation according to the invention is based.

There are many algorithms for obtaining the recovery trees, and those skilled in the art will be able to choose an appropriate implementation.

Then, in an operation 504, the vector x is initialized with the list of intensities of the inductive branches Ii, and with the list of voltages of the capacitive branches Uc of the circuit Cir.

This is done by means of a Push () function, which is used to stack the data. It will be noted moreover that in the embodiment described, the vectors x and z, the trees ST and N_ST, are treated as stacks, and manipulated with functions of the type Push () and Pop (). This is indeed particularly practical. However, these elements could be implemented differently, and treated with different functions. Once the trees ST and N_ST and the vector x initialized, the vector z is initialized in an operation 506.

In this operation, the vector z is initialized with the intensities of the voltage sources V, with the intensities of the non-inductive voltage controlled branches Iv, and the intensities of the non-regular components that can be nonlinear Ins.

Finally, in an operation 508, a function Volt () stores all the branches of the circuit Cir. which are not dynamic and voltage-controlled in the vector B. The utility of this vector will appear with Figure 6.

Two loops are then initialized successively to prepare the operation 50.

In the first loop, the tree ST is successively depilated from an operation 510. From the resulting index k, a node 1 of the branch k is chosen in an operation 512. Then, in an operation 514, the node index 1 is stacked in a vector N1.

In a next operation 516, the branch index k is stacked in a vector C1. Finally, in an operation 518, the pair (1; k) is stacked in a vector M. The vector M will be used with FIG. Kirchhoff's law running at node 1 will be written to characterize the dynamics of branch k.

Once these indices are stored, the loop resumes in 510, until the ST tree is emptied.

The second loop then starts in 520 with unstacking of the N_ST tree. In this loop, the intensity of the index element k pared at operation 520 is stored in the vector z in an operation 522. Next, the index k is stacked in an operation 524 in a vector C2 which represents the branches for which the formulation of the dynamic current-intensity relationship of a capacitor will be stored in the matrix N.

The loop is then reiterated at 520. When this second loop ends, a function Rest () stores (or stacks) all the nodes of the data Cir. which have not been stored in Nl in an operation 526.

Finally, the lists C1 and C2 are combined in a list C which therefore receives all the capacitive elements in an operation 528. The list C corresponds to the list of components which was used to establish the cover trees ST and N_ST. Finally, operation 45 ends in 530.

The operation 50 is then carried out from the vectors x and z obtained in the operation 45. Indeed, as we saw above, all the vectors useful for the simulation have dimensions directly related to those of x and z.

Thus, the memory spaces corresponding to these objects are reserved in this operation as follows:

In practice, the matrix F will receive the data related to the functions f1 and f2 of the formula (26) of Appendix A. The data of the function f1 will be stored in the index lines less than dim (x), and the data of function f2 will be stored in the following lines. The matrices G and H will receive the data associated with the functions g and h of the formula (26) of Appendix A. FIG. 6 represents an example of implementation of the operation 50. As we have seen above, this operation aims at establishing the vectors and matrices initialized at the operation 45, in order to obtain the model of the Cir circuit.

To prepare the filling of the matrix N, several successive loops will be executed to allow to fill the lines according to the identified elements.

Thus, the inductive, capacitive elements of the list C1, capacitive list C2, the remaining elements of the list N2, the elements controlled voltage and finally the capacitive elements will be successively processed.

Everything starts with an operation 600, in which an index i is set to 0 (zero). The index i is the line index, which will be incremented over the loops for each line.

In an operation 602, an Ind () function that takes the data Cir. as argument is executed and returns a list L which includes the inductive elements of the circuit.

Then, the first loop is executed, which comes to write the indices of these elements in a vector BCE to the index which corresponds to them. This loop is based, as previously on the progressive unstacking of the list L (operation 604), followed by the writing in the BCE vector of the corresponding data (operation 606). The vector BCE represents the indices of the rows of the matrix N in which we will write the constitutive branch equation of the component concerned.

In the case of inductive elements, the matrix N will receive the elements that define the inductance of each element concerned, and the matrix F will receive values associated with each element. This will be explained in Figure 10. Then, in an operation 608, the index i is incremented, and the list L is depilated again at 604. When the list L is empty, the operation 50 proceeds to the next loop, which is the processing of the components of the Cl list.

Here again, we begin in an operation 610 by unstacking the vector M. Then, in an operation 612, the index i is stacked in the vector KCL at the index corresponding to node 1 of the pair (k; 1) which has has been stripped of the vector M.

The vector KCL represents the line of N in which we will write Kirchhoff's law while running. In the case of capacitive elements, the matrix N will receive the capacity of each element, and the matrix F will receive values associated with each element. This will be explained with Figure 11.

Then, in an operation 614, the index i is incremented and the loop resumes at 610. When the list M is empty, the operation 50 passes to the next loop, which is the processing of the components of the list C2.

As we saw previously, the elements of the list C2 are the capacitive elements which are not described by a current law of Kirchhoff, but by their law of behavior.

This loop therefore comprises an unstacking operation 616, followed by an operation 618 of writing the index i in the vector BCE to the index of the component k, and an operation 620 of incrementation of the index i.

When the list C2 is empty, the operation 50 proceeds to the next loop, which is the processing of the components of the data Cir. which are stored in the N2 list.

Again, the loop starts with unstacking in an operation 622, followed by a write operation 624, the index i in the vector KCL at the index of the node k, and an operation 626 for incrementing the index i. When the list N2 is empty, the operation 50 passes to the next loop, which is the processing of the components of the list B.

Again, the loop begins with unstacking in an operation 628, followed by an operation 630 writing the index i in the vector BCE to the index of the component k, and an operation 632 for incrementing the index i.

When the list B is empty, the operation 50 passes to the next loop, which is the processing of the components of the list C.

It is a question here of entering the indices of the components corresponding to the Kirchhoff voltage laws for the capacitive elements. The loop therefore starts with an unstacking in an operation 634, followed by an operation 636 writing the index i in the vector KVL to the index of the component k, and an operation 638 for incrementing the index i.

Finally, operation 50 ends in 640.

In the end, we obtain a set of vectors that will, as we will see in Figures 7 to 13, allow to fill the matrices N, F, G, and H. These matrices correspond to a set of dynamic equations , and a set of input / output laws for non-regular elements, and an inclusion law set, to delimit the values of the non-regular element parameters.

All of these elements constitute the model 16 of the CIR circuit. Note that at this stage, this model includes only reference indices to the elements of the library 6 and no scalars, and that these indices will be used to fill the matrices thereafter.

FIG. 7 represents a schematic view of the operation of the simulation engine 8 during a simulation loop. In fact, the simulation engine 8 establishes the simulation of the CIR circuit. by establishing in successive time steps stable states of this circuit. The loop of the simulation engine 8 for a time step t goes into an operation 70 of the model Mod_Shl establishes the operation 50, and the last determined state St [t-1] for the circuit. The particular case of the first loop will be explained with Figure 15.

In an operation 75, the gear 10 calls a function Stamp_Discr () with the model Mod_Shl 16 and the last simulated state St [t-1] of the circuit.

The operation 75 is the one in which the matrices N, F, G, and H are filled with scalar values.

Thus, from the Mod_Shl model, the function Stamp_Discr () comes to fill the matrix by realizing a temporal discretization of the differential equations that it contains, so that, for example, Uk 'becomes Uk [t] -Uk [t-1 ], the instants t-1 and t being very close. In this matrix, the values at time t-1 are taken from the state St [M].

This operation is also slightly complicated by the fact that the matrix N is simultaneously reversed, as appears with FIG.

Indeed, as we saw above, we are here based on a system of Nx '= f (x, z, t) type, and we need to invert N to recover the intensities in the capacitive branches of the vector Cl. It is therefore easier to perform the inversion and discretization in a single step.

In fact, at first, the matrix N is filled, as well as the matrices F, G, and H in part. Then, the matrix N is inverted and the matrices F, G and H completed. These operations are shown in FIG.

Then, the matrices thus obtained are discretized. The discretization that is carried out here is done according to the method of Moreau, which is described in the article "Numerical Methods for Nonsmooth Dynamical Systems" of Acary and Brogliato published by Springer Verlag. Figure 8 shows the filling operations of the matrices before discretization. This filling is done in two loops. In a first loop, the representation of the circuit Cir. is successively depilated in an operation 800. Then, for each component, a function Stamp () is called with the index k of the component concerned.

The Stamp () function is adapted to each type of component. Figures 9 to 12 show examples for a resistor, inductance, capacitance and diode respectively.

Figure 9 shows the StampO function in the case of a resistor. It therefore starts from an operation 900 with the resistance R and the index k of this component. At the index k correspond two indices of node 11 and 12 which are the limits of the resistance k.

In an operation 902, the value 1 / R is added to the coordinate index element (KCL (II); 11) of the matrix F.

In an operation 904, the value -1 / R is added in the coordinate index element (KCL (II); 12) of the matrix F.

In an operation 906, the value -1 / R is added to the coordinate index element (KCL (12); 11) of the matrix F.

In an operation 908, the value 1 / R is added to the coordinate index element (KCL (12); 12) of the matrix F.

Then, the function ends in 910. These operations reflect the writing of the intensity that traverses the resistance k seen from the nodes 11 and 12 respectively.

Figure 10 shows the StampO function in the case of an inductor. It therefore starts from an operation 1000 with the inductance L, the index k of this component and the index xk of the intensity of this inductance in the vector x. At the index k correspond two indices of node 11 and 12 which are the terminals of the inductance k.

In an operation 1002, the value L is added to the coordinate index element (BCE (k); xk) of the matrix N. This amounts to writing the voltage U = L * I 'for the inductance k.

In an operation 1004, the value 1 is added to the coordinate index element (BCE (k); 11) of the matrix F.

In an operation 1006, the value -1 is added to the coordinate index element (BCE (k); 12) of the matrix F.

In an operation 1008, the value 1 is added to the coordinate index element (KCL (11); xk) of the matrix F.

In an operation 1010, the value -1 is added to the coordinate index element (KCL (12); xk) of the matrix F.

Then, the function ends in 1012. These operations reflect the writing of the intensity which passes through the inductance k seen from the nodes 11 and 12 respectively.

Figure 11 shows the StampO function in the case of a capacity. It therefore starts from an operation 1100 with the capacitance C, the index k of this component, the index xk of the voltage of this capacitance in the vector x, and the index zk of the intensity of this capacitance in the vector zk (when k belongs to C2). At the index k correspond two indices of node 11 and 12 which are the limits of the capacity k.

This function comprises three first operations 1102, 1104 and 1106 for writing the Kirchhoff voltage law, and three tests as a function of the presence of the capacitance in the vectors N1, N2 and C2. In operation 1102, the value -1 is added to the coordinate index element (KVL (k); xk) of the matrix F.

In operation 1104, the value 1 is added to the coordinate index element (KVL (k); 11) of the matrix F.

In operation 1106, the value -1 is added to the coordinate index element (KVL (k); 12) of the matrix F.

Then, in the first test, an operation 1108 makes it possible to check whether the node 11 is in the list N1.

If this is the case, in an operation 1110, it is checked whether k is in the list C2. If this is the case, the value C is added to the coordinate index element (KCL (II); xk) of the matrix N in an operation 1112. Otherwise, the value -1 is added to the element coordinate index (KVL (k); 12) of the matrix F in an operation 1114.

These operations amount to writing the Kirchhoff intensity law or the voltage law of the capacitance as a function of its Cl or C2 membership.

Then, or when the test of the operation 1108 is negative, a second test is performed in an operation 1116 to check if the node 12 is in the list Nl.

The operations 1118 to 1122 are identical to the operations 1110 to 1114 but with the node 12.

Finally, the last test of the operation 1124 provides for writing the branch equations of the capacity with the operations 1126 and 1128 if the capacity belongs to the list C2.

Finally, the function ends in an operation 1130 (or directly if the capacity did not belong to the list C2). Figure 12 shows the StampO function in the case of a diode. It therefore starts from an operation 1200 with the index k of this component, and the index zk of the intensity of this diode in the vector Ins. At the index k correspond two indexes of node 11 and 12 which are the terminals of the diode k. On the other hand, in the following, the value x represents the size of the vector x, and the value z represents the size of the vector z.

In an operation 1202, the value 1 is added to the coordinate index element (KCL (II); x + zk) of the matrix F.

In an operation 1204, the value -1 is added to the coordinate index element (KCL (12); x + zk) of the matrix F.

In an operation 1206, the value -1 is added to the coordinate index element (Ins (k); x + zk) of the matrix H. It will be noted that Ins (k) has been established with FIG.

In an operation 1208, the value 1 is added to the coordinate index element (KCL (II); x + z + Lns (k)) of the matrix H. It will be noted that Lns (k) has been established with Figure 4.

In an operation 1210, the value -1 is added to the coordinate index element (Lns (k); x + 11) of the matrix G.

In an operation 1212, the value 1 is added to the coordinate index element (Lns (k); x + 12) of the matrix F.

Note that here, the StampO function ^is presented as a single function. However, in the context of an implementation in object language, each component of the circuit can be treated as an instance of a class of components.

The StampO function is then a call to the method of each particular instance, the StampO variant method for each component class. Once the circuit has been fully stripped, the N matrix is complete and can be inverted. All elements of this matrix that have not been filled are initialized to 0.

The inversion of the matrix N is carried out in an operation 804. Thus, once the matrix N is inverted, one can obtain the system x '= N ^Λ -l * f (x, z, t).

This system is then exploited in a second loop. In this loop, the list of capacitive elements C is depilated in an operation 806, and in an operation 808 a function Stamp_inv () is called with k as an argument. This function is described in Figure 13.

As can be seen in this figure, in a first operation 1300 of a test to check if KCL (II) is greater than the dimension of the vector x.

If this is the case, then in an operation 1302, a function Fill () is called with KCL (Il) as argument. The function Fill () has the function of seeking the expression of the missing intensity corresponding to KCL (II) by means of the inverted matrix Inv_N, and of storing the result in the matrix F in the line KCL (II).

Otherwise a second test checks in an operation 1304 if KCL (12) is greater than the dimension of the vector x.

If this is the case, then the function Fill () is called in an operation 1306 with KCL (12) as an argument, and the result is stored in the KCL line (12) of the matrix F.

Finally after the operation 1302, 1306 or 1304 if the two tests are negative, the function ends in 1308.

Then, the matrices N, F, G and H are discretized as described above, and the function Stamp_Discr () returns a discretized model Discr_Mod which is used in a step 80 by the mechanism 12 to determine the next state of the circuit St [t ] by means of an Nxt () function. Figure 14 shows an exemplary implementation of the Nxt () function. The Nxt () function is a mechanism for solving the system described by the Discr_Mod model, and the input / output and inclusion (or domain delineation) equations.

In the example described here, this mechanism comprises two principles for finding a solution to this system:

a principle of research by linearization of the system, and

- the use of direct nonlinear methods (generalized Newton type).

Since linearization is the fastest search, it is this principle that is first implemented. For this, two loops are nested.

The first loop goes linear Discr_Mod discretized model, solve the linearized discretized model system, and repeat this operation until reaching a stable state.

The second loop changes the starting point of the first loop if the solution obtained is not suitable.

The first loop thus goes into an operation 1400 of the reception of the discretized model Disc_Mod, of the initialization of a time step / index sa 1, and of the definition of the state St [t-1] as a temporary state of the circuit St_tmp (s) where s is 0 (zero).

In an operation 1402, the model Discr_Mod () is linearized to take into account the temporary state St_tmp (t-1) by means of a function Lin (). The Lin () function makes it possible to simplify the expressions of all the non-linear elements in the Discr_Mod model.

The result is stored in a Discr_Mod_l (s) temporary linearized discrete model. At this point, we have a system of linear equations and a set of domain delimitation laws, as everything has been linearized. Then, in an operation 1404, the mechanism 12 calls a Solve () function that solves this system of equations, by means of pivoting methods for example, or projection / splitting techniques.

Finally, in an operation 1406, the state St_tmp (s) thus calculated is compared to the temporary state from which it is derived St_tmp (s-1), to see if the system is stabilized.

If this is not the case, then the index s is incremented in an operation 1408 and the first loop resumes in 1402, this time with the temporary state St_tmp (s) which has just been calculated as the starting point.

If this is the case, then a test in an operation 1410 checks whether the state thus determined satisfies the input / output equations, the non-linearized Discr_Mod system, and the domain boundaries for non-regular elements.

If so, then St_tmp (s) is defined as the new simulated state of the circuit St [t], and returned as a result in a terminal operation 1412.

If this is not the case, a function Shuf () is called in an operation 1414 to restart the first loop with a different starting point, from the reference state St [M].

If this has already been done several times without obtaining a satisfactory solution for St_tmp (s), then the second loop is started with an operation 1416.

Otherwise, the first loop resumes at 1402 with s reset to 1 (one), and the new state St_tpm (0) determined by the function Shuf ().

Operation 1416 calls an Enum () function. The Enum () function is less efficient in terms of computation time than the linearization loop, but it implements so-called optimization methods, which will methodically explore the space of parameters defined by the domain boundaries, and gradually calculate a new state St [t] that optimally matches the solution of the system.

Such optimization methods include, but are not limited to, cutting projection methods, Newton's "semi-smooth" methods, or interior-based methods.

Once the function Enum () has determined the new state St [t], the operation 80 then ends in 1412.

Figure 15 shows the particular case of the first state of the circuit. Indeed, for this state, there is no previous state.

This operation therefore starts in 1500 with a test that checks whether the state St [O] derived from the data Init_Par is complete. If this is the case, then no need for calculation, and the operation ends in 1502, the simulation can start from this state.

Otherwise, in an operation 1504, the matrix N is scalarly filled in the manner of the operation 75, by means of a function Stamp_0 (). The function Stamp_0 () uses the model 16 Mod_Shl and the data Init_Par, to fill the system with the starting data, and without carrying out discretization, but by inverting the matrix N as described above.

Then, in an operation 1506, the Solve () function described with Fig. 14 is called on the resulting Disc_Mod model to compute the state St [O], and the operation ends at 1502.

Figure 16 shows the Stamp () function that is applied for a MOSFET transistor.

The Applicant has established that a transistor such as transistor 166 can be modeled according to the set of equations of formula (30) of Annex A. It starts from an operation 1600 with the index zk of the intensity of this component in the vector z, and the indices gk, sk and dk which are respectively the indices of the node of the grid, the source and the drain of the transistor. On the other hand, in the following, the value x represents the size of the vector x, and the value z represents the size of the vector z.

In an operation 1602, the value 1 is added to the coordinate index element (KCL (dk); x + zk) of the matrix F.

In an operation 1604, the value -1 is added to the coordinate index element (KCL (sk); x + zk) of the matrix F.

In an operation 1606, the value -1 is added to the coordinate index element (Ins (k), x + zk) of the matrix H.

Then in operations 1608 to 1632, Nbzh, NbIh, Nbzg and NbIg vectors are filled with values from formula (30). These vectors represent derivatives of the G and H vectors that are used by the solver to solve the system.

In the operation 1608, a value corresponding to the z-derivative of the IDS value of the formula (30) is added to the coordinate index element (Ins (k); gk) of the matrix Nbzh.

In the operation 1610, the z-derivative of the first member of the IDS value of the formula (30) is removed from the coordinate index element (Ins (k); sk) of the matrix Nbzh.

In the operation 1612, the z derivative of the second member of the IDS value of the formula (30) is removed from the coordinate index element (Ins (k); sk) of the matrix Nbzh.

In the operation 1614, the value -K / 2 * K (Vg-Vd-Vt) ² is added in the coordinate index element (Ins (k), Lns (k) +1) of the matrix NbIh . In the operation 1616, the value K / 2 * K (Vg-Vs-Vt) ² is added in the coordinate index element (Ins (k), Lns (k) +3) of the matrix NbIh.

In the operation 1618, the value -1 is added to the coordinate index element (Lns (k) + 1, gk) of the matrix Nbzg.

In the operation 1620, the value -1 is added to the coordinate index element (Lns (k) +3, gk) of the matrix Nbzg.

In operation 1622, the value 1 is added to the coordinate index element (Lns (k) +1, dk) of the matrix Nbzg.

In the operation 1624, the value 1 is added to the coordinate index element (Lns (k) +3, sk) of the matrix Nbzg.

In the operation 1626, the value 1 is added to the coordinate index element (Lns (k) +1, Lns (k)) of the matrix NbIg.

In the operation 1628, the value -1 is added to the coordinate index element (Lns (k) +1, Lns (k)) of the matrix NbIg.

In the operation 1630, the value 1 is added to the coordinate index element (Lns (k) +3, Lns (k) +2) of the matrix NbIg.

In the operation 1632, the value -1 is added to the coordinate index element (Lns (k) +2, Lns (k) +3) of the matrix NbIg.

Finally, the function ends in an operation 1634.

FIG. 17 represents an example of a circuit that can be modeled thanks to the device of the invention. This circuit comprises a voltage source 160, a capacitance bridge 162, a resistor 164, a MOSFET transistor 166, an inductor 168 and a resistor 170.

The capacitance bridge 162 is connected on the one hand to the voltage source 160 to a node 172, and on the other hand to the first resistor 164 and the gate of the transistor 166 by a node 174.

The capacitance bridge 162 comprises four capacitors C1, C2, C3, and C4, the capacitors C1 and C2 on the one hand and C3 and C4 on the other hand being arranged in series between the nodes 172 and 174.

Inductance 168 is connected on the one hand to the drain of transistor 166 and on the other hand to resistor 170.

The voltage source 160, the resistor 162, the source of the transistor 166 and the resistor 170 are connected to the earth.

By applying the operations described in FIGS. 4 and 5, we obtain first of all a vector Ins according to formula (32) of Annex A with Ins≈l and Lns = 4, and vectors x and z respectively according to formulas (34) and (36).

The covering tree is (2,1) (2,4) (1,3), and the vectors M, Cl, C2, N1 and N2 obtained are according to formulas (38) to (46).

Next, applying the operations of FIG. 6 gives the ECB vectors according to formula (48), KCL according to formula (50), and KVL according to formula (52).

The application of the operations of FIGS. 7 and 8 gives the matrices N according to formula (54) and F according to formula (56). These operations applied to transistor (166) give the vectors according to formulas (58) to (64).

Finally, the inversion of the matrix N makes it possible to recover the equation of the intensity in the node 3, according to the formula (66), and the application of the operation 808 gives the filling according to the equation (68) .

The vectors F, N, Nbzh, NbIh, Nbzg and NbIg thus obtained will make it possible to simulate the circuit, and will serve as model data for the reducer 10 and the solver 12.

The invention described herein is therefore extremely advantageous for the simulation of many electrical circuits combining analog and digital elements. It finds a very particular application in switched circuits.

This is achieved in particular by the introduction of a new framework for analyzing circuits and their components which makes it possible to accurately take into account non-regular elements.

For this purpose, it will be noted that domain boundaries that involve mathematical elements that are called inclusion rules.

These elements make it possible, with the input / output equations, to model very faithfully most of the components known to date.

For more information on inclusion rules and how they work, the Applicant recommends consulting RT ROCKAFELLAR & JB WETS Variational Analysis. Springer Verlag, 1998, or "Finite-dimensional Variational Inequalities and Complementarity Problems" by F. FACCHINEI & JS PANG., Volume I & II of Springer Series in Operations Research, Springer Verlag, 2003. Although the invention has proved to be particularly effective in its application to switched circuits, it is fully adapted to the simulation of other types of circuit such as conventional analog circuits. In this context it represents a significant improvement over the known simulators.

The invention is not limited to a theoretical framework. The implementation of this framework posed many problems that determined the implementation described above.

It is understood, however, that many alternative embodiments of the elements described herein may be contemplated without departing from the scope of the following claims.

In addition, the invention also relates to an electrical circuit simulation method comprising:

receiving description data of an electronic circuit comprising a representation of this circuit by its components and their interconnections, as well as initial state data of this circuit,

obtaining characteristics of the circuit components, each with characteristics for simulating its behavior, at least some of which are associated with a dynamic equation, and / or an input / output equation with a domain delimitation expression defining the parameters possible status for the component concerned,

calculating a model of a circuit, from said representation of the circuit and the characteristics of its components, in the form of a triplet of sets of equations which respectively relate to the dynamic equations, the input / output equations and the domain boundaries of the components of this circuit,

repetitively calculating a posterior state of a circuit, from its model and from an earlier state of the circuit, until it fulfills a condition relating to the number of executions or the last calculated posterior state.

Claims

claims An electric circuit simulator comprising: a library (6), comprising circuit components, each with characteristics for simulating its behavior, at least some of which are associated with a dynamic equation, and / or an input / output equation with a delimitation expression of domain defining the possible state parameters for the component concerned, a constructor (4), arranged to calculate a model (16) of a circuit, from a representation of this circuit (14) by its components and their interconnections, in the form of a game triplet; equations that relate respectively to the dynamic equations, the input / output equations and the domain boundaries of the components of this circuit, a solver (12), arranged to calculate a posterior state of a circuit, from its model and from a previous state, and a simulation engine (8), arranged to call the constructor (4) with the representation of a circuit, and to execute the solver (12) with the resulting model from an initial state of the circuit, and to repeat this execution from the last calculated later state until fulfilling a condition relating to the number of executions or the last calculated posterior state. 2. Simulator according to claim 1, wherein the simulation engine (8) comprises a gearbox (10), arranged to calculate a temporally discretized form of the set of dynamic equations of a given model, as well as a mechanism that explores the set of domain boundaries, to define a state that satisfies the set of input / output equations and the set of discretized equations. 3. Simulator according to claim 2, wherein the reducer operates according to Moreau's method for calculating said temporally discretized form. 4. Simulator according to claim 2 or 3, wherein the reducer performs a linearization of said temporally discretized form. 5. Simulator according to one of claims 2 to 4, wherein the mechanism uses pivoting methods, or projection techniques / cutting.