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WO2010126698A2 - Modélisation d'une extraction cd en microscopie électronique à balayage (cd-sem) à dimension critique - Google Patents

Modélisation d'une extraction cd en microscopie électronique à balayage (cd-sem) à dimension critique Download PDF

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Publication number
WO2010126698A2
WO2010126698A2 PCT/US2010/030502 US2010030502W WO2010126698A2 WO 2010126698 A2 WO2010126698 A2 WO 2010126698A2 US 2010030502 W US2010030502 W US 2010030502W WO 2010126698 A2 WO2010126698 A2 WO 2010126698A2
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Prior art keywords
simulated
values
cut
value
line
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WO2010126698A3 (fr
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Qiaolin Zhang
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Synopsys Inc
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Synopsys Inc
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G03F7/70441—Optical proximity correction [OPC]
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/705—Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness

Definitions

  • the present invention generally relates to semiconductor design and manufacturing. More specifically, the present invention relates to a method and a system for accurately modeling critical-dimension (CD) scanning-electron-microscopy (CD-SEM) CD extraction for use during photolithography process model calibration and post-Optical Proximity Correction (OPC) design layout verification.
  • CD-SEM critical-dimension scanning-electron-microscopy
  • OPC post-Optical Proximity Correction
  • Semiconductor manufacturing technologies typically include a number of processes which involve complex physical and chemical interactions. Since it is almost impossible to find exact formulae to predict the behavior of these complex interactions, developers typically use process models which are fit to empirical data to predict the behavior of these processes. A process model can be used in a number of applications during the design of a semiconductor chip.
  • lithography model a photolithography process model
  • OPC simulation engine uses the lithography model to iteratively evaluate and modify edge segments in the mask layout.
  • the post-OPC mask patterns are expected to produce physical patterns on the wafer that closely match design intent.
  • lithography model calibration To generate an accurate lithography model, a fitting process is often performed, which is referred to as "lithography model calibration.”
  • One objective of lithography model calibration is to minimize the difference between model-simulated critical dimension (CD) values (or “simulated CDs”) and corresponding measured wafer CD values (or “wafer CDs”) on test patterns.
  • CD model-simulated critical dimension
  • wafer CDs measured wafer CD values
  • the particular CD extraction technique used to extract the simulated CDs can have a significant effect on the accuracy of the simulated CDs, and therefore on the accuracy of the OPC model.
  • lithography model calibration tools use a single-cut- line-based CD extraction technique to extract the model-simulated CD values. In this technique, only a single cut-line is placed at a precise location where the CD value is to be extracted. For example, FIG.
  • FIG. 2 illustrates a single-cut-line-based CD extraction technique performed on a simulated wafer pattern 200.
  • the blue geometries represent a part of design layout and the red contours represent simulated wafer pattern 200 of the layout through a lithography process.
  • the simulated CDs are extracted from simulated wafer pattern 200. More specifically, when a CD value needs to be extracted from a target feature within simulated wafer pattern 200, coordinate information is provided for the extraction location.
  • the single-cut-line -based CD extraction technique then places a single cut-line at the precise location on the target feature based on the coordinate information.
  • a single cut-line 206 is placed right between the very tips of the line-ends 202 and 204.
  • the extracted CD value using this technique is the shortest distance between simulated line-ends 202 and 204.
  • single cut-line 210 is placed right at a location on line feature 208 according to the provided coordinate information.
  • One embodiment of the present invention relates to a process that models critical-dimension (CD) scanning-electron-microscopy (CD-SEM) CD extraction during photolithography process model calibration.
  • the process receives measured CD values which were obtained using a CD-SEM extraction process, wherein the CD-SEM extraction process determines a measured CD value for a feature by measuring multiple CD values of the feature along multiple electron beam scans on the wafer surface.
  • the process determines simulated CD values, wherein a simulated CD value is determined based at least on a set of CD extraction cut- lines placed on the test pattern layout.
  • the process fits a parameter that models an aspect of the photolithography process based at least on both the measured CD values and the simulated CD values.
  • the process determines the simulated CD value by first placing a measurement window centered at the target feature. The process then places the set of CD extraction cut- lines within the measurement window based at least on a placement spacing parameter, wherein the placement spacing parameter models a spacing between the multiple electron beam scans in the CD-SEM extraction process. Next, the process extracts a set of single-cut- line CD values for the set of CD extraction cut-lines placed on the test pattern layout. The process next determines the simulated CD value using the set of single- cut-line CD values.
  • the fitting parameter includes the placement spacing parameter.
  • the process prior to placing the measurement window, obtains the simulated pattern by convolving the feature with a photolithography process model.
  • the process determines the simulated CD value using the set of single-cut-line CD values by computing an average of the set of single-cut- line CD values.
  • the process fits the parameter by, iteratively: updating the simulated CD values based at least on an updated photolithography process model, and updating the parameter's value based at least on a difference between the updated simulated CD values and the measured CD values.
  • the process fits the parameter by minimizing a difference between the simulated CD values and the measured CD values.
  • One embodiment of the present invention relates to another process that models critical-dimension (CD) scanning-electron-microscopy (CD-SEM) extraction during photolithography process model calibration.
  • the process receives a simulated CD value for a feature, wherein the simulated CD value is extracted from a simulated pattern associated with the feature using a single cut-line placed on the desired feature on a test pattern layout.
  • the process also receives raw CD-SEM measurement data for the feature, wherein the raw CD-SEM measurement data includes multiple measured CD values extracted for the feature using multiple electron beam scans distributed within a measurement window centered at the feature.
  • the process uses the multiple measured CD values to determine a predicted CD value which predicts the simulated CD value.
  • the process calibrates the photolithography process model based at least on both the predicted CD value and the simulated CD value.
  • the process determines the predicted CD value by determining a CD value along a cut-line on the feature on the wafer, wherein the location of the cut- line matches the location of the single cut-line used to extract the simulated CD value.
  • the process determines the CD value along the cut- line whose location matches the location of the single cut-line on the test pattern layout by performing a curve fitting on the multiple measured CD values to determine a local minimum or maximum value.
  • One embodiment of the present invention relates to a process that models critical-dimension (CD) scanning-electron-microscopy (CD-SEM) extraction during post- optical-proximity-correction (post-OPC) design layout verification.
  • the process receives measured CD values which were obtained using a CD-SEM extraction process from wafer, wherein the CD-SEM extraction process determines a measured CD value for a feature by measuring multiple CD values of the feature along multiple electron beam scans on the wafer surface.
  • the process determines simulated CD values, wherein a simulated CD value is determined based at least on a set of CD extraction cut- lines placed on the target feature on test patter layout.
  • the process verifies the quality of design layout corrected by OPC by comparing the measured CD values with the simulated CD values.
  • this process determines the simulated CD value by first placing a measurement window centered at the feature. The process then places the set of CD extraction cut-lines within the measurement window based at least on a placement spacing parameter, wherein the placement spacing parameter models a spacing between the multiple electron beam scans on the wafer surface in the CD-SEM extraction process. Next, the process extracts a set of single-cut-line CD values for the set of CD extraction cut-lines on the test patter layout. The process next determines the simulated CD value using the set of single-cut-line CD values.
  • One embodiment of the present invention relates to another process that models critical-dimension (CD) scanning-electron-microscopy (CD-SEM) extraction during post-optical-proximity-correction (post-OPC) design layout verification.
  • CD-SEM critical-dimension scanning-electron-microscopy
  • post-OPC post-optical-proximity-correction
  • the process receives a simulated CD value for a feature, wherein the simulated CD value is extracted from the target feature using a single cut-line placed on the test pattern layout.
  • the process also receives raw CD-SEM measurement data for the feature, wherein the raw CD- SEM measurement data includes multiple measured CD values extracted for the feature using multiple electron beam scans.
  • the process uses the multiple measured CD values to determine a predicted CD value which predicts the simulated CD value.
  • the process verifies the quality of design layout corrected by OPC by comparing the predicted CD value with the simulated CD value.
  • the process determines the predicted CD value by determining a CD value along a cut-line on the target feature, wherein the location of the cut- line matches the location of the single cut- line used to extract the simulated CD value.
  • the process determines the CD value along the cut- line whose location matches the location of the single cut- line by performing a curve fitting on the multiple measured CD values to determine a local minimum or maximum value.
  • FIG. 1 illustrates various steps in the design and fabrication of an integrated circuit in accordance with an embodiment of the present invention.
  • FIG. 2 illustrates a single-cut-line-based CD extraction technique performed on a simulated wafer pattern.
  • FIG. 3 illustrates a detailed process flow diagram of resolution enhancement stage 128 in FIG.1.
  • FIG. 4 illustrates a process flow diagram of a conventional lithography model calibration process.
  • FIG. 5 A illustrates examples of the measurement- window-based extraction technique used by the CD-SEM extraction process to extract wafer CDs from the wafer patterns.
  • FIG. 5B illustrates examples of a measurement- window-based simulated CD extraction technique on target features in accordance with an embodiment of the present invention.
  • FIG. 6 presents a flowchart illustrating a process of performing a simulated CD extraction on a target feature in accordance with an embodiment of the present invention.
  • FIG. 7 illustrates a modified lithography model calibration process which uses the measurement- window-based simulated CD extraction in accordance with an embodiment of the present invention.
  • FIG. 8 illustrates a modified lithography model calibration process which uses a wafer CD derived from raw CD-SEM measurement data in accordance with an embodiment of the present invention.
  • FIG. 9 presents a flowchart illustrating a modified post-OPC verification process which uses the measurement-window-based simulated CD extraction in accordance with an embodiment of the present invention.
  • FIG. 10 presents a flowchart illustrating a modified post-OPC verification process which uses the modified wafer CD extraction technique in accordance with an embodiment of the present invention.
  • the data structures and code described in this detailed description are typically stored on a computer-readable storage medium, which may be any device or medium that can store code and/or data for use by a computer system.
  • the computer- readable storage medium includes, but is not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices such as disk drives, magnetic tape, CDs (compact discs), DVDs (digital versatile discs or digital video discs), or other media capable of storing computer-readable media now known or later developed.
  • the methods and processes described in the detailed description section can be embodied as code and/or data, which can be stored in a computer-readable storage medium as described above. When a computer system reads and executes the code and/or data stored on the computer-readable storage medium, the computer system performs the methods and processes embodied as data structures and code and stored within the computer- readable storage medium.
  • modules or apparatus may include, but are not limited to, an application-specific integrated circuit (ASIC) chip, a field-programmable gate array (FPGA), a dedicated or shared processor that executes a particular software module or a piece of code at a particular time, and/or other programmable-logic devices now known or later developed.
  • ASIC application-specific integrated circuit
  • FPGA field-programmable gate array
  • the hardware modules or apparatus When activated, they perform the methods and processes included within them.
  • FIG. 1 illustrates various steps in the design and fabrication of an integrated circuit.
  • the process starts with the generation of a product idea (stage 100), which is realized using an Electronic Design Automation (EDA) software design process (stage 110).
  • EDA Electronic Design Automation
  • stage 110 When the design is finalized, it can be taped-out (stage 140).
  • stage 150 the fabrication process is consummated (stage 150) and packaging and assembly processes (stage 160) are performed which ultimately result in finished chips (stage 170).
  • stage 110 The EDA software design process (stage 110), in turn, comprises stages 112-130, which are described below. Note that this design flow description is for illustration purposes only. This description is not meant to limit the present invention. For example, an actual integrated circuit design may require a designer to perform the design stages in a different sequence than the sequence described herein. The following discussion provides further details of the stages in the design process.
  • System design stage 112: The designers describe the functionality to implement. They can also perform what-if planning to refine the functionality and to check costs. Hardware-software architecture partitioning can occur at this stage. Exemplary EDA software products from SYNOPSYS, INC. that can be used at this stage include MODEL ARCHITECT®, SABER®, SYSTEM STUDIO®, and DESIGNWARE® products.
  • stage 114 Logic design and functional verification: At this stage, the VHDL or Verilog code for modules in the system is written and the design is checked for functional accuracy. More specifically, the design is checked to ensure that it produces the correct outputs.
  • Exemplary EDA software products from SYNOPSYS, INC. that can be used at this stage include VCS®, VERA®, DESIGNWARE®, MAGELLAN®, FORMALITY®, ESP® and LED A® products.
  • Synthesis and design (stage 116): Here, the VHDL/Verilog is translated to a netlist.
  • the netlist can be optimized for the target technology. Additionally, tests can be designed and implemented to check the finished chips.
  • Exemplary EDA software products from SYNOPSYS, INC. that can be used at this stage include DESIGN COMPILER®, PHYSICAL COMPILER®, TEST COMPILER®, POWER COMPILER®, FPGA COMPILER®, TETRAMAX®, and DESIGNWARE® products.
  • Netlist verification (stage 118): At this stage, the netlist is checked for compliance with timing constraints and for correspondence with the VHDL/Verilog source code.
  • Exemplary EDA software products from SYNOPSYS, INC. that can be used at this stage include FORMALITY®, PRIMETIME®, and VCS® products.
  • Design planning (stage 120): Here, an overall floor plan for the chip is constructed and analyzed for timing and top-level routing.
  • Exemplary EDA software products from SYNOPSYS, INC. that can be used at this stage include ASTRO® and IC COMPILER® products.
  • stage 122 The placement (positioning of circuit elements) and routing (connection of the same) occurs at this stage.
  • Exemplary EDA software products from SYNOPSYS, INC. that can be used at this stage include the ASTRO® and IC COMPILER® products.
  • stage 124 At this stage, the circuit function is verified at a transistor level; this, in turn, permits what-if refinement.
  • Exemplary EDA software products from SYNOPSYS, INC. that can be used at this stage include ASTRORAIL®, PRIMERAIL®, PRIMETIME®, HSPICE®, HSIM®, NANOTIME®, NANOSIM® and STAR-RCXT® products.
  • stage 126 Physical verification: In this stage, the design is checked to ensure correctness for manufacturing, electrical issues, lithographic issues, and circuitry.
  • Exemplary EDA software products from SYNOPSYS, INC. that can be used at this stage include the HERCULES® product.
  • Resolution enhancement stage 128): This stage involves geometric manipulations of the layout to improve manufacturability of the design.
  • Exemplary EDA software products from SYNOPSYS, INC. that can be used at this stage include PROTEUS®, PROTEUS®AF, and PSMGED® products.
  • Mask data preparation stage 130: This stage provides the tape-out data for production of masks to produce finished chips.
  • Exemplary EDA software products from SYNOPSYS, INC. that can be used at this stage include the CATS® family of products.
  • Embodiments of the present invention can be used during one or more of the above-described steps. Specifically, one embodiment of the present invention can be used during the resolution enhancement step 128. OPC Process Flow
  • FIG. 3 illustrates a detailed process flow diagram of resolution enhancement stage 128 in FIG.1.
  • a DRC-clean layout 302 is generated at physical verification stage 126 in FIG. 1.
  • DRC-clean layout 302 is the input to resolution enhancement stage 128, which further includes an optical proximity correction (OPC) process 304 and a post-OPC verification process 308.
  • OPC process 304 can further include a number of mask manipulation tools, which can include, but are not limited to, line biasing, assist feature placement, and phase-shifting mask.
  • the output of OPC process 304 is a referred to as a "post-OPC" layout 306 because it is an OPC-corrected, DRC-clean layout.
  • post-OPC layout 306 is re-examined during post-OPC verification process 308 to ensure that post-OPC layout 306 meets the lithography constraints. If the post-OPC verification process is successful, post-OPC layout 308 is then ready for tape-out. However, if the post-OPC verification fails, tape-out is aborted and remedial actions have to be taken.
  • lithography model 310 includes a set of mathematical models that describe the photolithography process. In some embodiments, these mathematical models are represented by a set of predetermined kernel functions. These kernel functions are typically calibrated using both the measured wafer CDs and simulated CDs from test patterns, as mentioned previously. We describe the process of lithography model calibration in more detail below.
  • FIG. 4 illustrates a process flow diagram of a conventional lithography model calibration process 400.
  • lithography model calibration process 400 starts by receiving a set of test patterns 402.
  • these test patterns 402 are configured to represent various design patterns permitted by design rules in actual layouts.
  • Test patterns 402 are then printed onto one or more wafers through a physical photolithograph system (step 404), which transfers test patterns 402 into wafer patterns 406.
  • a critical-dimension scanning-electron-microscopy (CD-SEM) measurement process is used to extract wafer CDs from wafer patterns 406 using a measurement- window-based extraction technique (step 408).
  • CD-SEM critical-dimension scanning-electron-microscopy
  • the CD-SEM measurement tool extracts wafer CDs at a set of designated locations within test patterns 402 based on provided coordinate information. We refer to a layout feature in a test pattern at a given CD extraction location as a "target feature" hereinafter. For each target feature where a single CD value is to be extracted, the CD-SEM measurement tool then places a measurement window around the target feature. Within this measurement window, the CD-SEM measurement tool then performs multiple electron beam scans along a specified direction, and subsequently measures a CD value for each scan within the measurement window.
  • FIG. 5 A illustrates examples of the measurement- window-based measurement technique used by the CD-SEM measurement tool to measure wafer CDs from wafer patterns 406. More specifically, FIG. 5A illustrates two types of target features associated with two wafer CDs.
  • the first target feature in FIG. 5A is a line feature 502 (shown on the left) wherein a CD value representing the width of line feature 502 is to be extracted.
  • a measurement window 504 is placed around the middle section of line feature 502 by the CD-SEM measurement tool and a set of parallel scan lines 506 are shown within window 504 to represent multiple CD-SEM electron beam scans.
  • each extracted wafer CD value measures the distance between the two intersection points between a corresponding scan line and the boundary of line feature 502.
  • the set of scan lines 506 are equally spaced with a placement [0057]
  • the second target feature in FIG. 5A is a double-line-end feature 508 (shown on the right) which comprises line-end 510, line-end 512, and an end-to-end distance 514 between the two line-ends, wherein a CD value representing end-to-end distance 514 is to be extracted.
  • the red outlines in FIG. 5 A represent the shape of line-ends 510 and 512 in the original layout
  • the green curvatures represent the shape of the line- ends when they are printed on the wafer.
  • a measurement window 516 is placed around line-end feature 508 by the CD-SEM measurement tool to enclose portions of the two line-ends and the gap between them.
  • a set of parallel scan lines 518 are shown within window 516 to represent the multiple CD-SEM electron beam scans.
  • each extracted wafer CD value measures the distance between two intersection points between a corresponding scan lines and the boundaries of line-ends 510 and 512.
  • the set of scan lines 518 may not include a measurement placed precisely at the shortest distance between the two line-ends.
  • the set of scan lines 518 are equally spaced with a placement distance of ⁇ 2 . Note that ⁇ i and ⁇ 2 have different values in these two examples.
  • line feature 502 is referred to as a one-dimensional (ID) feature
  • the double line-end feature 508 is referred to as a two-dimensional (2D) feature.
  • the CD-SEM measurement tool After extracting multiple wafer CDs from a measurement window associated with each target feature, the CD-SEM measurement tool computes the average of the set of wafer CDs and reports the average CD as the extracted wafer CD for the target feature.
  • the wafer-CD-extraction step 408 output a set of wafer CDs 410, wherein each wafer CD 410 represents an averaged CD obtained based on the measurement- window-based technique. Note that this measurement-window-based CD extraction technique is often used to compensate for the effect of stage misalignment in CD-SEM measurements, wherein using a single CD-SEM scan can result in large errors from measurement to measurement even on the same feature. Hence, when multiple scans are used at each target feature, the stage misalignment effect is minimized and the measurements generate consistent results from measurement to measurement.
  • lithography model calibration process 400 also obtains a corresponding simulated CD. More specifically, based on the coordinate information, target features at the precise locations of CD extractions are convolved with a lithography model 422 being calibrated to obtain simulated wafer pattern boundary points 414 at the extraction locations (step 412).
  • lithography model 422 can be an initial lithography model at the beginning of the model calibration process, or an intermediate lithography model during the course of the model calibration process.
  • lithography model 422 includes a set of model parameters which are being regressed during model calibration.
  • lithography model calibration process 400 uses a single-cut-line-based extraction technique (as described in FIG. 2) to obtain a simulated CD at each extraction location based on the simulated wafer pattern boundary points 414 (step 416). Hence, calibration process 400 obtains a set of simulated CDs 418 corresponding to the set of wafer CDs 410 within test patterns 402.
  • Both wafer CDs 410 and simulated CDs 418 are then used together in a model parameters regression (i.e., tuning and searching) process, to fit the set of model parameters (step 420), thereby updating lithography model 422.
  • the fitting process is performed to minimize the differences between the set of simulated CDs and the set of wafer CDs.
  • lithography model calibration process 400 is performed iteratively wherein lithography model 422 is iteratively updated.
  • this single-cut-line-based CD extraction technique is a simplified model which is inconsistent with the physical CD-SEM measurement tool in CD-SEM. Therefore, the regression analysis during model calibration process can drive one or more model parameters into having non-physical values to compensate for the discrepancies, thus degrading model stability and accuracy.
  • Embodiments of the present invention provide a measurement- window-based simulated CD extraction technique. Because this technique is a modification to the conventional single-cut-line-based simulated CD extraction technique described in FIG. 4, we refer to the measurement-window-based technique as "modified" simulated CD extraction, and to the simulated CD extracted using the technique as a "modified” simulated CD. Furthermore, we refer to a lithography model calibration process using this modified simulated CD extraction as a "modified” lithography model calibration process.
  • FIG. 5B illustrates examples of a measurement- window-based simulated CD extraction technique on target features in accordance with an embodiment of the present invention. More specifically, FIG. 5B illustrates the same two target features in FIG. 5A. As seen in FIG. 5B, a measurement window 522 is placed around the middle section of line feature 502 by the measurement- window-based simulated CD extraction tool and a set of parallel cut-lines 524 are shown within window 522 to represent multiple CD extraction locations. Note that in this example, the set of cut-lines 524 are equally spaced with a placement distance of ⁇ i , wherein ⁇ i can the same or different from ⁇ i in FIG. 5 A.
  • the second target feature in FIG. 5B is double-line-end feature 508 which comprises line-end 510, line-end 512, and an end-to-end distance 514 between the two line- ends, wherein a CD value representing end-to-end distance 514 is to be extracted.
  • a measurement window 526 is placed around line-end feature 508 by the measurement- window-based simulated CD extraction tool to enclose portions of the two line- ends and the gap between them.
  • a set of parallel cut- lines 528 are shown within window 526 to represent the multiple CD extraction locations. Note that the shortest cut-line 530 within cut-lines 528 may not be placed precisely at the shortest distance between the two line-ends.
  • the set of cut- lines 528 are equally spaced with a placement distance of ⁇ 2 , wherein ⁇ 2 can the same or different from ⁇ 2 in FIG. 5A.
  • FIG. 6 presents a flowchart illustrating a process of performing a measurement- window-based simulated CD extraction on a target feature in accordance with an embodiment of the present invention.
  • the system receives a target feature (step 602).
  • the system generates a measurement window which is centered around the target feature on the test pattern design layout based on the associated coordinate information (step 604).
  • the measurement window size is adaptively determined according to the target feature size and patterns surrounding the target feature. For example, to generate a window for line-end feature 508, the height of the window may be chosen to include the entire line-ends (i.e., to where the curvature change stops), while the width of the window may be chosen to include the widest part of the line ends. In other embodiments, a fixed window size is used. In another embodiment, the minimum window size is determined to allow placing at least two cut-lines.
  • the system places a set of equally spaced CD extraction cut- lines within the measurement window with a constant placement distance to mimic the CD-SEM measurement scheme (step 606).
  • the system can receive information on the placement distance used by CD-SEM to measure the wafer CD on the same target pattern, the same placement distance can be used for the simulated CD extraction. However, the system may not have this information available.
  • one embodiment of the present invention treats the placement distance as a model parameter.
  • the system can assign an initial value to the placement distance. This initial value can be a nominal value which is commonly used in CD-SEM. As is described in more detail below, this placement distance parameter is allowed to vary during the subsequent model calibration process.
  • the system assigns lower and upper limits to the placement distance parameter so that during calibration the parameter is not allowed to vary too far from the nominal value. Note that even if the system has the information of the actual placement distance used by CD-SEM, the system can still choose to designate the placement distance as a model parameter instead of fixing it to the actual value. [0069]
  • the system extracts a simulated CD for each of the multiple cut-lines (step 608).
  • the system computes a simulated CD for the target feature by averaging the set of simulated CDs (step 610). Note that this averaging operation mimics the averaging operation performed by CD-SEM to obtain the wafer CDs.
  • FIG. 6 describes the process of extracting a single simulated CD value on a given test pattern design layout
  • the process is used to extract simulated CDs from the set of test patterns involved in lithography model calibration.
  • CD-SEM may use different placement distances during the measurement.
  • CD-SEM uses two distinctive placement distances: a first one for line patterns, and a second for other patterns.
  • the modified model calibration process generates two corresponding fitting parameters, X 1 (for line features or ID features) and X 2 (for other features or 2D features).
  • FIG. 7 illustrates a modified lithography model calibration process 700 which uses the measurement-window-based simulated CD extraction in accordance with an embodiment of the present invention.
  • lithography model calibration process 700 is similar to lithography model calibration process 400 described in FIG. 4. However in modified process 700, a measurement-window-based simulated CD extraction step 702 as is described in FIG. 6, replaces the single-cut-line-based simulated CD extraction step 416. Moreover, modified (i.e., window-based) simulated CDs 704 replace single-cut-line-based simulated CDs 418 in FIG. 4. Similar to the calibration process in FIG. 4, modified simulated CDs 704 and wafer CDs 410 are then used together in a regression process to fit a set of lithography model parameters.
  • the set of lithography model parameters include the placement distance parameters, such as X 1 and X 2 . Note that during the regression, Xi and X 2 can be regressed together with other lithography model parameters. Alternatively, Xi and X 2 can be calibrated independently.
  • the modified model calibration process is performed in an iterative manner to minimize the differences between the set of modified simulated CDs 704 and the set of wafer CDs 410. During each iteration of the calibration, simulated wafer pattern boundary points 414 are recomputed and the modified simulated CDs 704 are subsequently extracted. Note that when the lithography model calibration is completed, the placement distance parameters should substantially match the actual placement distances used in the CD-SEM measurement. Modified (Single-Cut-Line-Based) Lithography Model Calibration
  • the conventional simulated CD extraction technique can precisely place a single cut-line at a desired location on a target feature.
  • this single cut-line can be precisely placed such that the extracted simulated CD is substantially equal to a minimum or maximum possible value.
  • a single cut-line for extraction of a simulated CD can be placed between the very tips of two line-ends 510 and 512.
  • CD-SEM performs multiple measurements for each target feature within a measurement window
  • scan line 520 which is associated with the smallest CD value among scan lines 518 typically does not coincide with the minimum CD (i.e., tip- to-tip) cut-line in feature 508.
  • a data analysis can be performed on the raw CD-SEM data to determine a minimum or maximum CD value.
  • the single-cut-line-based simulated CD value can be predicted based on the multiple measured CD values on the target feature.
  • FIG. 8 illustrates a modified lithography model calibration process 800 which uses a wafer CD derived from raw CD-SEM measurement data in accordance with an embodiment of the present invention.
  • lithography model calibration process 800 is similar to lithography model calibration process 400 described in FIG. 4.
  • model calibration process 800 uses the conventional single-cut-line CD extraction technique to obtain the simulated CDs 418.
  • CD-SEM is used to obtain multiple CD measurements for each target feature based on multiple electon beam scans within a measurement window.
  • the averaged CD of the multiple measured CDs is not used as wafer CDs 410 for lithography model calibration as in processes 400 and 700.
  • a derived single-cut-line CD 804 represents a minimum or maximum CD value within the corresponding measurement window.
  • a derived single-cut-line CD 804 is the tip-to-tip distance between two line-ends 510 and 512.
  • a curve-fitting technique can be used to derive a minimum or maximum CD value within the measurement window and then use the minimum or maximum CD as single-cut-line CD 804.
  • an image-processing technique can be used to derive the wafer CD exactly at the desired location as single-cut-line CD 804.
  • the derived minimum or maximum CD value is not necessarily the smallest or the largest CD value in the original CD-SEM measurement data.
  • CDs 410 to physically match how simulated CDs 418 are generated. Also, this technique does not add extra model fitting parameters (i.e., the placement distances) into the model fitting process, and hence simplifies the regression computation in model calibration. However, this technique relies on the availability of the raw CD-SEM measurement data.
  • model simulated CDs and measured wafer CDs on a given layout are separately generated. However, rather than using these CDs to drive a model calibration process, the differences between them are compared with verification criteria to determine the quality of the design layout after OPC.
  • FIG. 9 presents a flowchart illustrating a modified post-OPC verification process 900 which uses the measurement-window-based simulated CD extraction in accordance with an embodiment of the present invention.
  • the system receives a post-OPC design layout and a lithography model (step 902).
  • the lithography model has a set of fixed fitting parameters.
  • the set of fixed parameters include placement distance parameters X 1 and ⁇ 2 associated with the measurement- window-based simulated CD extraction technique described above.
  • the received lithography model has been calibrated at least partially based on calibration process 700.
  • the system also receives wafer CDs for the post-OPC design layout which are obtained using CD-SEM (step 904). Note that these wafer CDs are obtained conventionally as is described in FIG. 4.
  • step 906 The system then generates simulated wafer pattern boundary points at CD extraction locations by convolving target features of the post-OPC layout at these locations with the lithography model (step 906).
  • step 908 the system generates the simulated CDs from the simulated wafer pattern boundary points using a measurement- window-based CD extraction technique (step 908).
  • the detailed process of step 908 is substantially similar to the process described in FIG. 6, and hence is not repeated here.
  • step 908 modifies the conventional post-OPC verification process which generates the simulated CDs based on the single-cut-line extraction technique.
  • the system compares the simulated CDs and wafer CDs to determine the quality of the post-OPC design layout (step 910).
  • FIG. 10 presents a flowchart illustrating a modified post-OPC verification process 1000 which uses the modified wafer CD extraction technique in accordance with an embodiment of the present invention.
  • the system receives a post-OPC design layout and a lithography model (step 1002).
  • the lithography model has a set of fixed fitting parameters.
  • the set of fixed fitting parameters do not include the placement distance parameters associated with the measurement-window-based simulated CD extraction technique described above.
  • the lithography model can be calibrated using conventional model calibration techniques.
  • the system then prints the post-OPC design layout to obtain wafer patterns (step 1004) and subsequently extracts wafer CDs from the wafer patterns by using CD-SEM (step 1006). Note that this step is conventional as is described in FIG. 4.
  • the system derives single-cut-line minimum or maximum CDs based on the wafer CDs to predict simulated CDs which are extracted using the conventional single-cut-line-based CD extraction technique (step 1008). Note that step 1008 modifies the conventional post-OPC verification process which generates averaged wafer CDs based on the multiple electron beam scans in a measurement window.
  • the system also generates the simulated CDs using a conventional single-cut- line-based CD extraction technique (step 1010). Finally, the system compares the simulated CDs and the predicted simulated CDs from CD-SEM to determine the quality of the post- OPC design layout (step 1012).

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Abstract

Dans un mode de réalisation, l'invention concerne un procédé de modélisation d'extraction CD en microscopie électronique à balayage (CD-SEM) à dimension critique pendant l'étalonnage d'un procédé photolithographique. Pendant l'opération, le procédé reçoit des valeurs CD mesurées obtenues au moyen d'un procédé d'extraction CD-SEM qui détermine une valeur CD mesurée pour une caractéristique par mesure des multiples valeurs CD de la caractéristique conjointement avec des balayages de faisceaux d'électrons multiples. Le procédé détermine ensuite les valeurs CD simulées, une valeur CD simulée étant déterminée en fonction d'au moins un ensemble de lignes de coupe d'extraction CD uniformément réparties autour d'une caractéristique. Pendant l'étalonnage du procédé de photolithographie, ce dernier ajuste un paramètre qui modélise un aspect dudit procédé de photolithographie en fonction au moins des valeurs CD mesurées et des valeurs CD simulées.
PCT/US2010/030502 2009-04-30 2010-04-09 Modélisation d'une extraction cd en microscopie électronique à balayage (cd-sem) à dimension critique Ceased WO2010126698A2 (fr)

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