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WO2010118181A3 - Transistor partagé dans une cellule de mémoire vive magnétique à couple de transfert de spin (sttmram) - Google Patents

Transistor partagé dans une cellule de mémoire vive magnétique à couple de transfert de spin (sttmram) Download PDF

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Publication number
WO2010118181A3
WO2010118181A3 PCT/US2010/030305 US2010030305W WO2010118181A3 WO 2010118181 A3 WO2010118181 A3 WO 2010118181A3 US 2010030305 W US2010030305 W US 2010030305W WO 2010118181 A3 WO2010118181 A3 WO 2010118181A3
Authority
WO
WIPO (PCT)
Prior art keywords
mtj
port
transistor
sttmram
spin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2010/030305
Other languages
English (en)
Other versions
WO2010118181A2 (fr
Inventor
Ebrahim Abedirard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avalanche Technology Inc
Original Assignee
Yadav Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yadav Technology Inc filed Critical Yadav Technology Inc
Publication of WO2010118181A2 publication Critical patent/WO2010118181A2/fr
Publication of WO2010118181A3 publication Critical patent/WO2010118181A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/75—Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

L'invention concerne une cellule de mémoire vive magnétique à couple de transfert de spin (STTMRAM) comprenant une jonction de tunnel magnétique (MTJ) sélectionnée identifiée pour être programmée ; un premier transistor comportant un premier port, un second port et une grille, le premier port du premier transistor étant couplé à la MTJ sélectionnée ; une première MTJ voisine couplée à la MTJ sélectionnée par l'intermédiaire du second port du premier transistor ; un second transistor comportant un premier port, un second port et une grille ; le premier port du second transistor étant couplé à la MTJ sélectionnée ; une seconde MTJ voisine couplée à la MTJ sélectionnée par l'intermédiaire du second port du second transistor ; une première ligne de bits/source couplée à la seconde extrémité de la MTJ sélectionnée ; et une seconde ligne de bits/source couplée à la seconde extrémité de la première MTJ voisine et à la seconde extrémité de la seconde MTJ voisine.
PCT/US2010/030305 2009-04-08 2010-04-07 Transistor partagé dans une cellule de mémoire vive magnétique à couple de transfert de spin (sttmram) Ceased WO2010118181A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16785909P 2009-04-08 2009-04-08
US61/167,859 2009-04-08

Publications (2)

Publication Number Publication Date
WO2010118181A2 WO2010118181A2 (fr) 2010-10-14
WO2010118181A3 true WO2010118181A3 (fr) 2011-02-03

Family

ID=42934268

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/030305 Ceased WO2010118181A2 (fr) 2009-04-08 2010-04-07 Transistor partagé dans une cellule de mémoire vive magnétique à couple de transfert de spin (sttmram)

Country Status (2)

Country Link
US (2) US8238145B2 (fr)
WO (1) WO2010118181A2 (fr)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7978498B2 (en) * 2009-04-03 2011-07-12 Sandisk 3D, Llc Programming non-volatile storage element using current from other element
US8270199B2 (en) 2009-04-03 2012-09-18 Sandisk 3D Llc Cross point non-volatile memory cell
US8139391B2 (en) 2009-04-03 2012-03-20 Sandisk 3D Llc Multi-bit resistance-switching memory cell
US9728240B2 (en) * 2009-04-08 2017-08-08 Avalanche Technology, Inc. Pulse programming techniques for voltage-controlled magnetoresistive tunnel junction (MTJ)
US9646668B2 (en) * 2009-04-08 2017-05-09 Avalanche Technology, Inc. Spin-transfer torque magnetic random access memory (STTMRAM) with enhanced write current
US7969767B2 (en) * 2009-05-29 2011-06-28 Qualcomm Incorporated Spin transfer torque—magnetic tunnel junction device and method of operation
US20130073790A1 (en) * 2011-09-16 2013-03-21 Avalanche Technology, Inc. Magnetic random access memory with burst access
US8767446B2 (en) 2011-10-12 2014-07-01 International Business Machines Corporation Multi-bit spin-momentum-transfer magnetoresistence random access memory with single magnetic-tunnel-junction stack
US20130258750A1 (en) * 2012-03-30 2013-10-03 International Business Machines Corporation Dual-cell mtj structure with individual access and logical combination ability
US9728251B2 (en) 2013-04-24 2017-08-08 Micron Technology, Inc. Resistance variable memory sensing using programming signals
US9047944B2 (en) 2013-04-24 2015-06-02 Micron Technology, Inc. Resistance variable memory sensing
US9608739B2 (en) 2013-10-15 2017-03-28 Visteon Global Technologies, Inc. System and method for a blended signal
CN103810118B (zh) * 2014-02-28 2016-08-17 北京航空航天大学 一种stt-mram缓存设计方法
US9330756B2 (en) 2014-08-13 2016-05-03 Micron Technology, Inc. Apparatuses and methods for sensing using an integration component
US9496314B1 (en) 2015-09-14 2016-11-15 Qualcomm Incorporated Shared source line magnetic tunnel junction (MTJ) bit cells employing uniform MTJ connection patterns for reduced area
US10573363B2 (en) 2015-12-02 2020-02-25 Samsung Electronics Co., Ltd. Method and apparatus for performing self-referenced read in a magnetoresistive random access memory
US11133044B2 (en) * 2018-06-01 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Interleaved routing for MRAM cell selection
US10950661B2 (en) * 2019-04-05 2021-03-16 Globalfoundries Singapore Pte. Ltd. Integrated circuits with resistive non-volatile memory cells and methods for producing the same
US12219778B2 (en) * 2020-06-29 2025-02-04 Taiwan Semiconductor Manufacturing Company Limited Multi-gate selector switches for memory cells and methods of forming the same
TWI775138B (zh) * 2020-09-03 2022-08-21 力晶積成電子製造股份有限公司 複合型記憶體結構
US12148487B2 (en) * 2021-08-06 2024-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. High-density and high-voltage-tolerable pure core memory cell

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6510079B2 (en) * 2000-10-11 2003-01-21 Infineon Technologies Ag MRAM configuration
US20040165427A1 (en) * 2003-02-20 2004-08-26 Won-Cheol Jeong Magnetic memories having magnetic tunnel junctions in recessed bit lines and/or digit lines and methods of fabricating the same
US20080094886A1 (en) * 2006-10-20 2008-04-24 Rajiv Yadav Ranjan Non-uniform switching based non-volatile magnetic based memory
US20080247222A1 (en) * 2007-04-05 2008-10-09 Qualcomm Incorporated Spin Transfer Torque Magnetoresistive Random Access Memory and Design Methods
US20080266943A1 (en) * 2007-04-24 2008-10-30 Magic Technologies, Inc. Spin-torque MRAM: spin-RAM, array

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW578149B (en) * 2002-09-09 2004-03-01 Ind Tech Res Inst High density magnetic random access memory
KR100480644B1 (ko) * 2003-02-28 2005-03-31 삼성전자주식회사 셀 구동 전류가 증가된 상 변화 메모리
US7978498B2 (en) * 2009-04-03 2011-07-12 Sandisk 3D, Llc Programming non-volatile storage element using current from other element
US8233309B2 (en) * 2009-10-26 2012-07-31 Sandisk 3D Llc Non-volatile memory array architecture incorporating 1T-1R near 4F2 memory cell

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6510079B2 (en) * 2000-10-11 2003-01-21 Infineon Technologies Ag MRAM configuration
US20040165427A1 (en) * 2003-02-20 2004-08-26 Won-Cheol Jeong Magnetic memories having magnetic tunnel junctions in recessed bit lines and/or digit lines and methods of fabricating the same
US20080094886A1 (en) * 2006-10-20 2008-04-24 Rajiv Yadav Ranjan Non-uniform switching based non-volatile magnetic based memory
US20080247222A1 (en) * 2007-04-05 2008-10-09 Qualcomm Incorporated Spin Transfer Torque Magnetoresistive Random Access Memory and Design Methods
US20080266943A1 (en) * 2007-04-24 2008-10-30 Magic Technologies, Inc. Spin-torque MRAM: spin-RAM, array

Also Published As

Publication number Publication date
US20120275219A1 (en) 2012-11-01
US8724378B2 (en) 2014-05-13
US20100259976A1 (en) 2010-10-14
WO2010118181A2 (fr) 2010-10-14
US8238145B2 (en) 2012-08-07

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