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WO2010105492A1 - Procédé d'encapsulation d'une pluralité de puces led à structure verticale sur une base, pour fabriquer une source de lumière led - Google Patents

Procédé d'encapsulation d'une pluralité de puces led à structure verticale sur une base, pour fabriquer une source de lumière led Download PDF

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Publication number
WO2010105492A1
WO2010105492A1 PCT/CN2010/000149 CN2010000149W WO2010105492A1 WO 2010105492 A1 WO2010105492 A1 WO 2010105492A1 CN 2010000149 W CN2010000149 W CN 2010000149W WO 2010105492 A1 WO2010105492 A1 WO 2010105492A1
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Prior art keywords
conductive
led
base
led chips
led chip
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Ceased
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PCT/CN2010/000149
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English (en)
Chinese (zh)
Inventor
楼满娥
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Zhejiang Manelux Lighting Co Ltd
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Zhejiang Manelux Lighting Co Ltd
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Priority to CN2010800015651A priority Critical patent/CN102037559B/zh
Publication of WO2010105492A1 publication Critical patent/WO2010105492A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10H20/00
    • H01L25/0753—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10H20/00 the devices being arranged next to each other
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21K—NON-ELECTRIC LIGHT SOURCES USING LUMINESCENCE; LIGHT SOURCES USING ELECTROCHEMILUMINESCENCE; LIGHT SOURCES USING CHARGES OF COMBUSTIBLE MATERIAL; LIGHT SOURCES USING SEMICONDUCTOR DEVICES AS LIGHT-GENERATING ELEMENTS; LIGHT SOURCES NOT OTHERWISE PROVIDED FOR
    • F21K9/00—Light sources using semiconductor devices as light-generating elements, e.g. using light-emitting diodes [LED] or lasers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a technology for fabricating a light emitting diode (hereinafter referred to as LED) in a multi-chip integrated package, and more particularly to a method for integrally mounting an LED chip of a plurality of vertical structures on a base to prepare an LED light source.
  • LED light emitting diode
  • LED As one of the mainstream light sources for next-generation lighting, LED has been recognized by the industry, but the illumination source requires not only high light efficiency, but also high luminous flux. It is often necessary to reach hundreds or even thousands of lumens. At present, the power of a single LED chip can withstand less than 10W, and its power conversion efficiency decreases as power increases. For example: a blue chip capable of withstanding 1.
  • 2W of electric power, plus YAG phosphor, made of white LED its luminous efficiency can reach 100 lumens / watt, the same process with a chip capable of withstanding 5W electric power into a white LED, it The luminous efficacy is only about 75 lumens per watt, and when it is 8W, the luminous efficacy is only 60 lumens per watt, and only 60% of the blue chip of 1. 2W of electric power is used.
  • planar LED chip has positive and negative electrodes disposed on the upper surface of the chip, and the working current of the chip does not pass through the bottom surface.
  • a vertically structured LED chip that is, one electrode is disposed on the upper surface of the chip, and the other electrode is disposed on the lower surface of the chip, and the chip operating current is drawn through the lower surface of the chip.
  • the base for carrying the chip must be made of a material with high thermal conductivity; and because it is a practical device, the base must have a certain mechanical strength.
  • the most widely used LED bases are made of copper or aluminum. These two materials have very good thermal conductivity. Their thermal conductivity is second only to silver in metals. But for most metals, the conductivity is good and the conductivity is not Often, this poses a very serious problem for the integrated packaging of vertical structure chips.
  • the vertical structure of the LED chip is disposed on the lower surface of the chip, when the base carrying the LED chip is a copper or aluminum metal material, when a plurality of LED chips are fixed on the base, if the vertical structure of the LED
  • the adhesive between the chip and the base is electrically conductive, and the bottom electrodes of all the chips mounted on the base are naturally electrically connected; that is, their electrical connection can only be used in parallel; however, actually the chip All paralleling is not feasible because the drive current can be large. If the adhesive is non-conductive, the bottom electrode can not be taken out, so the LED chip with vertical structure can not realize the integration of multiple LED chips into LED practical illumination source.
  • the planar structure chip is mounted on a base having good thermal conductivity and good electrical conductivity.
  • the base and the chip are electrically insulated, and can be electrically connected through electrodes on the chip, that is, connected in series, in parallel or in series. It can be done, but it is not feasible for vertical chips. Summary of the invention
  • the object of the present invention is to overcome the defects that a plurality of vertical structure LED chips cannot be directly mounted on a metal base when manufacturing an LED illumination source; in order to make the vertical structure chip and the planar structure chip the same, in one LED chip receiving cavity In the series, the multi-chip series, parallel or series and parallel combination of electric integrated package, to achieve a LED with a practical illumination source for the usual illumination, thereby proposing a plurality of vertical structure LED chips on a base A method of preparing an LED illumination source.
  • the invention provides a method for preparing an LED illumination source for packaging a plurality of vertical structure LED chips on a base. For the use of conductive and non-conductive bases, the following steps are respectively taken:
  • N and M are equal, and N and M 2;
  • the area is larger than the area of the LED chip and extends out of the periphery of the LED chip to facilitate electrical connection with adjacent LED chips; the conductive power sources are electrically insulated from each other.
  • the N vertical-structured LED chips are connected in series, in parallel, or in series and in parallel, and the terminals are fixed on the base through the lead and the external power lead frame, or the bayonet is fixed, and the external power leads are
  • the frame is insulated from the base, and the current generated by the external power source flows into the LED through the lead frame.
  • the non-conductive base is made of low temperature ceramic or plastic, and the non-conductive is The conductive region is formed on the base.
  • a sheet having a larger area than the LED chip (the sheet is used as a conductive region) is formed by using a material that is both electrically conductive and thermally conductive, and the sheet is embedded in the non-conductive base to expose the upper surface of the sheet.
  • a non-conductive base (see Figure lc);
  • the conductive region material is a silver or gold-tin alloy layer or the like (see FIG. 1a).
  • the method for packaging a plurality of vertical structure LED chips on a base provided by the present invention when using a conductive base, there are two preparation methods, and the first method comprises the following steps:
  • N and M are equal, and ⁇ or ⁇ ! 2;
  • the area of the conductive area is larger than the area of the LED chip, and extends out of the periphery of the LED chip to facilitate electrical connection with the adjacent LED chip;
  • the N vertical structure LED chips are then connected in series, in parallel or in series and in parallel in electrical connection.
  • the terminal is electrically connected to the external power supply through the bow wire and the outer power cable.
  • the conductive base is made of metal aluminum or copper; when the conductive base is made of metal aluminum, an aluminum nitride or aluminum oxide film is formed on the base of the metal aluminum, and then nitrogen is used.
  • a conductive layer is formed at a position where the LED chip and the lead wire are to be placed, and the conductive layer is formed by a screen printing method, a vacuum film forming process or an electroplating process to form a silver or gold tin alloy layer; 01 ⁇ The thickness of the layer of 0. 05 ⁇ 0. 01mm.
  • the method further includes: fixing (eg, inlaying, bonding) a piece of insulating material having thermal conductivity on the LED chip bearing surface of the conductive base; the insulating material piece is a diamond film and a high resistance single A crystalline silicon wafer, a silicon carbide wafer, a nanocarbon sheet, a nanocarbon material, a carbon composite material, a mica sheet, a graphite sheet, or a composite thereof (see Fig. 2a).
  • the second method includes the following steps:
  • the N vertical structure LED chips are connected in series, in parallel or in series, and in parallel, and the terminals are electrically connected through the lead wires and the external power lead frame and the external power source.
  • the conductive base may be made of copper or aluminum.
  • the M' non-conductive regions are formed on the LED chip bearing surface of the conductive base by a damascene, bonding or soldering process, and the high resistance single crystal silicon wafer, silicon carbide wafer, nanometer 5 ⁇ 0
  • the thickness of the sheet is 0. 05 ⁇ 0
  • the sheet thickness of the sheet is 0. 05 ⁇ 0 Olrran; further, on the upper surface of each of the sheets, a conductive region is formed according to the size of the LED chip and the shape of the bottom electrode lead-out area for mounting the LED chip and the bottom electrode, and the back surface of the sheet is plated for splicing. Tin-tin, silver or gold-tin alloy materials to join the original conductive base.
  • the conductive region may be inlaid or casted, embedded in a plastic or low-temperature ceramic, cast copper sheet, aluminum sheet; or on plastic or low-temperature ceramic, printed,
  • a vacuum coating or spraying method is used to form a layer of a metal such as gold, silver or tin or an alloy layer thereof.
  • the method further comprises growing a diamond film or depositing a nano carbon film on the silicon wafer.
  • the series connection method is as follows: a gold wire is connected from a conductive area on the bottom surface of one LED chip to a conductive area on the top surface of an adjacent LED chip, and then N pieces are sequentially sequentially replaced by a gold wire.
  • the vertical structure of the LED chips are electrically connected in series and then electrically connected to the external LED electrical lead wires (see FIG. 1a);
  • the parallel connection is as follows: all N vertical structure LED chip top electrodes are connected by one gold wire, and the other electrode is on the lower surface of the LED chip, the electrode and the conductive area are electrically connected, on the conductive area
  • the vacant part around the LED chip becomes the lead-out area of the lower surface electrode of the LED chip; the vacant part of the conductive area of one LED chip is connected in parallel with the vacant part of the conductive area of the adjacent LED chip, and the figure Id is three.
  • a schematic diagram of parallel connection of LED chips, after completion, is electrically connected to an external LED chip electrical lead-out line;
  • the invention provides a method for preparing an LED illumination source having the luminous flux required for normal illumination, and solves the problem that the vertical structure LED chip cannot be mounted on the bearing surface of the same base, and is combined into a high-power LED; the preparation of the invention
  • the electric combination of parallel or series and parallel combination is integrated and packaged, so as to achieve the purpose of one LED having the luminous flux required for normal illumination.
  • the preparation method is simple and easy to scale production.
  • the prepared LED illumination source has practicality and long service life, and the power can reach 50W, 100W or even larger.
  • FIG. 1 is a structural cross-sectional view of an LED illumination source made by mounting a plurality of conductive regions on a surface of a non-conductive base, and mounting a vertical structure of LED chips in each conductive region.
  • FIG. 1b is a structure shown in FIG. Top view
  • Figure lc is a cross-sectional view showing a structure in which a plurality of conductive materials are embedded in the upper surface of the non-conductive base of the present invention
  • FIG. 1d is a schematic diagram of an electrical connection embodiment in which three chips are connected in parallel according to the present invention.
  • 2a is a cross-sectional view showing the structure of an LED chip in which a vertical structure is formed by depositing an insulating non-conductive layer on the surface of the conductive substrate, and then forming N conductive regions on the non-conductive layer.
  • Figure 2b is a cross-sectional view showing the structure of an LED chip with a vertical structure in each conductive region by splicing an insulating sheet on the upper surface of the conductive base and then making N conductive regions on the insulating sheet.
  • Figure 2c is a cross-sectional view showing the fabrication of a plurality of insulating non-conductive regions on the upper surface of the conductive base, and then N conductive regions on the insulating layer, and mounting two vertical LED chips in each conductive region.
  • Figure 2d is a top view of the structure shown in Figure 2c
  • Figure 3 is a structure of an LED illumination source in which a metal piece is embedded in a non-conductive base of plastic, a vertical structure of an LED chip is mounted in each metal piece (conductive area), and electrical connection is made.
  • FIG. 4 is a cross-sectional view showing the structure of a 20W LED illumination source produced by the method of the present invention.
  • Figure 5 is a plan view showing the structure of a 50W LED illumination source produced by the method of the present invention. The picture is as follows:
  • Non-conductive base 1.
  • Conductive area 3. LED chip
  • Chip top surface electrode 4. Chip bottom electrode lead-out area 6. External power lead
  • an LED having a rated current of 700 raA and a power of 7 W is prepared, and the specific steps are as follows:
  • the conductive region 2 is made of a gold or silver film by printing or evaporation process; the area of the conductive region 2 is larger than the area of the LED chip 3, and extends out of the periphery of the LED chip 3, so as to be adjacent to 5 ⁇
  • the area of each of the conductive areas is 1. 5 mmX l. 5 mm.
  • the LED chip 3 of the vertical structure of 1. 0W-1. 2W is packaged in the six conductive regions 2 of the drawing, and the three LED chips 3 are used as a group, and the gold wire 7 is used.
  • a set of three LED chips are connected in series (refer to FIG. 1a), and then the two groups connected in series are electrically connected.
  • the terminal is connected to the driving power source through the external power supply lead 6, and the LED chip 3 is covered with Transparent optical material, transparent optical material can be silica gel, epoxy resin or lens; if white LED is to be made, blue light chip should be used, and the optical material covered on the blue chip should contain light conversion material such as phosphor (refer to the figure). Lb), these can be achieved by the skilled person, prepared into a rated current of 700mA, power of 7W LED.
  • the electrical connection is not in a proper manner. It is preferable to make a proper series connection and then parallel connection. Since the 12V is a universal power supply voltage, the voltage of the three LED chips 3 in series is 9. 0V - 10. 5V The voltage is exactly matched with the voltage of 12V. Therefore, the present embodiment uses three chips in series, and then serially connects the two electrical connections, which can be implemented by those skilled in the art.
  • a non-conductive base 1 is made of plastic or low-temperature ceramic material to prepare a 7W LED light source. 5 ⁇ 0 0.
  • the thickness of the thickness of the substrate is 0. 5mm ⁇ 0.
  • the thickness of the thickness of the substrate is 0. 5mm ⁇ 0 Lmm silver plated brass sheet, the frame is made around the silver plated brass piece, and the metal foil is shown in Fig. 3. It is a metal for mounting three strings of two LED chips 3 for electrical connection.
  • the sheet is then pressed into the non-conductive base 1 of the present embodiment to form an embedded conductive region 8.
  • the LED chip 3 can be placed in a large area, and the electrical connection is made, and the three chips are connected in series, and then the two groups are connected in parallel, and then taken out, as shown in the figure. 1 (b).
  • Low-temperature ceramics and plastics have poor thermal conductivity, so the base should be thin. Under the condition of satisfying the mechanical strength, it is as thin as possible, generally about 0.5 ⁇ 2mm, which is beneficial to the heat transfer to the radiator below. If the inorganic material is doped into the thermoplastic material, its thermal conductivity can be greatly improved, and it is suitable for mass production.
  • Example 2
  • a 20W white LED illumination source is fabricated using a vertical structure LED chip.
  • a general-purpose 20W white LED is produced by using a blue chip and a YAG garnet phosphor. Since the power of the entire LED is already quite large, the 20 or so LED chips 3 and 20 used in the operation of the LEDs have a large amount of heat generated during the simultaneous operation. Therefore, the non-conductive substrate in the embodiment 1 is not ideal for heat treatment. Another option in the present invention is required.
  • the conductive base 9 is made of an aluminum plate with a thickness of about 3 mm, and the aluminum plate is made into a basin shape.
  • the central portion of the aluminum plate is made into a pelvic bottom, and the bottom of the pelvis is a circle having a diameter of about 10-20 mm, and the aluminum plate can also be used.
  • the utility model is formed into a rectangle of considerable area, and two steps are arranged from the bottom of the bottom of the basin wall, the top of the basin edge is a platform, and the outer power lead 6 is arranged on the platform, as shown in FIG. 4; wherein, from the bottom of the basin
  • the angle between the slope of the first step and the plane of the basin bottom is between 100° and 160°, and the angle of the second step is not strictly required, so that the electrode is taken out as a principle.
  • a non-conductive layer 10 is formed on the bottom of the conductive base 9 to form a thin film of insulating material.
  • the general material film is formed into an aluminum nitride film or an aluminum oxide film by a conventional coating method.
  • Aluminum nitride has good thermal conductivity and insulation properties, but it is expensive, so alumina is usually used.
  • a conductive screen 2 is printed by using a conventional screen printing technique, that is, 20 conductive regions 2 (as shown in FIG. 4). Show).
  • 20 LED chips 3 are respectively divided into 4 groups, each group of 5 LED chips 3 are connected in series, and 4 groups in series are connected in parallel to each conductive region 2 made of silver paste. Put a 1W LED chip 3 and sinter the LED chip 3, then use the gold wire 7 to make the above electrical connection. First connect the 5 chips in series, then connect the LED chips 3 in the four groups. Together, the negative poles are connected together.
  • the white LED After completion, it is made by coating the white LED with the YAG phosphor powder on the chip, and then coating the transparent protective film. If the monochromatic light is added, the optical material such as transparent silica gel can be used to make the LED. Illumination source, which can be implemented by those skilled in the art.
  • an aluminum plate can also be used as the conductive base 9, that is, without making a basin type, an aluminum oxide insulating layer is directly formed on the aluminum plate, and an LED chip mounting region is made on the insulating layer of the aluminum oxide (20 conductive layers).
  • Zone 2 other electrical connection zones and connections are as described above.
  • such a structure must be protected by an optically transparent material for the LED chip carrying surface of the entire base 9, including the gold wire bonding area, which can be implemented by those skilled in the art to prevent contact or collision. Cause damage.
  • the electrical connection mode is 8 chips 3 connected in series, and six groups are connected in parallel to produce a 50W green LED illumination source, and the material and characteristics of the green LED chip. It has the same characteristics as the blue LED chip, and both can be used universally.
  • the conductive base 9 in this embodiment is a common metal copper base, and a high-resistance single crystal silicon wafer 14 having a thickness of 0.05 to 0.01 mm is used as a non-conductive region 11 on the metal copper base, which can be considered as Not electrically conductive.
  • the high-resistance single crystal silicon wafer 14 is plated with gold-tin alloy or other solderable material on both sides, and then patterned into one surface on one side by photolithography, thereby forming 48 mutually insulated conductive regions 2 and chips.
  • the bottom electrode lead-out area 5 (shown in Figure 5).
  • the other side of the high-resistance single crystal silicon wafer 14 has been plated with a gold-tin alloy or other solderable material, it can be attached to the copper base and equipped with a corresponding commercially available lead frame, thus making a suitable application.
  • the subsequent manufacturing process and the general LED manufacturing method are the same.
  • the method of the present invention can be divided into three categories, as follows:
  • N pieces of metal foil are produced, each of which is larger than the area of the LED chip, and then the metal foil is pressed into a plastic or low-temperature ceramic to form N conductive regions that are insulated from each other.
  • the N vertical structure LED chips are respectively placed on the N metal foils, the metal foil becomes the bottom electrode of the chip, and the top surface of the chip is the other electrode, so that the two electrodes of each chip are insulated from the other chip electrodes.
  • the bottom electrode of the previous chip and the top electrode of the latter chip are connected together by a gold wire to form a series connection between the two chips.
  • the LED chips are electrically connected in series or in parallel; as shown in Fig.
  • this is a metal foil for three strings.
  • Low-temperature ceramics and plastics have poor thermal conductivity, so the base should be thin. Under the condition of satisfying the mechanical strength, it is as thin as possible, which is beneficial to the heat transfer to the radiator below.
  • N mutually insulated conductive regions by printing or sputtering on a non-conductive base for mounting the chip and electrical connections.
  • the film is commonly referred to as a film, for example, in aluminum.
  • the film is coated with a thin film of a conductive layer.
  • the insulating layer is not electrically conductive, but has a certain degree of thermal conductivity, and the thickness of the insulating layer is about 0. 05 ⁇ 0.
  • a thin film of aluminum nitride or aluminum oxide is formed on the base, and a conductive layer is formed on the aluminum nitride or aluminum oxide film at a position where the LED chip and the lead wire are to be placed, for example, silver paste or silver or gold plating is applied by silk screen printing.
  • the conductive layer is formed by a process such as tin alloy, and the bottom electrodes of such a plurality of LED chips are separately drawn separately, and the electrical connection of the series, parallel connection and series-parallel connection can be performed between the chips. Due to the aluminum nitride, aluminum oxide has a certain thermal conductivity and is very thin, so it has little effect on the heat dissipation of the chip.
  • the LED base which is both conductive and thermally conductive, a layer of insulating but certain thermal conductivity is covered on the chip bearing surface by bonding or splicing, such as high resistance monocrystalline silicon wafer, silicon carbide wafer, Nano carbon sheet or nano carbon material, carbon composite material, mica sheet, graphite sheet, etc. and other composite materials, the upper surface of the sheet, according to the needs of the integrated package, the LED chip mounting area and the bottom electrode lead-out area are formed on the back side of the sheet.
  • bonding or splicing such as high resistance monocrystalline silicon wafer, silicon carbide wafer, Nano carbon sheet or nano carbon material, carbon composite material, mica sheet, graphite sheet, etc. and other composite materials
  • Plated with splicable materials such as tin-tin, silver, gold-tin alloy, etc., to be bonded to the original conductive base, or a bonding process, using a bonding or bonding process to wafer or Nano-carbon sheets and the like are bonded to a highly thermally conductive and electrically conductive base.
  • the present invention can grow a thin film material having a very high thermal conductivity on a silicon wafer, for example, a diamond film or a precipitated nanocarbon film on a silicon substrate, diamond
  • the thermal conductivity is almost five times that of copper. Therefore, the heat generated by the chip can be quickly transferred to the peripheral area of the chip, and then transferred to the heat dissipation base through the silicon wafer to achieve the purpose of rapid heat dissipation.
  • the thermal conductivity of the material such as nano carbon is copper. Double, but slightly reduced when made of non-conductive film, but it will greatly improve the thermal conductivity of silicon wafer.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Led Device Packages (AREA)

Abstract

La présente invention concerne un procédé d'encapsulation d'une pluralité de puces LED à structure verticale sur une base pour fabriquer une source de lumière LED. Dans le procédé selon l'invention : M régions conductrices (2), dont le nombre est égal au nombre des puces, sont formées sur la surface de portée de puces d'une base non conductrice (1) ; la surface de chacune des régions conductrices est plus grande que la surface de chacune des puces ; N puces LED (3) sont montées sur chacune des régions conductrices, respectivement, et les N puces LED sont connectées électriquement en série, en parallèle, ou en série/parallèle. Le procédé selon l'invention permet à une pluralité de puces à structure verticale d'être connectées électriquement à l'intérieur d'un seul réceptacle de puces LED, exactement comme les puces à structure plane, de telle sorte que des flux requis pour un éclairage classique sont obtenus.
PCT/CN2010/000149 2009-03-20 2010-02-03 Procédé d'encapsulation d'une pluralité de puces led à structure verticale sur une base, pour fabriquer une source de lumière led Ceased WO2010105492A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2010800015651A CN102037559B (zh) 2009-03-20 2010-02-03 在一底座上封装多个垂直结构led芯片制备led光源的方法

Applications Claiming Priority (2)

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CN200910080131 2009-03-20
CN200910080131.4 2009-03-20

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WO2010105492A1 true WO2010105492A1 (fr) 2010-09-23

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PCT/CN2010/000149 Ceased WO2010105492A1 (fr) 2009-03-20 2010-02-03 Procédé d'encapsulation d'une pluralité de puces led à structure verticale sur une base, pour fabriquer une source de lumière led

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CN (1) CN102037559B (fr)
WO (1) WO2010105492A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109633823A (zh) * 2019-02-15 2019-04-16 昂纳信息技术（深圳）有限公司 一种芯片封装结构及可调衰减装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6121637A (en) * 1997-10-03 2000-09-19 Rohm Co., Ltd. Semiconductor light emitting device with increased luminous power
US7081667B2 (en) * 2004-09-24 2006-07-25 Gelcore, Llc Power LED package
CN2927319Y (zh) * 2006-06-20 2007-07-25 楼满娥 用于安装led芯片的电连接装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6121637A (en) * 1997-10-03 2000-09-19 Rohm Co., Ltd. Semiconductor light emitting device with increased luminous power
US7081667B2 (en) * 2004-09-24 2006-07-25 Gelcore, Llc Power LED package
CN2927319Y (zh) * 2006-06-20 2007-07-25 楼满娥 用于安装led芯片的电连接装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109633823A (zh) * 2019-02-15 2019-04-16 昂纳信息技术（深圳）有限公司 一种芯片封装结构及可调衰减装置

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Publication number Publication date
CN102037559A (zh) 2011-04-27
CN102037559B (zh) 2012-05-30

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