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WO2010144097A1 - Mémoire sur puce hiérarchique - Google Patents

Mémoire sur puce hiérarchique Download PDF

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Publication number
WO2010144097A1
WO2010144097A1 PCT/US2009/047253 US2009047253W WO2010144097A1 WO 2010144097 A1 WO2010144097 A1 WO 2010144097A1 US 2009047253 W US2009047253 W US 2009047253W WO 2010144097 A1 WO2010144097 A1 WO 2010144097A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
volatile memory
data
crossbar
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2009/047253
Other languages
English (en)
Inventor
Gilberto Medeiros Ribeiro
R. Stanley Williams
Matthew D. Pickett
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Development Co LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Priority to US13/256,242 priority Critical patent/US8885422B2/en
Priority to PCT/US2009/047253 priority patent/WO2010144097A1/fr
Priority to TW099116818A priority patent/TWI531033B/zh
Publication of WO2010144097A1 publication Critical patent/WO2010144097A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array

Definitions

  • Fig. 1 is a diagram of an illustrative embodiment of a memory hierarchy within a computer system, according to one embodiment of principles described herein.
  • Fig. 2 is a perspective view of a crossbar memory array, according to one embodiment of principles described herein.
  • Fig. 3 is a diagram showing a cross-section of an illustrative hierarchical on-chip memory which includes a crossbar memory array and a complimentary metal-oxide-semiconductor (CMOS) layer, according to one embodiment of principles described herein.
  • CMOS complimentary metal-oxide-semiconductor
  • Fig. 4 is cross-sectional diagram of an illustrative hierarchical on-chip memory which includes a CMOS layer and multiple crossbar memory arrays, according to one embodiment of principles described herein.
  • FIG. 5 is a perspective view of a memory module which includes chips which have hierarchical on-chip memory, according to one embodiment of principles described herein.
  • Fig. 6 is a flow chart describing one illustrative method for forming hierarchical on-chip memory, according to one embodiment of principles described herein.
  • Fig. 8 is a flow chart of an illustrative method for managing data within a hierarchical on-chip memory, according to one illustrative embodiment of principles described herein.
  • Fig. 9 is a flow chart of an illustrative method for managing data within a hierarchical on-chip memory, according to one illustrative embodiment of principles described herein.
  • the hierarchical on-chip memory described below integrates two or more different memory types into a single integrated circuit which is accessed through a common interface and circuitry.
  • the hierarchical on-chip memory is a three dimensional multilayer circuit which includes a hybrid of Complimentary Metal Oxide Semiconductor (CMOS) memory circuitry and crossbar memory arrays.
  • CMOS memory circuitry provides a fast access memory which has a limited capacity, while the crossbar memory arrays provide non-volatile, inexpensive, large capacity memory.
  • the CMOS memory circuitry include Dynamic Random Access Memory (DRAM) or its variations, Static Random Access Memory (SRAM), Flash memory or its derivatives, or other memory technologies.
  • DRAM Dynamic Random Access Memory
  • SRAM Static Random Access Memory
  • Flash memory or its derivatives, or other memory technologies.
  • This multilayer circuit can be contained within a chip package which accessed through a single interface and combines the storage capacity of a hard drive with the fast access times of random access memory.
  • FIG. 1 is a simplified diagram of one illustrative embodiment of a memory hierarchy (100) within a computer system.
  • a memory hierarchy (100) can take a variety of forms and include a variety of interfaces (130).
  • the interfaces (130) are indicated by double headed arrows and show connectivity between various components within the computer system.
  • the illustrated interfaces (130) are not intended to be comprehensive or show the only data path through the memory hierarchy (100).
  • the interfaces (130) may be different for each type of memory, or may share common elements with interfaces to other memories.
  • the processor immediately reads from or writes to the on-chip cache (110), which is much faster than reading from or writing to other memory sources.
  • the cache memory (110) is typically constructed from very fast and very expensive memory. Consequently, the cache memory (110) has limited size, but can respond very quickly to requests from the CPU (105). [0019] Off-chip cache (115) is physically separated from the CPU
  • the primary volatile memory (120) is typically random access memory (RAM) which can be much larger and less expensive than cache type memory. According to one embodiment, the primary volatile memory (120) is contained in a separate circuit board, such as a Dual In-line Memory Module (DIMM) which incorporates a series of dynamic RAM chips. These modules are typically mounted into connectors on the CPU motherboard and can be removed or replaced.
  • DIMM Dual In-line Memory Module
  • the primary volatile memory (120) is slower than on-chip cache (110) and has longer read and write latencies. However, the primary volatile memory (120) is usually large enough to store current software instructions and frequently accessed data. For example, the primary volatile memory (120) may contain gigabytes of memory space.
  • non-volatile memory (125) is configured to retain data over long periods of time.
  • non-volatile memory (125) may only support a limited number of write cycles due to memory wear or other factors. For example, a given segment of flash memory can withstand around 100,000 write-erase cycles before the memory begins to deteriorate the integrity of the storage.
  • magnetic based non-volatile memory (125) such as hard drives and tape drives have limited lifetimes, with most failures resulting from mechanical damage to the medium or supporting mechanisms.
  • non-volatile memory may be its relatively long data access times. For example, when data is stored on a hard drive platter, the reading head must be physically repositioned over the location where the desired data is stored. Similarly, if the data is stored on magnetic tape, the tape must be wound to the location of the desired data. This physical reposition of the reading head or medium can require a significant amount of time compared to memories which do not rely on moving mechanisms.
  • a number of interfaces (130) and associated data buses are required to access the various memory types. In many cases separate busses and interfaces are used for each type of memory. This increases the cost and complexity of the computer system.
  • a crossbar memory array with programmable crosspoint devices can provide a highly compact nonvolatile storage medium which can be directly integrated over CMOS memory circuitry.
  • the crossbar array memory can store large amounts of data in the same area as the underlying CMOS memory circuitry and can be accessed through the same interface. This can provide a number of advantages, including simplifying the interface between the processor and the memory, reducing the total chip count of the computer device, eliminating the need for conventional hard drives, lowering the cost of the computer device, result in a smaller computer device, and other advantages.
  • Fig. 2 is a perspective view of an illustrative crossbar array
  • nanowires can also have square, circular, elliptical, or more complex cross sections.
  • the nanowires may also have many different widths or diameters and aspect ratios or eccentricities.
  • nanowire crossbar may refer to crossbars having one or more layers of sub- microscale wires, microscale wires, or wires with larger dimensions, in addition to nanowires.
  • the layers may be fabricated using a variety of techniques using any type of metal or highly conductive semiconducting material.
  • the nanowires may be fabricated by conventional photolithography as well as mechanical nanoimphnting techniques.
  • nanowires can be chemically synthesized and can be deposited as layers of approximately parallel nanowires in one or more processing steps, including Langmuir- Blodgett processes.
  • Other alternative techniques for fabricating nanowires may also be employed, such as interference lithography.
  • Many different types of conductive and semi-conductive nanowires can be chemically synthesized from metallic and semiconductor substances, from combinations of these types of substances, and from other types of substances.
  • the memristive device is read by applying a lower reading voltage which allows the internal electrical resistance of the memristive device to be sensed but does not generate a high enough electrical field to cause significant dopant motion.
  • the memristive device exhibits a rectifying behavior similar to Schottky diode.
  • the state of the memristive device can be read by applying a read stimulus (current or voltage) adjusted to maximize the bandwidth while minimizing the heat dissipation.
  • the read stimulus is a forward voltage bias across specified junction while reverse biasing other memristive devices in the array to suppress leakage currents.
  • programmable crosspoint devices (210) may perform a variety of functions including providing programmable switching between the nanowires.
  • programmable crosspoint devices (210) may have two states: a conductive state and a nonconductive state.
  • the conductive state may represent a binary "1 " and the nonconductive state may represent a binary "0", or visa versa.
  • Binary data can be written into the crossbar architecture (200) by changing the conductive state of the memristive crosspoint devices (210). The binary data can then be retrieved by sensing the state of the programmable crosspoint devices (210).
  • Fig. 3 is a diagram showing an illustrative three dimensional multilayer circuit (300) which includes a CMOS layer (310) and an overlying crossbar array (305).
  • the semiconductor industry has been improving the performance and density of integrated circuits primarily by shrinking the size of the electronic elements within the circuits.
  • a number of barriers are becoming evident which increase the difficulty of making further reduction to the size of these elements.
  • One potential solution for increasing the performance and planar density of integrated circuits is to create three dimensional circuits which contain multiple layers of interconnected circuitry.
  • Various three dimensional circuits which include integrated crossbar arrays are described in PCT Application No.
  • the crossbar array (305) is electrically connected to the underlying CMOS layer (310) by two groups of vias (325, 330).
  • a first group of vias (325) connects to the lower crossbar lines (322) and a second group of vias (330) connects to the upper crossbar lines (320).
  • the hierarchical on-chip memory may combine the speed of volatile RAM with the capacity of a hard drive into a single package. Consequently, in some embodiments, one or more memory modules (500) may replace both the volatile (120, Fig. 1 ) and nonvolatile (125, Fig. 1 ) memories in a computing architecture.
  • Fig. 6 is a flow chart describing one illustrative method for forming hierarchical on-chip memory.
  • the method includes forming a CMOS layer which includes volatile memory and covering the upper surface of the CMOS layer with a passivating/electhcally insulating layer (step 600).
  • a number of vias are connected to the CMOS layer and extend through the electrically insulating layer (step 610). These vias provide electrical access to the underlying CMOS layer.
  • a first crossbar array is then formed.
  • the crossbar array includes programmable crosspoint devices which are interposed between intersecting crossbar segments. These crossbar segments are electrically connected to the vias (step 620).
  • FIG. 7 shows the partitioned B-tree (700) when the query starts.
  • records from the partitions (710, 717, 720) satisfying the query predicate create multiple sorted streams (745).
  • the query predicate identifies key ranges within the partitions which are identified by a diagonally lined box within each partition. This data forms multiple sorted streams (745) that form a query result (755).
  • the query result (755) is returned as the answer to the query.
  • the partitioned B-tree algorithm is only one illustrative embodiment of a data management technique which is particularly suited for use with hierarchical on-chip memory.
  • a variety of other data management techniques could be used which divide data between the two memory types according to its frequency of usage. For example, data which is rewritten more frequently than a predetermined threshold is written into volatile memory and data which is written at or less frequently than the predetermined threshold is stored in non-volatile memory.
  • a variety of other data management approaches could be used, include conventional data techniques for accessing and writing to hard drives and volatile RAM.
  • a preference is given to writing data which is not going to be changed or rewritten to the crossbar memory.
  • a reference data table which holds unchanging physical constants may efficiently stored in the crossbar memory array.
  • Another example of data which could be efficiently stored in the crossbar memory array could be a directory of contact information. This information would change relatively slowly and making changes to the directory would induce minimal wear on crossbar memory array.
  • log files, file allocation tables, and other high accessed/modified parts of the file system could induce undesirable wear in the crossbar memory.
  • These types of files could be stored in volatile memory until an event triggered the files to be backed up to crossbar memory.

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  • Semiconductor Memories (AREA)

Abstract

L'invention porte sur une mémoire sur puce hiérarchique (400) qui comprend une couche CMOS à surface distribuée (310) comprenant une fonctionnalité d'entrée/sortie et une mémoire volatile et un ensemble de trous d'interconnexion (325, 330), la couche CMOS à surface distribuée (310) étant configurée pour adresser sélectivement l'ensemble de trous d'interconnexion (325, 330). Une mémoire à barres croisées (305) recouvre la couche CMOS à surface distribuée (310) et comprend des dispositifs de point de croisement programmables (315) qui sont accessibles de façon unique par l'intermédiaire de l'ensemble des trous d'interconnexion (325, 330). L'invention porte également sur un procédé d'utilisation d'une mémoire sur puce hiérarchique (400) qui consiste à stocker des données fréquemment réécrites dans une mémoire volatile et à stocker des données qui ne sont pas fréquemment réécrites dans une mémoire non volatile (305), la mémoire volatile étant contenue dans une couche CMOS à surface distribuée (310) et la mémoire non volatile (305) étant formée au-dessus et accessible par l'intermédiaire de la couche CMOS à surface distribuée (310).
PCT/US2009/047253 2009-06-12 2009-06-12 Mémoire sur puce hiérarchique Ceased WO2010144097A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US13/256,242 US8885422B2 (en) 2009-06-12 2009-06-12 Hierarchical on-chip memory
PCT/US2009/047253 WO2010144097A1 (fr) 2009-06-12 2009-06-12 Mémoire sur puce hiérarchique
TW099116818A TWI531033B (zh) 2009-06-12 2010-05-26 階層式晶片上記憶體

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2009/047253 WO2010144097A1 (fr) 2009-06-12 2009-06-12 Mémoire sur puce hiérarchique

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WO2015167495A1 (fr) * 2014-04-30 2015-11-05 Hewlett-Packard Development Company, L.P. Tête d'impression avec ensemble de memristance hors puce
CN109063833A (zh) * 2018-10-29 2018-12-21 南京邮电大学 一种基于忆阻器阵列的神经网络突触觉结构

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TW201113986A (en) 2011-04-16
US20120005418A1 (en) 2012-01-05
TWI531033B (zh) 2016-04-21
US8885422B2 (en) 2014-11-11

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