WO2010035316A1 - Memory control device and memory control method - Google Patents

Abstract

The data of the same physical address is written to memory banks (B0, B1) at the time of write and the data of different physical addresses is read from the memory banks (B0, B1) at the time of read, which are outputted in combination. If the data read from the memory bank (B0) is an uncorrectable error, the data is reread from the place where the data of the same physical address of the memory bank (B1) is written. If the data read from the memory bank (B1) is an uncorrectable error, the data is reread from the place where the data of the same physical address of the memory bank (B0) is written.

Description

Memory control device and memory control method

The present invention relates to a memory control device and a memory control method for controlling memory access to a plurality of memory banks.

When an arithmetic processing unit, so-called CPU (Central Processing Unit) accesses a memory, it issues a physical address (PA) and designates an access destination. The memory control device converts the physical address into a memory address and determines an access destination.

Conventionally, a plurality of memory banks have been connected to a memory control device, and each memory bank has been operated independently. Specifically, the same physical address is assigned to two memory banks and the same data is duplicated and written at the time of writing (write), or different physical addresses are assigned to each memory bank, and at the time of writing / reading A non-mirror mode is known in which throughput is improved by accessing each memory bank (see, for example, Patent Documents 1 and 2).

Also, a technique is known in which a plurality of data is taken out almost simultaneously, each error is individually detected, and an error with respect to the data counterpart is detected almost simultaneously (see, for example, Patent Document 3).

JP-A-63-233439 JP-A-6-250931 JP-A-8-234922

However, with the conventional technology, it has been impossible to achieve both the improvement of reliability by the mirror mode and the improvement of the throughput by the non-mirror mode. Therefore, the realization of a memory control technique having the same reliability as the mirror mode and the same transmission speed as the non-mirror mode has been an important issue.

The present invention has been made in order to solve the above-described problems related to the prior art, and provides a memory control device and a memory control method having the same reliability as the mirror mode and the same transmission speed as the non-mirror mode. The purpose is to provide.

In order to solve the above-described problems and achieve the object, the disclosed apparatus and method write data of the same contents to both the first memory bank and the second memory bank and accept a read request. The data specified by the read request is divided into the first half and the second half, and one memory bank is used for normal read of the first half data and preliminary read of the second half data, and the other memory bank is used for normal read of the second half data and preliminary read of the second half data. Use. The preliminary reading is executed when there is an unrecoverable error in the result of normal reading.

According to the disclosed apparatus and method, it is possible to obtain a memory control apparatus and a memory control method having the same reliability as the mirror mode and the transmission speed equivalent to the non-mirror mode.

FIG. 1 is a conceptual diagram illustrating the concept of the memory control method according to the present embodiment. FIG. 2 is a schematic configuration diagram illustrating a schematic configuration of the computer apparatus according to the present embodiment. FIG. 3 is a configuration diagram illustrating the configuration of the write control unit 21. FIG. 4 is a configuration diagram illustrating the configuration of the read control unit 22. FIG. 5 is an explanatory diagram for explaining a basic operation of a conventional memory control device (MAC). FIG. 6 is an explanatory diagram for explaining the operation in the conventional non-mirror mode. FIG. 7 is an explanatory diagram for explaining the operation in the conventional mirror mode. FIG. 8 is an explanatory diagram for explaining the operation of improving the reliability in the conventional mirror mode. FIG. 9 is an explanatory diagram for explaining the memory control operation according to the present embodiment. FIG. 10 is an explanatory diagram illustrating the reliability improvement operation in the memory control according to the present embodiment. FIG. 11 is an explanatory diagram for explaining address conversion when the address allocation shown in FIG. 9 is performed. FIG. 12 is a diagram illustrating a first modification of address assignment. FIG. 13 is an explanatory diagram for explaining address conversion when the address allocation shown in FIG. 12 is performed. FIG. 14 is a diagram illustrating a second modification of address assignment. FIG. 15 is an explanatory diagram for explaining address conversion when the address allocation shown in FIG. 14 is performed. FIG. 16 is a flowchart for explaining data read processing of the first 64 bytes. FIG. 17 is a flowchart for explaining read processing of data of the latter half 64 bytes. FIG. 18 is a flowchart for explaining the processing operation of the data selection units 22d0 and 22d1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Computer apparatus 11 Arithmetic processing apparatus 12 Memory control apparatus 13 System control apparatus 14 Interface apparatus 21 Write control part 21a, 22a0, 22a1 Address conversion part 21b Error detection information generation part 22 Read control part 22b0, 22b1 Address selection part 22c0, 22c1 Reread Confirmation unit 22d0, 22d1 Data selection unit 22e Data transmission unit B0, B1 Memory bank M01, M02, M11, M12 Memory module

Hereinafter, embodiments of a memory control device and a memory control method according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a conceptual diagram illustrating the concept of the memory control method according to the present embodiment. In the memory control method according to the present embodiment, the same contents are duplicated and written at the time of writing, and the data read from different addresses are combined and transmitted at the time of reading.

In the example shown in FIG. 1, the same physical address is assigned to the same DIMM address for the two memory banks B0 and B1, each of which is a set of a plurality of DIMMs (Dual Inline Memory Modules). The same data is written in 4-7. Since the transfer amount per cycle of the memory banks B0 and B1 is 64 bytes, the transmission rate at the time of writing is 64 bytes / cycle.

On the other hand, at the time of reading, the DIMM addresses 0 to 3 of the memory bank B0 and the DIMM addresses 4 to 7 of the memory bank B1 are read and combined and transmitted. Since the same contents are written to the same addresses in the memory banks B0 and B1 at the time of writing, the contents obtained by combining the DIMM addresses 0 to 3 of the memory bank B0 and the DIMM addresses 4 to 7 of the memory bank B1 are combined into the memory bank B0. The same contents as the DIMM addresses 0 to 7 and the DIMM addresses 0 to 7 of the memory bank B1.

If an error occurs in the result of reading from DIMM addresses 0 to 3 of memory bank B0 or the result of reading from DIMM addresses 4 to 7 of memory bank B1, the other memory bank, that is, DIMM addresses 0 to 3. Read and use DIMM addresses 4-7 of memory bank B0. FIG. 1 illustrates a case where both of the DIMM addresses 0 to 3 of the memory bank B0 and the DIMM addresses 4 to 7 of the memory bank B1 are in error, but the DIMM addresses 0 to 3 of the memory bank B0 and the memory addresses of the memory bank B1 If any one of the DIMM addresses 4 to 7 is an error, only the error may be read from the other memory bank.

Thus, by reading and combining data at different addresses from the memory banks B0 and B1, the transmission speed at the time of reading can be set to 128 bytes / cycle.

FIG. 2 is a schematic configuration diagram illustrating a schematic configuration of the computer apparatus according to the present embodiment. The computer apparatus 1 shown in FIG. 2 includes a system controller (SC) 13, an arithmetic processing unit (CPU: Central Processing Unit) 11, a memory control unit (MAC: Memory Access controller) 12, and an interface unit 14. The memory control device 12 is further connected to memory banks B0 and B1.

The arithmetic processing unit 11 is a device that executes various arithmetic processes. The arithmetic processing executed by the arithmetic processing unit 11 includes writing data to the memory banks B0 and B1, which are main storage devices, and reading data from the memory banks B0 and B1. The arithmetic processing unit 11 issues a physical address (PA) and designates an access destination when performing memory access to the memory banks B0 and B1.

The interface device 14 is a device for connecting to various devices (not shown) such as an auxiliary storage device and a network communication device. The system control device 13 is a bridge that connects the arithmetic processing device 11, the memory control device 12, and the interface device 14.

The memory bank B0 has two memory modules M01 and M02, and the memory bank B1 has two memory modules M11 and M12. Each of the memory modules M01, M02, M11, and M12 is a DIMM.

In addition, the memory control device 12 includes therein a write control unit 21 that controls writing to the memory banks B0 and B1, and a read control unit 22 that controls reading from the memory banks B0 and B1.

FIG. 3 is a configuration diagram illustrating the configuration of the write control unit 21. As shown in FIG. 3, the write control unit 21 includes an address conversion unit 21a and an error detection information generation unit 21b therein.

The address conversion unit 21a converts the physical address (PA) issued by the arithmetic processing unit 11 into DA that is an address in the DIMM. In this conversion, the address conversion unit 21a creates an address for the memory bank B0 and an address for the memory bank B1, respectively. The physical address PA is aligned in units of 64 bytes.

The error detection information generation unit 21b receives 64 bytes of data from the arithmetic processing unit 11 via the system control unit 13. The error detection information generation unit 21b divides the 64-byte data into four 16-byte data, and calculates an error check code (ECC) that is error detection information every 16 bytes. Then, the error detection information generation unit 21b transmits (data 16 bytes + error check code 2 bytes) × 4 data to the memory modules in the memory bank B0 and the memory bank B1.

FIG. 4 is a configuration diagram illustrating the configuration of the read control unit 22. As shown in FIG. 4, the read control unit 22 includes address conversion units 22a0 and 22a1, address selection units 22b0 and 22b1, reread confirmation units 22c0 and 22c1, data selection units 22d0 and 22d1, and a data transmission unit 22e.

The physical address PA issued when the arithmetic processing unit 11 issues a read request is aligned (aligned) in units of 128 bytes. The read control unit 22 reads the physical address of 128 bytes from the memory bank by dividing the physical address into the first half 64 bytes and the second half 64 bytes.

The address conversion unit 22a0 is a processing unit responsible for address conversion of the first half 64 bytes. When the physical read address for the first half 64 bytes of the physical address and the result of the normal read are unrecoverable errors Find the reread address to be used. Here, the address conversion unit 22a0 designates the address of the memory bank B0 as the normal read address, and designates the address of the memory bank B1 as the reread address. The address conversion unit 22a0 calculates the memory address DA by setting the value of the sixth bit of the physical address PA to “0”.

The address conversion unit 22a1 is a processing unit responsible for address conversion of the second half 64 bytes. When the second half 64 bytes of the physical address are a normal read address for normal reading and the result of the normal reading is an unrecoverable error. Find the reread address to be used. Here, the address conversion unit 22a1 designates the address of the memory bank B1 as the normal read address, and designates the address of the memory bank B0 as the reread address. Further, the address conversion unit 22a1 calculates the memory address DA by setting the value of the sixth bit of the physical address PA to “1”.

The address selection unit 22b0 is a processing unit that reads from the memory bank B0. First, when the memory address DA is sent from the address conversion units 22a0 and 22a1, the address selection unit 22b0 selects the normal read address sent from the address conversion unit 22a0 and reads from the memory module in the memory bank B0. . Thereafter, when there is a reread request from the reread confirmation unit 22c1, the reread address is selected and read again from the memory module in the memory bank B0.

The address selection unit 22b1 is a processing unit that reads from the memory bank B1. First, when the memory address DA is sent from the address conversion units 22a0 and 22a1, the address selection unit 22b1 selects the normal read address sent from the address conversion unit 22a1 and reads from the memory module in the memory bank B1. . Thereafter, when there is a reread request from the reread confirmation unit 22c0, the reread address is selected and read again from the memory module in the memory bank B0.

The read confirmation unit 22c0 is a reread determination unit that determines the necessity of rereading based on the result of the normal read of the first 64 bytes, and makes a reread request to the address selection unit 22b1 when rereading is necessary. From the memory module, a set of data and an error check code (data 16 bytes + error check code 2 bytes) is output four times. The reread confirmation unit 22c0 checks each error check code against the normal read data, and determines that rereading is necessary if there is an uncorrectable error (UE) in any one of the four. .

The read confirmation unit 22c1 is a reread determination unit that determines the necessity of rereading based on the result of the normal read of the second half 64 bytes and makes a reread request to the address selection unit 22b0 when rereading is necessary. From the memory module, a set of data and an error check code (data 16 bytes + error check code 2 bytes) is output four times. The reread confirmation unit 22c1 checks each error check code with respect to the normal read data, and determines that rereading is necessary if any one of the four errors (UE) cannot be corrected.

The data selection unit 22d0 checks the ECC of normal read data of 64 bytes in the first half, and if there is no error or a correctable error (CE), selects the normal read data. If there is no error, the data is corrected if it is CE, and the data is corrected and sent to the data sending unit 22e.

On the other hand, when there is an unrecoverable error in the normal read data, the data selection unit 22d0 checks the error check code of the data reread from the memory bank B1. As a result of this check, if the reread data is no error or CE, the reread data is selected. If there is no error, the data is corrected if it is CE, and the data is corrected and sent to the data sending unit 22e. If the reread data is also a UE, “Marked UE” is sent to the data sending unit 22e.

The data selection unit 22d1 checks the ECC of the normal read data of the latter half 64 bytes, and selects normal read data if there is no error or a correctable error (CE). If there is no error, the data is corrected if it is CE, and the data is corrected and sent to the data sending unit 22e.

On the other hand, if there is an unrecoverable error in the normal read data, the data selection unit 22d1 checks the error check code of the data reread from the memory bank B0. As a result of this check, if the reread data is no error or CE, the reread data is selected. If there is no error, the data is corrected if it is CE, and the data is corrected and sent to the data sending unit 22e. If the reread data is also a UE, “Marked UE” is sent to the data sending unit 22e.

The data transmission unit 22e combines the data of the first half 64 bytes sent from the data selection unit 22d1 with the data of the first half 64 bytes sent from the data selection unit 22d0, and outputs the data to the system controller 13 as 128 bytes data.

As described above, the designated 128-byte data is divided into the first half and the second half, and the data is read out from different memory banks and combined, whereby the data can be read out in 128 bytes.

Next, the operation of the memory control device 12 will be described with reference to FIGS. 5 to 15 in comparison with the non-mirror mode operation and the mirror mode operation in the conventional memory control.

FIG. 5 is an explanatory diagram for explaining a basic operation of a conventional memory control device (MAC). The physical address (PA) indicates a place to write / read when the arithmetic processing unit accesses the memory, and is 1 byte per address. The DIMM address (DA) corresponds to the address line of the DIMM. Since the data widths of the memory banks B0 and B1 are 16 bytes, the address of DA is 16 bytes of PA. Since the burst length is 4, the transfer amount per cycle of one memory bank is 16 × 4 = 64 bytes.

When the physical address of the data write destination and the contents of the data are sent from the system controller to the memory controller, the memory controller converts the physical address into a DIMM address, and the corresponding DIMM of the DIMM connected to the memory controller Write data to address. Two memory banks B0 and B1 are connected to one memory control device, and two DIMMs are connected to each of the memory banks B0 and B1.

The two memory banks B0 and B1 operate independently of each other, and can simultaneously perform operations such as writing to and reading from each connected DIMM. The data to be written to / read from the DIMM uses the error correction code of the data part 16 bytes + ECC part 2 bytes, and can correct a 1-bit error and detect a 2-bit error.

The operation mode of the memory control device includes the mirror mode and the non-mirror mode as described above. The non-mirror mode is a capacity and speed priority mode. FIG. 6 is an explanatory diagram for explaining the operation in the conventional non-mirror mode.

As shown in FIG. 6, in the non-mirror mode, by assigning different physical addresses to the two memory banks B0 and B1, and accessing the two memory banks B0 and B1 at the time of writing / reading, the memory bank A throughput twice as large as B0 and B1 is obtained.

Specifically, in address allocation, different physical addresses are allocated alternately by 64 bytes for memory bank B0 and memory bank B1. At the time of writing, data from the system control device is distributed to the memory banks B0 and B1. By operating the memory banks B0 and B1 simultaneously in parallel, the data transfer amount between the system control device and the memory control device per cycle is 64 × 2 = 128 bytes. Similarly, at the time of reading, the memory banks B0 and B1 are simultaneously operated in parallel to extract separate data, so that the data transfer amount between the system controller and the memory controller per cycle is 64 × 2 = 128 bytes. .

In the example shown in FIG. 6, PA0 to 63 are assigned to DA0 to DA3 of memory bank B0, and PA64 to 127 are assigned to DA0 to 3 of memory bank B1. Further, PA128 to 191 are assigned to DA4 to 7 of memory bank B0, and PA192 to 255 are assigned to DA4 to 7 of memory bank B1.

Therefore, when a write request specifying physical addresses PA0 to 127 is received from the system controller, PA0 to 63 are written to DA0 to 3 of memory bank B0, and PA64 to 127 are written to DA0 to 3 of memory bank B1. When a read request specifying physical addresses PA0 to 127 is received from the system controller, PA0 to 63 are read from DA0 to DA3 of memory bank B0, and PA64 to 127 are read from DA0 to DA3 of memory bank B1.

On the other hand, the mirror mode is a mode in which the reliability of data is improved instead at the expense of capacity and speed. FIG. 7 is an explanatory diagram for explaining the operation in the conventional mirror mode.

As shown in FIG. 7, in the mirror mode, the same physical address is assigned to the two memory banks B0 and B1, and the same data is written twice at the time of writing. At the time of reading, data of the same physical address is simultaneously read from the two memory banks B0 and B1, and ECC check and data compare are performed. By this ECC check and the data conveyor, even if an uncorrectable error occurs in one of the memory banks, the data is not damaged.

Specifically, in the address assignment, the same physical address is assigned to the memory bank B0 and the memory bank B1. At the time of writing, the data from the system control device is written twice in the memory banks B0 and B1. Therefore, the data transfer amount between the system control device and the memory control device per cycle is 64 bytes. Similarly, at the time of reading, data of the same physical address is simultaneously read from the memory banks B0 and B1, data to be transmitted is determined by ECC check and data compare, and sent to the system controller. Therefore, the data transfer amount between the system control device and the memory control device per cycle is 64 bytes.

In the example shown in FIG. 7, PA0 to 63 are assigned to DA0 to 3 of memory bank B0 and memory bank B1, and PA64 to 127 are assigned to DA4 to 7 of memory bank B0 and memory bank B1.

Therefore, when a write request specifying physical addresses PA0 to 63 is received from the system controller, PA0 to 63 are written to both DA0 to DA3 of memory bank B0 and DA0 to DA3 of memory bank B1. When a read request specifying physical addresses PA0 to 63 is received from the system controller, PA0 to 63 are read from both DA0 to DA3 of memory bank B0 and DA0 to DA3 of memory bank B1, and ECC check, Reliability is improved by performing data comparison.

FIG. 8 is an explanatory diagram for explaining the operation of improving the reliability in the conventional mirror mode. As shown in FIG. 8, if the data read from the memory bank B0 and the data read from the memory bank 1 are both error-free (ECC check OK) and the data comparison results match (data conveyor ○), the data can be obtained. It is assumed that the obtained data is normal.

If one of the data read from the memory bank B0 and the data read from the memory bank 1 is error-free (ECC check OK) and the other is a correctable error (CE), the error is corrected before the data If the data comparison results match (data conveyor ○), the obtained data is assumed to be normal.

Similarly, if both the data read from the memory bank B0 and the data read from the memory bank 1 are correctable errors (CE), the two data are compared after correcting both errors, and the data comparison results match. If (data conveyor ○), the obtained data is assumed to be normal.

One of the data read from the memory bank B0 and the data read from the memory bank 1 is an uncorrectable error (ECC check UE), and the other is no error (ECC check OK) or correctable error (CE). In this case, the data conveyor is not performed, and it is assumed that the data obtained without error (ECC check OK) or the data obtained by correcting the error is normal.

If both the data read from the memory bank B0 and the data read from the memory bank 1 are uncorrectable errors (ECC check UE), the data conveyor is not performed and normal data cannot be obtained by reading. “Marked UE” is output.

Even if the data read from the memory bank B0 and the data read from the memory bank 1 are both error-free (ECC check OK), the comparison result of the data does not match (data conveyor ×). "UE" is output.

Also, one of the data read from the memory bank B0 and the data read from the memory bank 1 is a correctable error (CE), and the other is no error (ECC check OK) or a correctable error (CE). Then, after correcting the error, the data are compared, and if the data comparison results do not match (data conveyor ×), “Marked UE” is output.

As a situation where a data compare error is caused by the reliability improvement operation in the conventional mirror mode, the most likely situation is that the data is erroneously 3 bits in either memory bank and becomes 1 bit error of another data. Is the case. However, even if the data is incorrect by 3 bits, it does not always result in a 1-bit error of another data, and the probability that the data becomes a 3-bit error is extremely small.

Therefore, in the memory control method according to the present embodiment, data of the same physical address is written to the memory banks B0 and B1 at the time of writing, and data of physical addresses different from each other are read at the memory banks B0 and B1 at the time of reading. If the read data is an error that cannot be corrected, the data of the same physical address is written somewhere in the other memory bank. Do. By doing so, even if the data read from one of the memory banks is an error that cannot be corrected, the data is not lost and normal data can be obtained. If an uncorrectable error does not occur, the transfer speed at the time of reading is the same as in the non-mirror mode.

FIG. 9 is an explanatory diagram for explaining the memory control operation according to the present embodiment. In the example shown in FIG. 9, first, in address allocation, the first half of the DIMM address is assigned different physical addresses by 64 bytes alternately in the memory bank B0 and the memory bank B1 as in the non-mirror mode. The second half of the DIMM address is assigned the same physical address as the first half of the paired memory bank.

FIG. 9 shows an example in which the capacity per memory bank is 1 KByte, where DA = 0 to 31 is the first half and DA = 32 to 63 is the second half.

And, in the first half, as in the non-mirror mode, PA0 to 63 are allocated to DA0 to DA3 of memory bank B0, and PA64 to 127 are allocated to DA0 to 3 of memory bank B1. Further, PA128 to 191 are assigned to DA4 to 7 of memory bank B0, and PA192 to 255 are assigned to DA4 to 7 of memory bank B1. This allocation is repeated until the first half end DA = 31.

In the second half of DA = 32 to 63, the same allocation as that of the first half of the memory bank B1 is performed for the memory bank B0, and the same allocation as that of the first half of the memory bank B0 is performed for the memory bank B1.

At the time of writing, the data from the system control device is written twice in the two memory banks B0 and B1. However, the DA for writing data is different between the memory bank B0 and the memory bank B1. For example, when there is a write request for the physical address PA = 0 to 63 from the system controller, write processing is performed on DA = 0 in the memory bank B0 and DA = 32 in the memory bank B1. Therefore, the data transfer amount between the system controller and the memory controller per cycle is 64 bytes, which is the same as in the conventional mirror mode.

At the time of reading, as in the conventional non-mirror mode, the memory bank to be read is changed every time the physical address PA is +64, and the memory banks B0 and B1 are operated in parallel at the same time. Retrieve the data. However, when an uncorrectable error (UE) is found by the ECC check, the same PA data is recorded in the latter half of the DIMM address of the other memory bank, and is read.

FIG. 10 is an explanatory diagram for explaining the reliability improving operation in the memory control according to the present embodiment. As shown in FIG. 10, when the ECC check result in the first read (normal read) indicates no error (OK), reread is not performed and the obtained data is used as normal data as it is. Similarly, when the ECC check result in the first read (normal read) is a correctable error (CE), reread is not performed and the obtained data is corrected to normal data.

On the other hand, if the ECC check result of the first lead is an uncorrectable error (UE), the lead is executed again (reread). When the reread ECC check result indicates no error (OK), the data obtained by the reread is set as normal data. Similarly, even when the ECC check result in reread is a correctable error (CE), the data obtained by reread is corrected to normal data. However, if the reread error also cannot be corrected, “Marked UE” is output.

Therefore, in the memory control according to the present embodiment, if an uncorrectable error (UE) does not occur in the read of the first half of the DA, the data transfer amount of one cycle between the system controller and the memory controller is the conventional non-mirror mode. It will be 128 bytes as well as the hour.

FIG. 11 is an explanatory diagram for explaining the address conversion when the address allocation shown in FIG. 9 is performed. As shown in FIG. 9, when the capacity per memory bank is 1 Kbyte, DA = 0 to 31 is the first half, and DA = 32 to 63 is the second half, the memory of the memory bank B0 from the physical address PA In the conversion to the address DA, the value of the fourth bit of PA becomes the value of the 0th bit of DA, and the value of the fifth bit of PA becomes the value of the first bit of DA. The 6th bit value of PA is the 5th bit value of DA, and the 7th to 9th bit values of PA are the 2nd to 4th bit values of DA, respectively.

On the other hand, in the conversion from the physical address PA to the memory address DA of the memory bank B1, the value of the fourth bit of PA becomes the value of the 0th bit of DA, and the value of the fifth bit of PA becomes the first bit of DA. Value. Then, the 6th bit value of PA is inverted to the 5th bit value of DA, and the 7th to 9th bit values of PA are set to the 2nd to 4th bit values of DA, respectively.

Note that the address assignment and the conversion from PA to DA can be implemented with appropriate modifications. FIG. 12 shows a first modification of address allocation, and FIG. 13 is an explanatory diagram for explaining address conversion when the address allocation shown in FIG. 12 is performed.

In the address assignment shown in FIG. 12, the memory bank B0 is the same as the mirror mode. That is, PA0 to 63 are assigned to DA0 to DA3, and PA64 to 127 are assigned to DA4 to DA7. Similarly, PAs 128 to 191 are assigned to DAs 8 to 11, and PAs 192 to 255 are assigned to DAs 12 to 15.

On the other hand, for memory bank B1, PAs 64 to 127 are assigned to DA0 to DA3, and PAs 0 to 63 are assigned to DA4 to 7. Similarly, PAs 192 to 255 are assigned to DAs 8 to 11, and PAs 128 to 191 are assigned to DAs 12 to 15.

In the address conversion in this case, as shown in FIG. 13, in the conversion from the physical address PA to the memory address DA of the memory bank B0, the value of the fourth bit of PA becomes the value of the 0th bit of DA, and The value of the fifth bit becomes the value of the first bit of DA. Similarly, the 6th to 9th bit values of PA are the 2nd to 5th bit values of DA, respectively.

On the other hand, in the conversion from the physical address PA to the memory address DA of the memory bank B1, the value of the fourth bit of PA becomes the value of the 0th bit of DA, and the value of the fifth bit of PA becomes the first bit of DA. Value. Then, the 6th bit value of PA is inverted to the 2nd bit value of DA, and the 7th to 9th bit values of PA are set to the 3rd to 5th bit values of DA, respectively.

And at the time of reading, first, the memory banks B0 and B1 read a portion where DA is a multiple of 8, and if it is UE, read the portion where DA is +4 in the other memory bank. That is, first, the portion surrounded by the solid line in FIG. 12 is read, and if the error cannot be corrected, the portion surrounded by the broken line is read. As a result, the transmission data at the time of reading is the same as the example shown in FIG.

FIG. 14 is a second modification of address allocation, and FIG. 15 is an explanatory diagram for explaining address conversion when the address allocation shown in FIG. 14 is performed.

The address assignment shown in FIG. 14 is the same as in the conventional mirror mode. PA0 to 63 are assigned to DA0 to DA3 of memory bank B0 and memory bank B1, and PA64 to DA4 to 7 of memory bank B0 and memory bank B1 are assigned. 127 is assigned. Similarly, PA128 to 191 are assigned to DA8 to 11 of memory bank B0 and memory bank B1, and PA192 to 255 are assigned to DA12 to 15 of memory bank B0 and memory bank B1.

As shown in FIG. 15, the address conversion in this case is the same in the memory bank B0 and the memory bank B1, the value of the fourth bit of the physical address PA becomes the value of the 0th bit of DA, and the PA 5 The value of the bit is the value of the first bit of DA. Similarly, the 6th to 9th bit values of PA are the 2nd to 5th bit values of DA, respectively.

When reading, the memory bank to be read is changed every time PA is +64 (DA is +4). If the read result is UE, the same DA location in the other memory bank is read. That is, first, the portion surrounded by the solid line in FIG. 14 is read, and if the error cannot be corrected, the portion surrounded by the broken line is read. As a result, the transmission data at the time of reading is the same as the example shown in FIG.

Next, the processing operation of the read control unit 22 will be described. FIG. 16 is a flowchart for explaining data read processing of the first 64 bytes. As shown in FIG. 16, first, the address conversion unit 22a0 obtains the DA for normal reading from the physical address PA aligned in 128 bytes using address conversion for the memory bank B0 (PA → DA conversion). Reread DA is obtained by using address conversion for B1 (PA → DA conversion). At this time, the sixth bit of PA is set to 0 (S101).

Next, the address selector 22b0 reads data from the normal read DA (S102), and sends the normal read data obtained by the read to the data selector 22d0 (S103).

The reread confirmation unit 22c0 checks the ECC of the normal read data (S104), and if there is no unrecoverable error (S104, no UE), the process is terminated as it is. However, if there is an uncorrectable error (S104, with UE), a reread request is transmitted to the address selection unit 22b1 (S105).

The address selection unit 22b1 that has received the reread request reads data from the reread DA (S106), sends the reread data obtained by the read to the data selection unit 22d0 (S107), and ends the processing.

FIG. 17 is a flowchart for explaining the data read process of the second half 64 bytes. As shown in FIG. 17, first, the address conversion unit 22a1 obtains the DA for normal reading from the physical address PA aligned in 128 bytes by using address conversion for the memory bank B1 (PA → DA conversion), and the memory bank Reread DA is obtained by using address conversion for B0 (PA → DA conversion). At this time, the sixth bit of PA is set to 1 (S201).

Next, the address selector 22b1 reads data from the normal read DA (S202), and sends the normal read data obtained by the read to the data selector 22d1 (S203).

The reread confirmation unit 22c1 checks the ECC of the normal read data (S204), and if there is no unrecoverable error (S204, no UE), the process is terminated as it is. However, if there is an uncorrectable error (S204, with UE), a reread request is transmitted to the address selection unit 22b0 (S205).

The address selection unit 22b0 that has received the reread request reads data from the reread DA (S206), sends the reread data obtained by the read to the data selection unit 22d1 (S207), and ends the processing.

FIG. 18 is a flowchart for explaining the processing operation of the data selection units 22d0 and 22d1. The data selectors 22d0 and 22d1 perform this process for each data 16 bytes. The data selection units 22d0 and 22d1 first check the ECC of the normal read data (S301). As a result, if there is no error (OK) or the error can be corrected even if there is an error (S301, OK or CE), the process proceeds to step S304. If it is CE (S304, Yes), the data is corrected (S305), and the data is sent to the data sending unit 22e (S306). If it is not CE and there is no error (S304, No), the data is sent as it is to the data sending unit 22e (S306).

On the other hand, when there is an error that cannot be repaired in the normal read data (S301, UE), the data selection units 22d0 and 22d1 check the ECC of the reread data (S302). As a result, if there is no error (OK) or if the error can be corrected (S302, OK or CE), the process proceeds to step S307. If it is CE (S307, Yes), data correction is performed (S308), and then the data is sent to the data sending unit 22e (S309). If it is not CE and there is no error (S307, No), the data is sent as it is to the data sending unit 22e (S309).

If the reread data also has an error that cannot be repaired (S303, UE), the data selection units 22d0 and 22d1 send “Marked UE” to the data transmission unit 22e (S303).

As described above, in the memory control device according to the present embodiment, the data of the same physical address is written to the memory banks B0 and B1 at the time of writing, and the data of different physical addresses are read at the memory banks B0 and B1 at the time of reading. To. If the read data is an error that cannot be corrected, the data of the same physical address is written somewhere in the other memory bank. Do. By doing so, even if the data read from one of the memory banks is an error that cannot be corrected, the data is not lost and normal data can be obtained. In addition, if the uncorrectable error does not occur, the transfer speed at the time of reading is the same as that in the non-mirror mode, so that the memory control device having the same reliability as the mirror mode and the same transmission speed as the non-mirror mode A memory control method can be obtained.

Claims (8)

In the memory control device connected to the control device and the first and second memory banks, each of which is a set of a plurality of memory modules, and controlling memory access from the control device to the first and second memory banks,
The first read physical address for reading from the control device to the first memory bank is any of the first memory modules belonging to the first memory bank when normal reading is performed. Is converted to a first read memory module address that identifies the memory module, and when re-reading occurs, the same data as the first memory module is held and the second memory bank belonging to the second memory bank is retained. A first read address conversion unit that converts any of the memory modules belonging to the set of two memory modules into a second read memory module address;
A second read physical address for reading from the control device to the second memory bank is specified, and any memory module belonging to the set of the second memory modules is specified when normal read is performed. The address is converted to a third read memory module address, and when reread occurs, the same data as the third memory module is held, and any one of the memory modules belonging to the set of the first memory modules is stored. A second read address conversion unit for converting to a specified fourth read memory module address;
Of the first memory module address and the fourth memory module address, when a first reload request is input, the fourth memory module address is selected, or the first memory module address is selected. A first read address selection unit that selects the first memory module address and outputs it to the first memory bank if a read request is not input;
Of the second memory module address and the third memory module address, when a second reload request is input, the third memory module address is selected, or the second memory module address is selected. 2. A memory control apparatus comprising: a second read address selection unit that selects the second memory module address and outputs the second memory module address to the second memory bank when a read request is not input. The memory control device further includes:
First read data and first error detection output from one of the memory modules belonging to the set of the first memory modules specified by the first memory module address output by the first read address selection unit Based on the information, when a reread request for the first read data in which an error has occurred is necessary, a first reread determination unit that outputs the second reread request;
Second read data and second error detection output from one of the memory modules belonging to the set of second memory modules specified by the second memory module address output from the second read address selection unit A second re-reading determination unit for outputting the first re-reading request when a re-reading request of the second read data in which an error has occurred is necessary based on the information;
Select either the first read data or the second read data held by any one of the memory modules belonging to the set of the second memory modules specified by the second memory module address A first read data selection unit to output;
Select either the third read data or the fourth read data held by any one of the memory modules belonging to the set of the first memory modules specified by the first memory module address 2. The memory control device according to claim 1, further comprising a second read data selection unit for outputting. The memory control device further includes:
Either the first read data or the second read data selected by the first read data selection unit, and the third read data or the fourth read data selected by the second read data selection unit. 3. The memory control device according to claim 2, further comprising a read data transmission unit that outputs any of the read data to the control device as continuous read data by merging any of the read data. The memory control device further includes:
A first write physical address for writing first write data from the control device to the first memory bank is specified, and a first memory module belonging to the first memory bank is specified. A write memory module address is converted and output to the first memory bank, and second write data is written from the control device to the second memory module belonging to the second memory bank. A write address conversion unit that converts a write physical address of 2 into a second write memory module address that identifies the second memory module belonging to the second memory bank and outputs the second write memory module address to the second memory bank; ,
An error detection information generation unit that generates and adds the first error detection information and the second error detection information to the first write data and the second write data, respectively. The memory control device according to any one of claims 1 to 3. The memory control device further includes:
The first write data is written to any one of the memory modules belonging to the first set of memory modules, and the first write data is also written to any memory module belonging to the second set of memory modules. Write, and further write the second write data to any memory module belonging to the first set of memory modules, and write the second write data to any one of the second set of memory modules. 5. The memory control device according to claim 4, wherein the data is written in the memory module. The control device is connected to an arithmetic processing device, and the arithmetic processing device sends the first read physical address, the second read physical address, the first write physical address, and the second to the control device. The controller issues the first physical address, the second physical address, the first physical address, and the second physical address issued by the arithmetic processing unit. 4. The memory control device according to claim 1, wherein the memory control device is used to perform memory access to the first and second memory banks. A memory of a memory control device connected to the control device and first and second memory banks, each of which is a set of a plurality of memory modules, and controlling memory access from the control device to the first and second memory banks. A control method,
A write step of writing data of the same content to both the first memory bank and the second memory bank when a write request is received from the control device;
When a read request is received from the control device, one of the first memory bank and the second memory bank is set to the first half data normal read destination and the other half of the first half of the data designated by the read request. A first half data read control step of designating a memory bank as a first half data preliminary read destination;
When normal data is obtained as a result of reading from the first half data normal read destination, the data is selected as the first half read data, and there is an unrecoverable error in the result of reading from the first half data normal read destination. A first half read data selection step of selecting data read from the first half data preliminary read destination as the first half read data when present,
When a read request is received from the control device, either the second memory bank or the first memory bank of the second half of the data designated by the read request is transferred to the second half data normal read destination, the other A second half data read control step for designating a memory bank as a second half data preliminary read destination;
When normal data is obtained as a result of reading from the latter half data normal read destination, the data is selected as the latter half read data, and an unrecoverable error is found in the result of reading from the latter half data normal read destination. A memory control method comprising a second half read data selection step of selecting data read from the second half data preliminary read destination as second half read data, if present. The memory control method further includes:
8. The memory control method according to claim 7, further comprising a read data transmission step of combining the first half read data and the second half read data and transmitting the combined data to the control device.

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