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WO2010009584A1 - Système et procédé d'affectation d'adresse intelligente basée sur un bus série - Google Patents

Système et procédé d'affectation d'adresse intelligente basée sur un bus série Download PDF

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Publication number
WO2010009584A1
WO2010009584A1 PCT/CN2008/001814 CN2008001814W WO2010009584A1 WO 2010009584 A1 WO2010009584 A1 WO 2010009584A1 CN 2008001814 W CN2008001814 W CN 2008001814W WO 2010009584 A1 WO2010009584 A1 WO 2010009584A1
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WIPO (PCT)
Prior art keywords
slave
host
address
command
accordance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2008/001814
Other languages
English (en)
Inventor
Xi Luo
Hongchen Xu
Yunfeng Zhang
Lei Shi
Zhifeng Zhang
Yuanhui Liu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Johnson Controls Building Efficiency Technology Wuxi Co Ltd
Johnson Controls Technology Co
Original Assignee
Johnson Controls Building Efficiency Technology Wuxi Co Ltd
Johnson Controls Technology Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Johnson Controls Building Efficiency Technology Wuxi Co Ltd, Johnson Controls Technology Co filed Critical Johnson Controls Building Efficiency Technology Wuxi Co Ltd
Publication of WO2010009584A1 publication Critical patent/WO2010009584A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40019—Details regarding a bus master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L61/00—Network arrangements, protocols or services for addressing or naming
    • H04L61/50—Address allocation
    • H04L61/5038—Address allocation for local use, e.g. in LAN or USB networks, or in a controller area network [CAN]

Definitions

  • the invention generally relates to smart address assignment, and more particularly, to a method and system of smart address assignment based on a serial bus under the master-slave communication mode
  • a serial bus is widely used in the industrial control field When a s ⁇ nal bus is used, all devices on the bus share communication media, and the communication information sent by any device can be received by other devices on the bus In order to identify the devices which send or receive the information, it is necessary to assign one communication address to each device Generally, a bus has two types of operation modes, i e master-slave mode and "alternate master- alternate slave" mode The latter does not perform well when there are a large number of nodes, therefore, the communication network architecture of "single master, mulu slaves" is used in the most conditions in the industrial control Under the master-slave mode, lhe whole communication bus system is composed of one master node and several slave nodes, wherein the master node continuously checks whether the slave nodes have communication request in turn If the slave nodes have communication request, then the bus control nght is given to a slave node, and the slave node surrenders the bus control nght when it finishes sending communication Only when the host determines the address of the slave
  • a host is connected to a plurality of slaves, and the location of each slave is unfixed and slaves are separated by a long distance. Accordingly it is very likely to set repeated addresses by manually setting the device addresses.
  • many hosts are closed hosts, therefore only when the housing of the machine is opened, can simple settings be done. If the users maintain the salves or newly add slave devices, it tends to cause some unexpected malfunctions.
  • Fig. Ia which shows a network architecture of RS485 bus in the prior art
  • the network is comprised of one host and three slaves 1, 2, 3.
  • Figs Ib and Ic illustrate the structural views of the host and the slave in the prior art respectively.
  • the host in the prior art includes an MCU microcontroller, a communication module, a memory and a DIP input device.
  • the communication module is connected to twisted pair lines, and connected to the MCU microcontroller. Under the control of the MCU microcontroller, the communication module executes the normal sending and receiving functions.
  • the MCU microcontroller is connected to the communication module and memory respectively.
  • the memory is used to store each inputted salve address, and provides it to the MCU microcontroller for retrieval.
  • the DIP input switch is used to input each set slave address to the memory " . It is necessary to manually input the set address of each slave into the host of the prior art, therefore, it is necessary to pro ⁇ de an input device, i.e. DIP input switch, for correctly inputting the set slave address to the memory.
  • the slave of the prior art includes an MCU microcontroller, a communication module, a memory and a DIP input device. It is necessary to manually input the set address of each slave of the prior art, therefore, it is necessary to provide an input device, i.e. DIP input switch.
  • the device addresses are not allowed to be duplicate, and the device address on the bus is unique.
  • the manual setting process if a user inadvertently sets the addresses of two slaves, e.g. slave 1 and salve 3, as OxOl, then, according to the bus character, if the host sends a command to the slaves of address 0x01, slaves 1 and 3 each will receive the instruction, and answer the host, so that two slaves sending messages at the same time in the network will cause the communication failure at all the terminals, i.e. cause bus conflict, and hence the whole system cannot operate.
  • There is an urgent need for automatic address assignment under the master-slave communication mode in the application For example, if some slave stations are added to an existing system, the problem of duplicate addresses may occur; similarly, when a damaged slave station is replaced, it is also possible to cause the problem that the addresses are duplicate.
  • an address assignment method in a serial bus system including at least one host and at least one slave, the method including the following steps: a, providing an electronic physical switch for each of the at least one slave in a serial bus, to control the line connection/disconnection between each said slave and its next slave adjacent thereto; b, disconnecting the electronic physical switch of each of the at least one slaves ; c, after the host assigns an address to the slave which is to be assigned an address and which is the most adjacent to the host, close the electronic physical switch of the said slave.
  • step c is repeated, until the address assignment is completed for all of the slaves.
  • the host sends an initialization command to the slaves, to disconnect the electronic physical switches.
  • the method also includes the following step: the host sends an address checking command to the slaves, and the slave with an address that matches the address to be checked in the address checking command sends an acknowledgement response to the host.
  • the address assignment method further includes step d: the host regularly sends polling command to the slaves, the polling command includes the address of each slave. More preferably, the polling command also includes an address of an original value.
  • the address assignment method further includes: e. add at least one additional slave in the serial bus system; f. initialize the additional slave, to disconnect the electronic physical switch of the additional slave, and set the address of the additional slave as the original value; g. the additional slave with an address that matches the address which is the original value in the polling command sends the acknowledgement response to the host, store the said address, and close the electronic physical switch of the said additional slave. More preferably, step g is repeated, until the address assignment is completed for all of the additional slaves.
  • the address assignment method further includes the step of determining whether the effectively-assigned address is less than the number of the slaves.
  • the original value of the slave address is OxFF.
  • the electronic physical switch is a relay. According to another aspect of the invention, it provides a host for a serial bus system.
  • the serial bus system also includes at least one slave and the host includes: a controller; a communication module connected to the controller, for sending data to the at least one slave and receiving data from the at least one slave; a memory connected to the controller, for accessing the address data of the at least one slave; and an initialization switch connected to the controller, for starting the initialization operation when the initialization switch is activated.
  • the controller includes: an initialization command unit, for sending an initialization command to the at least one slave when the initialization switch is activated; and an address assignment command sending unit, for sending an address assignment command to the at least one slave.
  • the controller also includes a polling module, for regularly sending a polling command to the at least one slave, wherein the polling command includes the address of the at least one slave. More preferably, the polling command also includes an address of an original value.
  • the controller also includes an exception processing module, for invoking the address assignment command unit to send the address assignment command to the additional slave when the polling module finds that an additional slave is added.
  • an exception processing module for invoking the address assignment command unit to send the address assignment command to the additional slave when the polling module finds that an additional slave is added.
  • the controller also includes an address checking command sending unit, for sending an address checking command to the at least one slave.
  • the communication module is a RS485 communication module.
  • the memory is a nonvolatile memory.
  • the initialization switch is a JP jumper switch or a trigger key switch.
  • it provides a slave for a serial bus system.
  • the serial bus system also includes at least one host, the slave including: a controller; a communication module connected to the controller, for sending data to the at least one host and receiving data from the at least one host; a memory connected to the controller, for accessing the address data of the slave; an electronic physical switch connected in the serial bus and located downstream of the communication module; and an initialization switch connected to the controller, for starting the initialization operation when the initialization switch is activated.
  • the slave including: a controller; a communication module connected to the controller, for sending data to the at least one host and receiving data from the at least one host; a memory connected to the controller, for accessing the address data of the slave; an electronic physical switch connected in the serial bus and located downstream of the communication module; and an initialization switch connected to the controller, for starting the initialization operation when the initialization switch is activated.
  • the controller includes: an initialization command executing unit, for disconnecting the electronic physical switch and setting its own address as an original value, when the initialization switch is activated or after receiving the initialization command sent by the at least one host; an address assignment command sending unit, for using the address in the address assignment command to replace the address before the assignment and making a response, when it receives an address assignment command sent by the at least one host, and at the same time closing the electronic physical switch.
  • an initialization command executing unit for disconnecting the electronic physical switch and setting its own address as an original value, when the initialization switch is activated or after receiving the initialization command sent by the at least one host
  • an address assignment command sending unit for using the address in the address assignment command to replace the address before the assignment and making a response, when it receives an address assignment command sent by the at least one host, and at the same time closing the electronic physical switch.
  • the controller also includes an address checking command answering unit, for making a response after receiving an address checking command sent by the at least one host.
  • the communication module is a R.S485 communication module.
  • the memory is a nonvolatile memory.
  • the initialization switch is a JP jumper switch or a trigger key switch.
  • the electronic physical switch is a relay.
  • the system includes: at least one host; at least one slave; a serial bus including pair lines; wherein each of the at least one slave includes an electronic physical switch, and wherein the pair lines in the serial bus are lead from the host, and in turn pass the electronic physical switch of each of the at least one slave.
  • each of the at least one host includes: a host controller; a host communication module connected to the host controller, for sending data to the at least one slave and receiving data from the at least one slave; a host memory connected to the host controller, for accessing the address data of the at least one slave; and a host initialization switch connected to the host controller, for starting the initialization operation when the host initialization switch is activated.
  • the host controller includes: an initialization command unit, for sending an initialization command to the at least one slave when the host initialization switch is activated; and a host address assignment command sending unit, for sending an address assignment command to the at least one slave.
  • the host controller also includes a polling module, for regularly sending a polling command to the at least one slave, wherein the polling command includes the address of the at least one slave. More preferably, the polling command also includes an address of an original value.
  • the host controller also includes an exception processing module, for invoking the address assignment command unit to send the address assignment command to the additional slave when the polling module finds that an additional slave is added.
  • an exception processing module for invoking the address assignment command unit to send the address assignment command to the additional slave when the polling module finds that an additional slave is added.
  • the host controller also includes an address checking command sending unit, for sending an address checking command to the at least one slave.
  • the host communication module is a RS485 communication module.
  • the host memory is a nonvolatile memory.
  • the host initialization switch is a JP jumper switch or a trigger key switch.
  • each of the at least one slave includes: a slave controller; a slave communication module connected to the slave controller, for sending data to the at least one host and receiving data from the at least one host; a slave memory connected to the slave controller, for accessing the address data of the at least one slave; an electronic physical switch connected in the serial bus and located downstream of the slave communication module; and a slave initialization switch connected to the slave controller, for starling the initialization operation when the slave initialization switch is activated.
  • the slave controller includes: an initialization command executing unit, for disconnecting the electronic physical switch and setting its own address as an original value, when the slave initialization switch is activated or after the initialization command sent by the at least one host is received; a slave address assignment command sending unit, for using the address in the address assignment command to replace the address before the assignment and making a response, when it receives an address assignment command sent by the at least one host, and at the same time close the electronic physical switch.
  • an initialization command executing unit for disconnecting the electronic physical switch and setting its own address as an original value, when the slave initialization switch is activated or after the initialization command sent by the at least one host is received
  • a slave address assignment command sending unit for using the address in the address assignment command to replace the address before the assignment and making a response, when it receives an address assignment command sent by the at least one host, and at the same time close the electronic physical switch.
  • the controller also includes an address checking command answering unit, for making a response after receiving an address checking command sent by the at least one host.
  • the slave communication module is a RS485 communication module.
  • the slave memory is a nonvolatile memory.
  • the slave initialization switch is a JP jumper switch or a trigger key switch.
  • the electronic physical switch is a relay.
  • the host when adding a new slave to the system, just activate the initialization key on the slave, the host will execute the address assignment of the newly-inserted slave without affecting the communication of other slaves.
  • the invention can realize automatic address assignment in serial bus systems, so as to avoid the problems of high error rate and low efficiency during manual setting process.
  • Fig. Ia is a network architecture of RS485 bus in the prior art
  • Fig. Ib is a structure scheme of a host hi the prior art
  • Fig. Ic is a structure scheme of of a slave in the prior art
  • Fig 2 is a network architecture of a smart address assignment system according to an embodiment of the invention.
  • Fig 3 is a structure scheme of a host according to an embodiment of the invention
  • Fig 4 is a structure scheme of slave according to an embodiment of the invention
  • Fig 5 is a flow-chart of a smart address assignment method according to one embodiment of the invention
  • Fig 6 is a flow-chart of a smart address assignment method according to another embodiment of the invention.
  • Fig 7 is a flow-chart of a smart address assignment method according to yet another embodiment of the invention.
  • Fig 8 is a flow-chart showing the initialization process of a slave according to one embodiment of the invention.
  • RS485 bus As an example.
  • the invention is not limited to RS485 bus, but it may be advantageous to use other buses, e.g. RS 422 bus.
  • Fig 2 is a network architecture of a smart address assignment system according to an embodiment of the invention.
  • the system includes a host 100, a plurality of slaves 200 , and RS485 bus 300, wherein host 100 is the commands starter , slaves 200 are the receiver and executor of the commands, and the host 100 and the slaves 200 are connected through RS485 bus to realize the sending and receiving of instructions.
  • Each slave 200 is set with an electronic physical switch 205.
  • the twisted pair lines of RS485 bus are lead out from the host 100, the twisted pair lines are firstly lead into the input terminal of the electronic physical switch of the first slave, then lead to the input terminal of the electronic physical switch of the second slave from the output terminal of the electronic physical switch of the first slave, and on the analogy of this operation, the network is build up.
  • Fig 3 shows a structure scheme of host 100 according to an embodiment of the invention, wherein host 100 includes a host controller 101 (e.g. host MCU microcontroller), a host communication module 102, a host memory 103, and a host initialization switch 104.
  • host controller 101 e.g. host MCU microcontroller
  • the host communication module 102 is connected to the host MCU microcontroller 101 and the twisted pair lines respectively, and executes normal sending and receiving functions under the control of the host MCU microcontroller 101;
  • the host MCU microcontroller 101 is connected to the host communication module 102 and the host memory 103 respectively, so as to implement initialization actions, automatically assign each slave address, store the assigned slave addresses, and regularly poll the slaves, and when it is found that a new slave is connected in, read the assigned slave address in the host memory 103, automatically increase it sequentially to create a new address, and assign it to the newly-connected slave;
  • the host memory 103 is used to automatically store the addresses which are assigned to the corresponding slaves by the host 100, and provide them to the host MCU microcontroller 101 for retrieval;
  • the host initialization switch 104 is connected to the host MCU microcontroller 101, so as to start initialization actions after it is pressed.
  • the initialization actions include: setting all the slave addresses with a predetermined value, such as OxFF, assigning addresses to all slaves in the network, and recording and storing them into the host memory 103.
  • the host initialization switch 104 is a JP jumper switch or trigger key switch
  • the host memory 103 is a flash memory.
  • the host initialization switch 104 is not limited to the switch described above, which may be a toggle switch or any other suitable switch.
  • the host memory 103 is also not limited to abovementioned memory, which may be any other suitable memory.
  • the host memory is preferably a nonvolatile memory, including but not limited to, floppy disk, Random-access memory (RAM), Read-only memory (ROM), Erasable Programmable Read-Qnly Memory (EPROM or flash memory), etc.
  • the host controller 101 is also not limited to MCU microcontroller, which may be any suitable controller.
  • the host controller 101 may be also connected to an alarm device (not shown) for giving off voice and/or light alarm during communication failure.
  • the host controller may include the following functional modules: an initialization command unit, for sending an initialization command to the slave after the initialization switch is pressed; and an address assignment command sending unit, for sending an address assignment command to the slave.
  • the host controller may also include a polling module, for regularly sending a polling command to the slave.
  • the host controller may also include an exception processing module, for invoking the address assignment command unit to send the address assignment command to the additional slave when the polling module finds that an additional slave is added.
  • the host controller may also include an address checking command sending unit, for sending an address checking command to the slave.
  • Fig 4 is a structure scheme of slave 200 according to an embodiment of the invention.
  • slave 200 includes a slave controller 201, such as MCU microcontroller, a slave communication module 202, a slave memory 203, an electronic physical switch 205, and a slave initialization switch 204.
  • the electronic physical switch 205 is a relay (normally closed, in order not to affect the communication of other slaves when this slave is switched off or malfunctioned, which is equivalent to the case where this slave is not connected on the bus), and the slave initialization switch is a JP jumper switch.
  • the electronic physical switch 205 and the slave initialization switch 204 are not limited to the abovementioned types, but may be any other suitable types.
  • the slave controller 201 is not limited to MCU microcontroller, but may be any other suitable controller.
  • the slave communication module 202 is connected to the slave MCU microcontroller 202 and the twisted pair lines respectively, and the twisted pair lines are lead out after passing through the relay 205;
  • the slave memory 203 is used to store the assigned address of slave 200;
  • the relay 205 executes connection/disconnection under the control of the slave MCU microcontroller 201, and is closed in the default state, so as not to affect the normal communication of other devices when starting or initialization can not be executed due to the faults that occur at the slave nodes;
  • the slave initialization switch 204 is a JP jumper, for initializing the address based on the control of the slave MCU microcontroller 201, for example, it may be necessary to initialize the address as factory default setting after the device is repaired.
  • the slave controller can include the following functional modules: an initialization command executing unit, for disconnecting the electronic physical switch and setting its own address as an original value, after the initialization switch is activated or after the initialization command sent by the host is received; an address assignment command sending unit, for using the address in the address assignment command to replace the address before the assignment. and making a response when it receives an address assignment command sent by the host, and at the same time closing the electronic physical switch.
  • the slave controller may also include an address checking command answering unit, for making a response after receiving an address checking command sent by the host.
  • Fig.5 is a flowchart of a smart address assignment method according to one embodiment of the invention.
  • the system operation is started from step 502, and at this time, both the host and the slaves are powered up.
  • the host initialization switch 104 is pressed, and the initialization command units of the host controller 101 of the host 100 sends the initialization commands to slaves 200, so that the initialization command executing units of the slave controllers of all slaves 200 take action to disconnect the relays 205, and all of the slave addresses are set with a predetermined value, such as Oxff.
  • the initialization command is sent consecutively for 20 times, to assure that the slaves have received them.
  • step 506 the address assignment command unit of the host controller 101 of the host 100 sends effectively-assigned addresses to slaves 200, and the address assignment command sending units of the slave controllers of the slaves 200 which have not been assigned the addresses, after receiving the addresses, use the assigned addresses to replace Oxff, close the relay, and make a responses. If there is a response, then the operation proceeds to step 508, i.e. waiting for the answer of slaves or until a predetermined waiting time, such as 100 ms. If there is a response, then the effectively-assigned address is increased according to a predetermined sequence, e.g. increased by 1 and the operation proceeds to step 506 again.
  • a predetermined sequence e.g. increased by 1
  • step 506 the address assignment command sending unit of the slave controller of another slave which is the nearest to the said slave, after receiving the address assignment command, stores the address, closes its relay 205 and makes a response. If there is no answer after step 506 has been entered for a plurality of times (such as 10 times), then it is considered that the addresses have been assigned to all of the slaves, and subsequently the operation proceeds to step 510, wherein automatic address assignment is completely finished.
  • Fig 6 is a flowchart of a smart address assignment method according to another embodiment of the invention.
  • the system operation is started from step 602, and at this time, both the host and the slaves are powered up.
  • the host 100 in the system determines whether the system initialization is necessary by checking the host initialization switch 104 (jumper switch state or key switch state). For example, the system automatically sets that, when the host initialization switch is 1, it is needed to perform initialization, and when the host initialization switch is 0, it is not necessary to perform initialization.
  • the host initialization switch 104 jumper switch state or key switch state
  • the initialization command unit of the host controller 101 of host 100 consecutively sends address assignment group-sending commands to slaves 200 for many times, so that the initialization command executing units of the slave controller of all slaves 200 take action to disconnect the relay 205, and the slave addresses are set with a predetermined value, such as Oxff.
  • the host 100 consecutively sends the commands for 20 times, to assure that the slaves receive them.
  • step 606 the system enters step 606 and at this time the system reads the list of assigned slave addresses from the designated memory area, and subsequently enters step 608, wherein it enters the normal communication program, and polls the slaves. It should be understood that the system may also has the opposite settings.
  • step 612 since the original bus is physically disconnected, but there is always one node which is uniquely connected to the host (the nearest node), the address checking command sending unit of the host controller 101 of the host 100 sends address checking command to the nearest slave 200, wherein the carried target address is Oxff, and the address checking command answering unit of the slave controller of the slave whose address is Oxff makes a response after receiving the command, and if the host does not receive the answer of the slave after a predetermined time (such as 30s), an alarm is triggered. Otherwise the system enters step 614, and waits for the answer of the slave or waits for a predetermined time, such as 100ms.
  • a predetermined time such as 100ms.
  • step 614 If the slave makes a response in step 614, then the system enters step 616, and the system sends the effective slave addresses to be assigned. Otherwise, the system returns to step 612.
  • step 618 the address assignment command sending unit of the host controller 101 of the host sends the effectively-assigned address to the slaves, which carry the formally-assigned address, and the addresses to be assigned which the address assignment command sending unit of the slave controller of the slave 200 receives, and uses the formally-assigned address to replace Oxf ⁇ closes its relay 205 and makes a response. If there is a response, the effectively-assigned addresses is increased according to a predetermined sequence (e.g.
  • step 616 again, and at this time, previous slave which has been assigned an address also receives the assigned address that the host sends to the slave. However, since it finds that the address does not match its assigned address, the slave would not make a response. But the address assignment command sending unit of the slave controller of another slave which is the nearest to this slave, after receiving the address assignment command, stores the address, closes the relay 205 and makes a response. If there is no response after step 618 has been entered for a plurality of times (such as 10 times), then it is considered that the addresses have been assigned to all of the slaves, and subsequently the process enters step 620 wherein the system address assignment ends, the largest assigned address of the slaves is stored and the success of automatic assignment is suggested.
  • Fig 7 is a flowchart of a smart address assignment method according to another embodiment of the invention.
  • the system operation starts from step 702, and at this time, both the host and the slaves are powered up.
  • the host 100 in the system determines whether the system initialization is necessary by checking the host initialization switch 104 (jumper switch state or key switch state). For example, the system automatically sets that, when the host initialization switch is 1, it is needed to perform initialization, and when the host initialization switch is 0, it is unnecessary to perform initialization. In other words, if the host initialization switch is 1, then the system enters step 710, and at this time, the system starts to read the total number of the slaves.
  • the host initialization switch 104 jumper switch state or key switch state
  • step 706 the system enters step 706, and at this time the system reads the list of the assigned slave addresses from the designated memory area, and subsequently enters steps 708, wherein it enters the normal communication program, and polls the slaves. It should be understood that, the system may also have the opposite settings.
  • step 712 the initialization command unit of the host controller 101 of the host 100 consecutively sends address assignment group-sending commands to slaves 200 for many times so that the initialization command executing units of the slave controllers of all slaves 200 take action to disconnect the relays 205, and the slave addresses are set as Oxff. In one embodiment, host 100 consecutively sends the commands for 20 times, to assure that the slaves receive them.
  • step 714 since the original bus is physically disconnected, but there is always one node which is uniquely connected to the host (the nearest node), therefore the address checking command sending unit of the host controller 101 of the host 100 sends address checking command to the nearest slave 200, wherein the carried target address is Oxff, and the address assignment command sending unit of the slave controllers of the slave whose address is Oxff makes a response after receiving the command, and if the host does not receive the answer of the slave after a predetermined time (e.g. 30s), an alarm will be triggered, otherwise the process enters step 716, and waits for the answer of the slave or waits for a predetermined time, such as 100ms.
  • a predetermined time e.g. 30s
  • step 718 the address assignment command sending unit of the host controller 101 of the host sends the effective slave address to be assigned to the slaves, wherein the effective slave address carries formally-assigned address, and the address assignment command sending unit of the slave controller of slaves 200 which have not been assigned addresses, after receiving the addresses, uses the formally-assigned address to replace Oxff and closes its relay 205 and makes a response.
  • step 720 the system waits for the answer of the slave or for 100 ms again. If there is no response, then the system will return to step 716, otherwise the system will enter step 722.
  • step 722 the system determines whether "effectively-assigned address ⁇ SlaveNum>" is valid. If it is valid, the effectively-assigned address will be added by 1, and the system will enter step 720 again, otherwise, the system will enter step 724 wherein the system address assignment ends, the largest assigned address of the slaves is stored and the success of automatic assignment is suggested.
  • Fig 8 is a flowchart showing the initialization process of a slave according to one embodiment of the invention.
  • the slave 200 is powered up.
  • slaves 200 determines whether the system initialization is necessary by checking the slave initialization switch 204. For example, the system automatically sets that, when the slave initialization switch is 1, it is needed to perform initialization, and when the slave initialization switch is 0, it is unnecessary to perform initialization.
  • step 610 the system enters step 610, and at this time the initialization command executing units of the slave controllers of the slaves set their memories 203 as factory " default setting value, such as Oxff, and the relay 205 is disconnected, to wait for the assigned address. If the slave initialization switch is 0, then the system enters step 806, and determines whether the address has been assigned, and subsequently enters step 808 and turns to the normal communication mode. It should be understood that, the system may also has the opposite settings. ⁇ /hen a new slave 200 is to be inserted in the original network, it is just needed to activate the sla ⁇ e initialization switch 204, and resume the default setting Oxff.
  • the slave would wait for an address assignment command, disconnect the switch of its relay 205, and then be directly inserted to the newly connected network and the host initialization switch 104 is pressed again, so that the smart address assignment of all slaves can be automatically completed all over again.
  • an address can be assigned to the newly-inserted slave, without having the host initialization switch 104 pressed again.
  • the polling module of the host controller of the host can be set such that Oxff device searching command is added to the command sent during polling.
  • the host can also be set such that it separately sends a command to inquire the OxFF address when the bus is idle after the ending of all normal communications.
  • the period of the normal communication is different according to different system conditions, for example, the period may be 10s. Both of the above methods can be used to assign addresses to the newly-inserted slaves.
  • the invention will be described by taking the example wherein OxFF device searching command is added to the command sent by the host during regular polling. Firstly, the initialization switch of the new slave is activated, and the default setting Oxff is resumed. During polling of the host, the polling module of the host controller would receive a response once it sends OxFF device searching command, which means that a new slave has been inserted. Subsequently, the exception processing module of the host controller of the host invokes the address assignment command unit to assign an address to the new slave, until the assignment for all new slaves is completed.
  • the host on the basis of the assigned address number, increases the address number sequentially, and assigns them to the newly-added slaves.
  • the aforementioned polling command sent by the host may be sent regularly, wherein carried target addresses are respectively the addresses of the slaves, and also include one Oxff address.
  • the invention is further described in combination with a communication protocol stack, wherein the data frame format is comprised of 23 bytes.
  • the specific data frame format is described as follows:
  • each byte respectively represents: STX: 0x02. This value is just an example value, and it should be understood that, it may be other values;
  • CMD data format type
  • Dest Addr destination address of data sending
  • Source Addr source address of data sending
  • DATA 16-byte sending data
  • ETX 0x03. This value is just an example value, and it should be understood that, it may be other values.
  • one host and three slaves I 3 2 and 3 constitute one control network, and is taken as an example embodiment.
  • the addresses which the host assigns to the slaves start from 0x01.
  • the normal state of the relay in each slave is in closed state. It should be understood that, the addresses of the slaves are not limited to starting from 0x01, which may be selected any one from 0x00 -OxFE
  • the host will automatically enter the initialization process: 1.
  • the host sends the initialization command: STX + 0x5A + OxFF + 0x00 + Data + CRC16 + ETX (any data)
  • the host consecutively sends it for 5 seconds, and after three slaves receive effective information, delays for 3 seconds to disconnect the relay, and at the same time set its own address as Oxff.
  • slave 1 sends the response to the host:
  • the destination address 0x00 is the address of the host
  • the source address OxFF is the address of the slave. 3.
  • the destination address is 0x01, which represents that the assignment starts from 0x01;
  • slave 1 After receiving the command, slave 1 sends acknowledgement response to the host:
  • slave 1 After slave 1 receives the command, slave 1 compares the address in the command with its assigned address, finds that the addresses do not match, then neglects it and does not answer it; after receiving the command, slave 2 stores the address (i.e. replaces Oxff with the address in the command) and sends the acknowledgement response to the host: STX + OxAo + 0x00 + 0x02 + Data + CRC16 + ETX (any Data) and at the same time closes the relay, and connects next slave 3.
  • slave 3 After slave 1 and slave 2 receive the command and find that the address in the command and their assigned addresses do not match, then neglect them and do not answer them; after receiving the command, slave 3 stores the address and sends the acknowledgement response to the host:
  • the host consecutively sends it for 10 times, and if there is no response, the address assignment ends.
  • the format of the address assignment command is not limited to the above format, but may be any other suitable format, for example, it may apply the format that carries assigned address in the Data bit.
  • the slave whose address is Oxff after receiving the command, uses Addr to replace Oxff, and sends the acknowledgement response, and at the same time connects the communication of the next slave
  • the first slave finds that it is not its own address by comparison and does not answer it; after receiving the command, the second slave finds that the command is just for itself, then the second slave uses Addr + 1 to replace Oxff, and answers it , and at the same time connects the next slave
  • the address checking is not executed after the initialization step, and the address assignment can be directly executed. In another embodiment, every time before address assignment, address checking is executed once.
  • Oxff is resumed. Then, slave 4 is directly inserted to the network. After slave 4 is powered up, it finds that the initialization switch is pressed, then slave 4 starts initialization, disconnects the relay, and waits for the address assignment.
  • Slaves 1, 2 and 3 receive the command and find that the address in the command does not match their assigned addresses, and then neglect it; after receiving the command, slave 4 stores the address and sends the acknowledgement response to the host: STX + 0xA6 + 0x00 + 0x04 + Data + CRC 16 + ETX (any Data)
  • the host consecutively sends it for 10 times, and if there is no response, the address assignment ends.
  • one new slave 5 is added in the network between slave 1 and slave 2
  • one new slave 6 is added between slave 3 and slave 4
  • the initialization switches of slaves 5 and 6 are pressed, the factory default setting Oxff is resumed, and then the slaves are directly inserted to the network.
  • slave 5 and salve 6 are powered up and find that the initialization switches are pressed, then slave 5 and slave 6 start initialization, disconnect the relay, and wait for the address assignment.
  • slave 6 Since slave 6 is located downstream of slave 5, when the relay of slave 5 has been disconnected, only slave 5 is the slave that is connected to the host and whose address is Oxff, i.e., in the system, at any time, there is no more than one slave whose address is Oxff is connected to the host.
  • slave 1 After slave 1 receives the command and finds that the address in the command does not match its assigned address, slave 1 neglects it; after receiving the command, slave 5 sends the acknowledgement response to the host:
  • slave 1 After slave 1 receives the command and finds that the address in the command does not match its assigned address, slave 1 neglects it; after receiving the command, slave 5 saves the address and sends the acknowledgement response to the host: STX + 0xA6 + 0x00 + 0x05 + Data + CRC 16 + ETX (any Data) and at the same time closes the relay, and connects slave 6.
  • the host sends the formal address assignment command to the slaves again: STX + 0x5C + 0x07 + 0x00 + Data + CRC16 + ETX (any Data)
  • the host consecutively sends it for 10 times, and if there is no response, the address assignment ends.
  • the invention is not limited to the detailed form disclosed in the abovementioned preferred implementing scheme.
  • the invention can also be applied in multi- master and multi-slave system.
  • this kind of system there would be one master station which realizes the address assignment, and the other master stations may not take part in the address assignment, or they may be treated as a special slave station (with some kind of special mark).

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
  • Selective Calling Equipment (AREA)

Abstract

Cette invention se rapporte à un système destiné à affecter une adresse intelligente. Le système comprend : un hôte, qui inclut un contrôleur MCU qui exécute une fonction d'affectation d'adresses, un module de communication, une mémoire et un commutateur d’initialisation ; un esclave, qui inclut un contrôleur MCU qui exécute une fonction d'affectation d'adresse, un module de communication, un commutateur physique électronique, une mémoire et un commutateur d’initialisation. Le réseau est formé de la façon suivante : après avoir quitté l'hôte, les lignes de paires torsadées sont acheminées à la borne d'entrée du commutateur physique électronique du premier esclave, puis elles sortent par la borne de sortie du commutateur physique électronique du premier esclave pour aller vers la borne d'entrée du commutateur physique électronique du deuxième esclave.
PCT/CN2008/001814 2008-07-21 2008-10-29 Système et procédé d'affectation d'adresse intelligente basée sur un bus série Ceased WO2010009584A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1125370A (zh) * 1994-02-17 1996-06-26 海德堡印刷机械股份公司 在一种串联主从装置中配置功能单元的方法及装置
JPH1165970A (ja) * 1997-08-25 1999-03-09 Hitachi Ltd 制御システム構築方法
CN1655081A (zh) * 2004-02-10 2005-08-17 上海新时达电气有限公司 自动分配串行总线设备地址分配器及其控制方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1125370A (zh) * 1994-02-17 1996-06-26 海德堡印刷机械股份公司 在一种串联主从装置中配置功能单元的方法及装置
JPH1165970A (ja) * 1997-08-25 1999-03-09 Hitachi Ltd 制御システム構築方法
CN1655081A (zh) * 2004-02-10 2005-08-17 上海新时达电气有限公司 自动分配串行总线设备地址分配器及其控制方法

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GB2506976A (en) * 2012-08-20 2014-04-16 Control Tech Ltd Address allocation for slave nodes connected in series
EP2840643A1 (fr) * 2013-06-05 2015-02-25 Samsung SDI Co., Ltd. Contrôleur esclave, procédé de communication, système de communication, système de stockage d'énergie comprend le système de communication
US9436261B2 (en) 2013-06-05 2016-09-06 Samsung Sdi Co., Ltd. Battery management system, and method of managing the same
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