WO2010086642A2

WO2010086642A2 - Apparatus for use in near field rf communicators

Info

Publication number: WO2010086642A2
Application number: PCT/GB2010/050106
Authority: WO
Inventors: Alastair Leffley
Original assignee: Innovision Research and Technology PLC
Current assignee: Broadcom Innovision Ltd
Priority date: 2009-01-27
Filing date: 2010-01-25
Publication date: 2010-08-05
Anticipated expiration: 2011-07-27
Also published as: GB2467183B; WO2010086642A3; GB2467183A; GB0901313D0

Abstract

A voltage level shifter has a supply voltage coupling to couple to a supply voltage having a reset voltage level and a programming voltage level, a control voltage input to couple to a control voltage having first and second voltage levels (a and ã), and an output. The relative timing of transitions between first and second control voltage levels (a and ã) and transitions between the reset and programming voltage levels is controlled so that the voltage level shifter is not exposed to the programming voltage level during control voltage transitions.

Description

APPARATUS FOR USE IN NEAR FIELD RF COMMUNICATORS

This invention relates to apparatus for use in near field RF communicators for and a method of controlling a voltage level shifter and a voltage level shift controller.

Near field RF (radio frequency) communication is becoming more and more commonplace as is the use of such technology to transfer data. Near field RF communicators communicate through the modulation of the magnetic field (H field) generated by a radio frequency antenna. Near field RF communication thus requires an antenna of one near field RF communicator to be present within the alternating magnetic field (H field) generated by the antenna of another near field RF communicator by transmission of an RF signal (for example a 13.56 Mega Hertz signal) to enable the magnetic field (H field) of the RF signal to be inductively coupled between the communicators. The RF signal may be modulated to enable communication of control and/or other data. Ranges of up to several centimetres (generally a maximum of 1 metre) are common for near field RF communicators.

NFC communicators are a type of near field RF communicator that is capable in an initiator mode of initiating a near field RF communication (through transmission or generation of an alternating magnetic field) with another near field RF communicator and is capable in a target mode of responding to initiation of a near field RF communication by another near field RF communicator. The term "near field RF communicator" includes not only NFC communicators but also initiator near field RF communicators such as RFID transceivers or readers that are capable of initiating a near field RF communication but not responding to initiation of a near field RF communication by another near field RF communicator and target or responding near field RF communicators such as RFID transponders or tags that are capable of responding to initiation of a near field RF communication by another near field RF communicator but not of initiating a near field RF communication with another near field RF communicator. Hence NFC communicators can act as both RFID transceivers and RFID transponders and are able to communicate with other NFC communicators, RFID transceivers and RFID transponders. In addition NFC communicators may be associated with or comprised within or attached to certain peripheral devices, for example SIM cards (e.g. UICC), Secure Elements, memory devices (for example MCU, RAM, ROM and non-volatile memory), display driver or other drivers. During operation the NFC communicator must also be able to communicate with and transfer data to and from such peripheral device.

There are several standards in existence which set out certain communication protocols and functional requirements for RFID and near field RF communications. Examples are ISO/IEC 14443, ISO 15693, ISO/IEC 18092 and ISO/IEC 21481.

NFC communicators may be comprised within a larger device, NFC communications enabled devices. Examples include mobile telephones, PDAs, computers, smart cards. When comprised within such NFC communications enabled devices the NFC communicator must be able to transfer data to and from the larger device and to and from any peripheral devices (including interface systems, such as the single wire protocol) associated with such larger device.

Near field RF communicators such as NFC communicators may include electrically erasable memory.

Electrically erasable memory comprises floating gate transistors that may require high voltages, for example 15 volts, in order to perform memory program or erase operations.

Voltage level shifting circuits are used to shift logic signals from a low voltage digital power supply voltage, for example 1.8 volts, up to the high voltage required to enable programming or erasing of the memory.

Level shifting circuits generally comprise a number of voltage controlled impedances (VCIs), for example Insulated Gate Field Effect Transistors (IGFETs).

Existing level shifting circuits require the use of voltage controlled impedances that are either capable of withstanding high voltages or are protected from such high voltages. High voltage transistors such as high voltage IGFETs designed to be capable of withstanding high source-drain voltages may be used. However, generally it is difficult to design high voltage VCIs such as high voltage transistors that can be switched using logical level voltages without crude dimensioning of the high voltage VCIs which wastes semiconductor real-estate (area), increases the overall device size and increases costs.

Without such designing of the high voltage transistors so that they can be switched using logical level voltages, the logic level voltages will be too weak to drive the high voltage transistors properly and additional circuitry may be required which increases the circuit complexity and size and so again increases overall costs.

Low voltage VCIs rather than high voltage VCIs may be used so enabling driving with a logic level signal, provided they are protected from the high voltages that arise in the level shifting circuit. This may be achieved, by, for example, providing additional 'cascode' high voltage VCIs, for example high voltage transistors, in the level shifting circuit in series with the low voltage VCIs, provided that appropriate control electrode drive voltages are available for the cascode high voltage VCIs. Another possibility, is to use medium voltage VCIs using such cascode protection and/or to use an intermediate level shifting stages for example by coupling two or more level shifting stages into a level shifting chain for example using a first level shifting circuit to shift the low voltage level to an intermediate voltage level and a second level shifting circuit to shift the intermediate voltage level to the required high voltage level. These possibilities overcome the problem of source-drain voltage sensitivity but require the use of additional components which increases the overall size and complexity of the level shifting circuitry and thus increases costs.

Thus there exists a need in the art for a voltage level-shifting scheme requiring few components, occupying the minimum amount of semiconductor "real-estate"; and, which is able to control high voltage levels (EE program/erase voltages) using low control voltages. An aspect of the present invention provides a method of controlling operation of a voltage level shifter that alleviates at least some of the aforementioned problems.

An aspect of the present invention provides a method of controlling operation of a voltage level shifter, the voltage level shifter comprising a supply voltage coupling to couple to a supply voltage having a reset voltage level and a programming voltage level, a control voltage input to couple to a control voltage having first and second voltage levels, and an output, the method comprising controlling the relative timing of transitions between first and second control voltage levels and transitions between the reset and programming voltage levels so that the voltage level shifter is not exposed to the programming voltage level during control voltage transitions.

The supply voltage transitions may be controlled so that the voltage level shifter is not exposed to the programming voltage level during control voltage transitions. The supply voltage may have an intermediate voltage level intermediate the programming and reset voltage levels and the method may comprise controlling supply voltage transitions between the reset voltage level, the programming voltage level, and the intermediate voltage level.

Transitions between supply voltage levels may occur periodically. Transitions between supply voltage levels may be controlled in response to a requirement for a control voltage transition.

Transitions between first and second voltage levels may occur when the supply voltage is not at the programming voltage level. Transitions between first and second voltage levels may occur when the supply voltage is at the reset voltage level.

An aspect of the present invention provides a method of controlling operation of a voltage level shifter comprising a voltage controlled impedance having first and second main electrodes and a control electrode coupled to a control voltage coupling, the first main electrode being coupled to a reference voltage coupling and the second main electrode coupled to the supply voltage coupling, the voltage controlled impedance having an on-voltage dependent upon the voltage between its first and second main electrodes, the method comprising controlling the relative timing of transitions between first and second control voltage levels and transitions between the reset and programming voltage levels so that transitions between the first and second voltage levels occur when the on voltage is less than or equal to the difference between first and second voltage levels.

In a second aspect the present invention provides a method of controlling operation of a voltage level shifter, the voltage level shifter comprising a supply voltage coupling to couple to a supply voltage having a reset voltage level and a programming voltage level, a control voltage input to couple to a control voltage having first and second voltage levels, and an output, the method comprising controlling the relative timing of transitions between first and second control voltage levels and transitions between the reset and programming voltage levels so that the voltage level shifter generates a correct logical output even with first and second control voltages at levels insufficient to render a voltage controlled impedance of the level shifter fully conducting.

An aspect of the present invention provides a method of controlling operation of a voltage level shifter, the voltage level shifter comprising a supply voltage coupling to couple to a supply voltage having a reset voltage level and a programming voltage level, a control voltage input to couple to a control voltage having first and second voltage levels, and an output, the method comprising controlling the relative timing of transitions between first and second control voltage levels and transitions between the reset and programming voltage levels so that the voltage level shifter generates a correct logical output even with first and second control voltages at inferior levels, that is levels insufficient to render a voltage controlled impedance of the level shifter fully conducting.

An aspect of the present invention provides apparatus for controlling operation of a voltage level shifter comprising a supply voltage coupling to couple to a supply voltage having a reset voltage level and a programming voltage level, a control voltage input to couple to a control voltage having first and second voltage levels, and an output, the apparatus having a controller to control the relative timing of transitions between first and second control voltage levels and transitions between the reset and programming voltage levels so that the voltage level shifter is not exposed to the programming voltage level during control voltage transitions. In another aspect the present invention provides an apparatus for controlling operation of a voltage level shifter comprising a supply voltage coupling to couple to a supply voltage having a reset voltage level and a programming voltage level, a control voltage input to couple to a control voltage having first and second voltage levels, and an output, the apparatus having a controller to control the relative timing of transitions between first and second control voltage levels and transitions between the reset and programming voltage levels to enable the voltage level shifter to generate a correct logical output even with first and second control voltages at levels insufficient to render a voltage controlled impedance of the level shifter fully conducting.

An aspect of the present invention provides a level shifter circuit comprising: a level shifter having a first voltage controlled impedance (203) having first and second main electrodes and a control electrode coupled to a control voltage coupling having first and second control voltage levels (a and a), the first main electrode of the first voltage controlled impedance being coupled to a reference voltage coupling (GND), and a second voltage controlled impedance (202) having first and second main electrodes and a control electrode, the first main electrode of the second voltage controlled impedance (202) being coupled to a supply voltage coupling (Vpp) to couple to a supply voltage having a reset voltage level and a programming voltage level, the second main electrode of the second voltage controlled impedance (202) being coupled to the reference voltage coupling (GND) and the control electrode of the second voltage controlled impedance (202) being coupled to the second main electrode of the first voltage controlled impedance (203); and a controller to control the relative timing of transitions between first and second control voltage levels and transitions between the reset and programming voltage levels so that the voltage level shifter is not exposed to the programming voltage level during control voltage transitions.

In an embodiment, the level shifter circuit has: a third voltage controlled impedance (204) having first and second main electrodes and a control electrode coupled to a control voltage coupling having first and second control voltage levels (a and a), the first main electrode of the third voltage controlled impedance (204) being coupled to the reference voltage coupling (GND), the control electrode of the third voltage controlled impedance (204) being coupled to a further control voltage coupling having first and second control voltage levels, and the second main electrode of the third voltage controlled impedance being coupled to second main electrode of the second voltage controlled impedance so that the second voltage controlled impedance is coupled to the reference voltage coupling via the third voltage controlled impedance ; and a fourth voltage controlled impedance having first and second main electrodes and a control electrode, the first main electrode of the fourth voltage controlled impedance being coupled to the supply voltage coupling , the second main electrode of the fourth voltage controlled impedance being coupled to second main electrode of the first voltage controlled impedance so that the fourth voltage controlled impedance is coupled to the reference voltage coupling via the first voltage controlled impedance and the control electrode of the fourth voltage controlled impedance being coupled to the second main electrode of the third voltage controlled impedance .

An aspect of the present invention provides a level shifter circuit comprising: a level shifter having cross-coupled p-channel IGFETS having their source electrodes coupled to a voltage supply line that couples to a supply voltage having a reset voltage level and a programming voltage level and their drain electrodes coupled to drain electrodes of respective n-channel IGFETS having their source electrodes coupled to a reference voltage line, the gate electrodes of the n-channel IGFETS being coupled to a logic level signal supplier to provide first and second voltage levels in anti-phase to the gate electrodes of the n-channel IGFETS; and a controller to control the relative timing of transitions between first and second control voltage levels and transitions between the reset and programming voltage levels so that the voltage level shifter is not exposed to the programming voltage level during control voltage transitions. In an embodiment a voltage level shifter has a supply voltage coupling to couple to a supply voltage having a reset voltage level and a programming voltage level, a control voltage input to couple to a control voltage having first and second voltage levels, and an output. The relative timing of transitions between first and second control voltage levels and transitions between the reset and programming voltage levels is controlled so that the voltage level shifter is not exposed to the programming voltage level during control voltage transitions.

Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:

Figure 1 shows a representational diagram illustrating communication between two devices comprising NFC communicators; Figure 2 shows an embodiment of an NFC communicator according to an aspect of the present invention;

Figure 3 shows a part-functional, part circuit diagram of a voltage level shifter in accordance with an embodiment of the invention;

Figure 4shows a timing diagram for explaining operation of the voltage level shifter shown in Figure 3.

With reference to the drawings in general, it should be understood that any functional block diagrams are intended simply to show the functionality that exists within the device and should not be taken to imply that each block shown in the functional block diagram is necessarily a discrete or separate entity. The functionality provided by a block may be discrete or may be dispersed throughout the device or throughout a part of the device. In addition, the functionality may incorporate, where appropriate, hard-wired elements, software elements or firmware elements or any combination of these. The near field RF communicator may be provided wholly or partially as an integrated circuit or collection(s) of integrated circuits.

Referring now specifically to Figure 1 , there is shown a representational diagram illustrating communication between two NFC communications enabled devices. In Figure 1 the representations of the NFC communications enabled devices have been shown partly cut-away and the functionality provided by the NFC communications enabled devices illustrated by way of a functional block diagram within the NFC communications enabled device.

As shown in Figure 1 , one NFC communications enabled device comprises a mobile telephone (cellphone) 1 and the other NFC communications enabled device comprises a portable computer 2 such as a notebook or laptop computer.

The mobile telephone 1 has the usual features of a mobile telephone including mobile telephone functionality 10 (in the form of, usually, a programmed controller, generally a processor or microprocessor with associated memory or data storage, for controlling operation of the mobile telephone in combination with a SIM card), an antenna 8 for enabling connection to a mobile telecommunications network, and a user interface 3 with a display 4, a keypad 5, a microphone 6 for receiving user voice input and a loudspeaker 7 for outputting received audio to the user. The mobile telephone also has a chargeable battery 11 coupled to a charging socket 12 via which a mains adapter (not shown) may be connected to enable charging of the battery 1 1. The mobile telephone 1 may have an alternative or additional power supply (not shown), for example a reserve battery or emergency battery. The chargeable battery 1 1 forms the primary power supply for the mobile telephone and NFC communicator 15. Given it is chargeable, it is designed to be removed at certain times.

Similarly the portable computer 2 has the usual features of a portable computer including portable computer functionality 20 in the form of, usually, a processor with associated memory in the form of ROM, RAM and/or hard disk drive, one or more removable media drives such as a floppy disk drive and/or a CDROM or DVD drive, and possibly a communications device for enabling the portable computer to connect to a network such as the Internet. The portable computer 2 also includes a user interface 21 including a display 22, a keyboard 23 and a pointing device, as shown a touchpad 24. The portable computer 2 also has a chargeable battery 25 coupled to a charging socket 26 via which a mains adapter (not shown) may be connected to enable charging of the battery 25. Again the chargeable battery 25 is the primary power supply for the portable computer and NFC communicator 30. In addition, as shown in Figure 1 , both NFC communications enabled devices 1 and 2 have an NFC communicator 15 and 30. As shown, the NFC communicators 15 and 30 are incorporated within the larger devices and, as with the other functional blocks, may be discrete entities within the host devices or may be provided by features dispersed throughout or integrated within the host device or a part of the host device.

Each NFC communicator 15 and 30 comprises NFC operational components 16 and 31 for, as will be described below, enabling control of the NFC functionality and generation, modulation and demodulation of an RF signal. Each NFC communicator 15 and 30 also comprises an antenna circuit 17 and 32 comprising an inductor or coil in the form of an antenna 18 and 33. The antenna circuits 17 and 32 enable an alternating magnetic field (H field) generated by the antenna of one near field RF communicator 15 (or 30) by transmission of an RF signal (for example a 13.56 Mega Hertz signal) to be inductively coupled to the antenna of the other near field RF communicator 30 (or 15) when that antenna is within the near field of the RF signal generated by the one near field RF communicator 15 (or 30).

The NFC communicators 15 and 30 are coupled to the mobile telephone and portable computer functionality 10 and 20, respectively, to enable data and/or control commands to be sent between the NFC communicator and the host device and to enable user input to the NFC communicator. Communication between the user interface 3 or 21 and the NFC communicator 15 or 30 is via the host device functionality 1 1 or 20, respectively.

Each NFC communicator 15 and 30 also comprises a power provider 19 and 34. The power providers 19 and 34 may be power supplies within the host device or specific to the NFC communicators 15 and 30, for example a button cell battery, or other small battery. In this case as shown by dashed lines in Figure 1 , one or both of the power providers 19 and 34 comprise a coupling to derive power from the corresponding device battery 1 1 or 25 i.e. the primary power supply.

It will be appreciated that Figure 1 shows only examples of types of host devices. A host device may be another type of electrical device such as a personal digital assistant (PDA), other portable electrical device such as a portable audio and/or video player such as an MP3 player, an I POD®, CD player, DVD player or other electrical device. As another possibility the NFC communicator (15 or 3) may be comprised within or coupled to a peripheral device, for example in the form of a smart card or other secure element which may be stand alone or comprised within or intended to be inserted into another electrical device. For example a SIM card for use in a mobile telephone. As a further possibility such peripheral devices may comprise interfacing systems or protocols such as the single wire protocol.

Also, rather than being incorporated within the host device, the NFC communicator 15 or 30 may be associated with the host device, for example by a wired or wireless coupling. In such a case, a housing of the NFC communicator may be physically separate from or may be attached to the housing of the host device; in the later case, the attachment may be permanent once made or the NFC communicator may be removable. For example, the NFC communicator may be housed within: a housing attachable to another device; a housing portion, such as a fascia of the NFC communications enabled device or another device; an access card; or may have a housing shaped or configured to look like a smart card. For example an NFC communicator may be coupled to a larger device by way of a communications link such as, for example, a USB link, or may be provided as a card (for example a PCMCIA card or a card that looks like a smart card) which can be received in an appropriate slot of the larger or host device.

In addition, one or both of the NFC communications enabled devices may be a standalone NFC communicator, that is it may have no functionality beyond its NFC communications functionality.

Figure 2 shows a functional block diagram of an NFC communications enabled device 100 in accordance with the invention to illustrate in greater detail one way in which the NFC operational components of an NFC communications enabled device embodying the invention may be implemented.

In this example, the NFC communications enabled device 100 comprises an NFC communicator 100a having NFC operational components including an antenna circuit 102, power provider 104, controller 107, data store 108, signal generator 109 and demodulator 1 14. Data store 108 comprises a memory controller 108'. Memory controller 108' controls read, write and erase operations performed on the memory 108'. In this example memory controller 108' comprises a voltage controller 210 (Figure 3) which is operable to control the voltage level VPP in response to a logic level signal provided by a logic level controller 211 (Figure 3). As other possibilities, the memory controller 108' may be separate from the data store or may be provided by the controller 107. The logic level controller 21 1 may or may not be part of memory controller 108'.

The power provider 104 may be any one or more of the types of power providers discussed above. In the interests of simplicity, power supply couplings from the power provider 104 to other components are not shown in Figure 2.

The NFC communications enabled device 100 may or may not also have or be capable of being connected or coupled with at least one of other functionality 105 (for example functionality of a host device or peripheral device such as described above) and a user interface 106.

The NFC operational components include a demodulator 1 14 coupled between the antenna circuit 102 and the controller 107 for demodulating a modulated RF signal inductively coupled to the antenna circuit 102 from another near field RF communicator in near field range and for supplying the thus extracted data to the controller 107 for processing. The received signal is first past through a rectifier 200 and regulator 310. The regulator 310 sets the required pin voltage and rectifier 200 provides rectified voltage to remainder of NFC circuit. Together the rectifier 200 and regulator 310 protect the NFC operational components from high voltages received at antenna circuit 102. For example the regulator may limit the voltage to 3.3 volts. Any standard regulator and rectification circuit can be used for this. The NFC operational components may also include an amplifier for amplifying an RF signal inductively coupled to the antenna circuit 102.

In addition the NFC operational components include components for enabling modulation of an RF signal to enable data to be communicated to another near field RF communicator in near field range of the NFC communicator 100a. As shown in Figure 2, these components comprise a signal generator 109 coupled via a driver 1 11 to the antenna circuit 102. In this example, the signal generator 1 10 causes modulation by gating or switching on and off the RF signal in accordance with the data to be communicated. The NFC communicator may use any appropriate modulation scheme that is in accordance with the standards and/or protocols under which the NFC communicator operates. As another possibility a separate or further signal controller may be incorporated within the NFC operational components to control modulation of the signal generated by the signal generator 109 in accordance with data or instructions received from the controller 107.

The NFC operational components also include a controller 107 for controlling overall operation of the NFC communicator. The controller 107 is coupled to a data store 108 for storing data (information and/or control data) to be transmitted from and/or data received by the NFC communications enabled device. The controller 107 may be a microprocessor, for example a RISC processor or other microprocessor or a state machine. Program instructions for programming the controller and/or control data for communication to another near field RF communicator may be stored in an internal memory of the controller and/or the data store.

The NFC communicator 100a may operate in an initiator mode (that is as an initiating near field RF communicator) or a target mode (that is as a responding near field RF communicator), dependent on the mode to which the NFC communicator is set. The mode may be determined by the controller 107 or may be determined in dependence on the nature of a received near field RF signal. When in initiator mode, an NFC communicator initiates communications with any compatible responding near field RF communicator capable of responding to the initiating NFC communicator (for example an NFC communicator in target mode or an RFID tag or transponder) that is in its near field range, while when in target mode an NFC communicator waits for a communication from a compatible initiating near field RF communicator (for example an NFC communicator in initiator mode or an RFID initiator or transceiver). As thus used, compatible means operable at the same frequency and in accordance with the same protocols, for example in accordance with the protocols set out in various standards such as ISO/IEC 18092, ISO/IEC 21481 , ISO/IEC 14443 and ISO/IEC 15693. NFC communicators commonly operate at or around 13.56MHz. When in initiator or target mode, the NFC communicator may communicate in accordance with an active or passive protocol. When using an active protocol the initiating NFC communicator will transmit an RF field and following completion of its data communication turn off its RF field. The responding near field RF communicator (target) will then transmit its own RF field and data before again turning off the RF field and so on. When using a passive protocol the NFC communicator (initiator) will transmit and maintain its RF field throughout the entire communication sequence. The protocol used will depend on instructions received from the controller 107 and the response received from a responding near field RF communicator.

In Figure 2 control of operation of the NFC communicator is through controller 107. As another possibility where the NFC communicator is comprised as part of a host device, control of the operation of the NFC communicator may be directed by the host device, for example through other functionality 105. In such circumstances all or part of the control may be provided by other functionality 105. For example the NFC communicator controller 107 may control modulation and modulation protocols whereas the data to be transmitted may be provided by other functionality 105.

The NFC communicator also comprises an antenna circuit 102. The design of the antenna circuit will depend on the NFC communicator 100 and the environment in which it operates. For example the antenna circuit may be in the form described for co-pending international patent application number PCT/GB2008/000992 (which claims priority from GB 0705635.1 ).

Figure 3 shows a part-functional, part circuit diagram of a voltage level shifter that may be used in a NFC communicator such as described above whilst Figure 4 shows a timing diagram for explaining operation of the voltage level shifter shown in Figure 3.

The example of Figure 3 shows a voltage level shifter constructed from High Voltage, HV, Voltage Controlled Impedances 201 , 202, 203 and 204. Each Voltage Controlled Impedance has a first main and a second main electrode and at least one control electrode. The electrodes of HV voltage controlled impedances are able to withstand large voltages. In the example illustrated, the Voltage Controlled Impedances 201 and 202 are p-channel IGFETS (for example PMOS transistors) whilst the Voltage Controlled Impedances 203 and 204 are high voltage n-channel IGFETS (for example high voltage NMOS transistors).

The first main electrodes of voltage controlled impedances 201 and 202 are both coupled to supply voltage line, VPP. The control electrode of voltage controlled impedance 201 is coupled to the second main electrode of voltage controlled impedance 202 and the control electrode of voltage controlled impedance 202 is coupled to the second main electrode of voltage controlled impedance 201. Thus the voltage controlled impedances 201 and 202 are cross-coupled.

The control electrode of voltage controlled impedance 202 and the second main electrode of voltage controlled impedance201 are coupled together to the second main electrode of voltage controlled impedance 203 at node 205. The control electrode of voltage controlled impedance 201 and the second main electrode of voltage controlled impedance 202 are coupled together to the second main electrode of voltage controlled impedance 204 at node 206. The first main electrodes of voltage controlled impedances 203 and 204 are coupled to a ground connection or reference voltage GND.

A voltage controller 210 is coupled to control the supply voltage VPP. Logic level controller 211 has first and second outputs. The first output of logic level controller is coupled to the control electrode of voltage controlled impedance 203 and the second output of logic level controller 211 is coupled to the control electrode of voltage controlled impedance 204.

In one possibility logic level controller 211 has a third coupling (shown in dashed lines) to voltage controller 210 and is operable to sense the voltage VPP.

The first and second outputs of logic level controller 21 1 provide low voltage levels. The first output of logic level controller 211 provides a logic signal voltage, a. which is controlled to be at a first voltage, for example 1.8V, representing a logical high level or a second voltage, for example OV, representing a logical low level. The second output of logic level controller 21 1 provides a logic signal voltage, a, that is the logical inverse of logic signal voltage a.

In the example of Figure 3 the low level voltage signal, in this example 1.8 V, is insufficient fully to bias the HV voltage controlled impedances 203 and 204 into a conducting state.

Voltage controller 210 is arranged to control the voltage VPP according to a timing scheme so that the voltage VPP is varied as a function of time. In examples of the invention, the timing of switch transitions in the logic signals, a and a, is controlled by logical level controller 21 1 to take advantage of the variation of VPP.

The control of the timing of switch transitions in the logic signals, a and a, by logical level controller 21 1 will now be described with reference to Figure 4. In the example of Figure 4 voltage vs. time graphs illustrate a possibility for voltage control employed in examples of the invention. The break lines in Figure 4 indicate that the two shown cycles are not necessarily successive cycles, although they could be.

Graph 301 in Figure 4 represents the variation of voltage VPP with time. In this example, Voltage VPP is controlled to vary between a low voltage, GND, (for example 0 volts) and a high voltage VPP_max (for example 15 volts) via an intermediate voltage VPP_mιd (for example 3 volts) in a periodic or cyclical manner. The two cycles shown in Figure 4 are different (they have different ramp up times), they may however be the same or may vary in other ways.

As illustrated, at time t₀ VPP is VPP_mιd. VPP remains at VPP_mιd until, at time t| VPP begins to ramp down to reach GND at time t₂ . At time t₃ VPP begins to increase and continues to increase until, at time t₄, VPP reaches VPP_max; then, at time t₅ VPP begins to ramped down to reach VPP_mκl at time t₆where it remains until time t₇when it ramps down to reach GND at time t₈. In this example this cycle continues periodically with a period T, where T=t_rt₇.

Logic level controller 211 controls logic signals, a and a, to vary in accordance with required logic or memory control operations. Graphs 302 and 303 show the variation with time of low-level logic signals, a and a. Logic level signal a(a) is controlled to transition from logical-high state (logical-low state) to logical-low state (logical-high state) at a time t₂i in the interval between t₂ and time t₃. During this interval VPP is, as shown by graph 301 , at the same voltage as GND. As will be appreciated, in practice whether or not a transition occurs will depend on operational need, for example the need to perform memory program or erase operations.

The procedure of level shifting voltages using control signals according to the example of Figure 4 using a circuit according to the example of Figure 3 will now be described.

At time t₀ voltage controller 210 controls VPP to be VPP_mκ] and the low-level logic signal, a, is in a logical high state. This renders voltage controlled impedance 204 conducting and couples the voltage GND to the control electrode of voltage controlled impedance 201. Accordingly voltage controlled impedance 201 is rendered conducting and node 205 is coupled to VPP_mιd.

Between times t-i and t₂voltage controller 210 ramps VPP down to voltage GND when the voltage across the first and second main electrodes of voltage controlled impedance 201 , 202, 203 and 204 becomes approximately zero which means that the respective overdrive voltage for each of these voltage controlled impedances is relatively reduced.

At time t₂i the logic level controller 211 inverts the logic signals a and a, for example to perform a memory operation. Thus if, as shown in Figure 4, voltage a was in the logical-high state and voltage a was in the logical-low state, then these reverse. Voltage controller 211 applies the now logical-high signal, a, to the control electrode of 203. Although the voltage of the logical-high signal, a, is insufficient to render HV voltage controlled impedance 203 fully conducting some sub-threshold conduction does occur.

At time t₃ the voltage VPP begins to increase. In the absence of a voltage across the first and second main electrodes of 203, the sub-threshold conduction is sufficient appreciably to couple node 205 to GND. As VPP increases the voltage between the control and first main electrode of voltage controlled impedance 202 also increases, node 205 being coupled to GND. Accordingly voltage controlled impedance 202 is biased into a conducting state by the increasing voltage VPP.

At some later time t₈i the logic level controller 211 may invert the logic signal, for example to perform a memory operation causing voltage controller 211 to apply a logical high signal , a, to the control electrode of 204. Although the voltage of the logical-high signal, a, is insufficient to render HV voltage controlled impedance 204 fully conducting some sub-threshold conduction does occur.

At time t₉ the voltage VPP begins to increase. In the absence of a voltage across the first and second main electrodes of 204 the sub-threshold conduction is sufficient appreciably to couple node 206 to GND. As VPP increases the voltage between the control and first main electrode of voltage controlled impedance 201 also increases, node 206 being coupled to GND. Accordingly voltage controlled impedance 201 is biased into a conducting state by the increasing voltage VPP.

The timing diagram of Figure 4 shows two cycles of operation. In the first cycle VPP starts statically at VPP_mιd, resets to OV (GND) and then is "pumped" up to

VPP_ma_x. During its "pumping", node 206 follows both the same logic polarity as a and the value of VPP to rise to 15V, while 205 follows the polarity of a and therefore stays at GND.

In the second cycle VPP also starts statically at VPP_mιd, resets to GND and then is "pumped" up to VPP_max.

During its "pumping", node 205 follows both the same logic polarity as a and the value of VPP to rise to VPP_max, while 206 follows the polarity of a and therefore stays at GND.

The timing diagram therefore shows clearly that the logical function of 205 and 206 follows that of the logic signals a and a once the VPP signal is reset to GND and then pumped up to the high VPP voltage. The invention exploits the fact that VPP will be reset to OV (GND) before it is pumped. During the time that VPP is at OV, when the low voltage signal drives the high voltage transistor, the difficulty of level shifting is reduced greatly. The task becomes much simpler. This allows the circuit of Figure 3 to be used, with low- voltage signals driving high-voltage n-channel transistors directly.

This invention greatly widens the usable range of operation during which a low voltage signal is able to drive a high voltage transistor, by exploiting the fact that the VPP voltage is reset to OV. The benefits are great. Wasteful large transistor dimensions are avoided. Semiconductor area is saved. The complexity and potential risk of cascode schemes are avoided. Risk and complexity are reduced and the final design is inherently much simpler.

It will be understood that although periodic control of voltage VPP has been described aperiodic control of VPP is another possibility. In another possibility, instead of controlling logic level transitions according to a timing scheme, logic level controller 211 may cause logic transitions to occur only when VPP is at a low voltage, for example GND. In one possibility voltage controller 21 1 may be coupled to sense voltage level VPP and to enable a logic transition only when VPP is within a predetermined voltage range. As another possibility the procedure for performing a memory operation includes reducing VPP to permit memory operations as they are required.

Logic level transitions have been shown as occurring only when VPP is at a ground voltage level. However these transitions may occur when VPP is at any substantially low voltage level. The voltage levels that may be used in examples of the invention are dictated by characteristics of the voltage controlled impedances that are employed. Optionally, other VPP control waveforms, for example waveforms having higher or lower duty cycles may be used.

In the example of Figure 4: VPP_max is 15V greater than GND, VPP_mιd is 3V greater than GND; and, the logical-high signal, a_max, is 1.8V greater than GND. These examples are intended to be illustrative and not to limit the invention in any way. As will be appreciated, if suitable components are chosen and appropriate modifications are made the circuit and a suitable timing scheme may be employed with different voltages.

Examples of the invention may be used in the control of level shifters to shift voltages between any two voltage levels where the lower voltage level, under normal circumstances, would be insufficient to drive voltage controlled impedances in the level shifter. Depending on the size of the higher voltage the level-shifter may use only low-voltage voltage controlled impedances and employ methods according to the invention to enable control of the higher voltage level using the lower voltage level. In one example a design could have separate logic-voltage domains for example: at 1.2V and at 1.8V. In this example when a signal at 1.2V is passed to a circuit powered at 1.8V it may need to be level-shifted.

Voltage controlled impedances 203 and 204 are each chosen to be conducting when a sufficient positive potential difference exists between their respective control and first main electrodes. Voltage controlled impedances 201 and 202 are each chosen to be conducting when a sufficient negative potential difference exists between their respective control and first main electrodes. As will be apparent to the skilled practitioner, by making appropriate modifications, voltage controlled impedances having different polarities may be used.

In the example shown in Figure 3 voltage controlled impedances 201 and 202 are PMOS transistors and voltage controlled impedances 203 and 204 are NMOS transistors. It will be appreciated by the skilled practitioner that, by making appropriate modifications to the circuit shown in Figure 3, any suitable voltage controlled impedance may be used.

In the above reference is made to an NFC communicator. It will be apparent to the skilled man that a level shifter in accordance with the invention may be used in any near field RF communicator that requires voltage level shift functionality, for example any near field RF communicator that includes electrically erasable memory. A level shifter in accordance with the invention may also be used in any device or apparatus having electrically erasable memory for which a voltage level shifter may be required or desired. A level shifter in accordance with the invention may also be used for any other device or apparatus requiring such voltage level shifting functionality.

The above embodiments are to be understood as illustrative examples of the invention. Further embodiments of the invention are envisaged. It is to be understood that any feature described in relation to any one embodiment may be used alone, or in combination with other features described, and may also be used in combination with one or more features of any other of the embodiments, or any combination of any other of the embodiments. Furthermore, equivalents and modifications not described above may also be employed without departing from the scope of the invention, which is defined in the accompanying claims.

Claims

1. A method of controlling operation of a voltage level shifter, the voltage level shifter comprising a supply voltage coupling to couple to a supply voltage having a reset voltage level and a programming voltage level, a control voltage input to couple to a control voltage having first and second voltage levels, and an output, the method comprising controlling the relative timing of transitions between first and second control voltage levels and transitions between the reset and programming voltage levels so that the voltage level shifter is not exposed to the programming voltage level during control voltage transitions.

2. A method of controlling operation of a voltage level shifter, the voltage level shifter comprising a supply voltage coupling to couple to a supply voltage having a reset voltage level and a programming voltage level, a control voltage input to couple to a control voltage having first and second voltage levels, and an output, the method comprising controlling the relative timing of transitions between first and second control voltage levels and transitions between the reset and programming voltage levels so that the voltage level shifter generates a correct logical output even with first and second control voltages at levels insufficient to render a voltage controlled impedance of the level shifter fully conducting.

3. A method according to claim 1 or 2, wherein supply voltage transitions are controlled so that the voltage level shifter is not exposed to the programming voltage level during control voltage transitions.

4. A method according to claim 3, wherein the supply voltage has an intermediate voltage level intermediate the programming and reset voltage levels and the method comprises controlling supply voltage transitions between the reset voltage level, the programming voltage level, and the intermediate voltage level.

5. A method according to any of claims 1 to 4, wherein transitions between supply voltage levels occur periodically.

6. A method according to any of claims 1 to 4, wherein transitions between supply voltage levels are controlled in response to a requirement for a control voltage transition.

7. A method according to any of claims 1 to 5, comprising controlling transitions between first and second voltage levels to occur when the supply voltage is not at the programming voltage level.

8. A method according to any of claims 1 to 5, comprising controlling transitions between first and second voltage levels to occur when the supply voltage is at the reset voltage level.

9. A method according to any of claims 1 to 6, wherein the level shifter comprises a voltage controlled impedance having first and second main electrodes and a control electrode coupled to a control voltage coupling, the first main electrode being coupled to a reference voltage coupling and the second main electrode being coupled to the supply voltage coupling, the voltage controlled impedance having an on-voltage dependent upon the voltage between its first and second main electrodes, the method comprising controlling the relative timing of transitions between first and second control voltage levels and transitions between the reset and programming voltage levels so that transitions between the first and second voltage levels occur when the on voltage is less than or equal to the difference between first and second voltage levels.

10. A method of controlling operation of a voltage level shifter comprising a voltage controlled impedance having first and second main electrodes and a control electrode coupled to a control voltage coupling, the first main electrode being coupled to a reference voltage coupling and the second main electrode being coupled to the supply voltage coupling, the voltage controlled impedance having an on-voltage dependent upon the voltage between its first and second main electrodes, the method comprising controlling the relative timing of transitions between first and second control voltage levels and transitions between the reset and programming voltage levels so that transitions between the first and second voltage levels occur when the on-voltage is less than or equal to the difference between first and second voltage levels.

1 1. Apparatus for controlling operation of a voltage level shifter comprising a supply voltage coupling to couple to a supply voltage having a reset voltage level and a programming voltage level, a control voltage input to couple to a control voltage having first and second voltage levels, and an output, the apparatus having a controller to control the relative timing of transitions between first and second control voltage levels and transitions between the reset and programming voltage levels so that the voltage level shifter is not exposed to the programming voltage level during control voltage transitions.

12. Apparatus for controlling operation of a voltage level shifter comprising a supply voltage coupling to couple to a supply voltage having a reset voltage level and a programming voltage level, a control voltage input to couple to a control voltage having first and second voltage levels, and an output, the apparatus having a controller to control the relative timing of transitions between first and second control voltage levels and transitions between the reset and programming voltage levels to enable the voltage level shifter to generate a correct logical output even with first and second control voltages at levels insufficient to render a voltage controlled impedance of the level shifter fully conducting.

13. Apparatus according to claim 1 1 or 12, wherein the controller is arranged to control supply voltage transitions so that the voltage level shifter is not exposed to the programming voltage level during control voltage transitions.

14. Apparatus according to claim 11 , 12 or 13, wherein the supply voltage has an intermediate voltage level intermediate the programming and reset voltage levels and the controller is arranged to control supply voltage transitions between the reset voltage level, the programming voltage level, and the intermediate voltage level.

15. Apparatus according to any of claims 11 to 14, wherein the controller is arranged to control transitions between supply voltage levels in response to a requirement for a control voltage transition.

16. Apparatus according to any of claims 11 to15, wherein the controller is arranged to control transitions between first and second voltage levels to occur when the supply voltage is not at the programming voltage level.

17. Apparatus according to any of claims 11 to 15, wherein the controller is arranged to control transitions between first and second voltage levels to occur when the supply voltage is at the reset voltage level.

18. Apparatus according to any of claims 11 to 16, wherein the level shifter comprises a voltage controlled impedance having first and second main electrodes and a control electrode coupled to a control voltage coupling, the first main electrode being coupled to a reference voltage coupling and the second main electrode being coupled to the supply voltage coupling, the voltage controlled impedance having an on-voltage dependent upon the voltage between its first and second main electrodes, the controller being arranged to control the relative timing of transitions between first and second control voltage levels and transitions between the reset and programming voltage levels so that transitions between the first and second voltage levels occur when the on voltage is less than or equal to the difference between first and second voltage levels.

19. A level shifter circuit comprising a level shifter and apparatus according to any of claims 1 1 to 18.

20. A level shifter circuit according to claim 19, wherein the level shifter comprises voltage controlled impedances in the form of insulated gate field effect transistors.

21. A level shifter circuit comprising: a level shifter having cross-coupled p- channel IGFETS having their source electrodes coupled to a voltage supply line that couples to a supply voltage having a reset voltage level and a programming voltage level and their drain electrodes coupled to drain electrodes of respective n-channel IGFETS having their source electrodes coupled to a reference voltage line, the gate electrodes of the n-channel IGFETS being coupled to a logic level signal supplier to provide first and second voltage levels in anti-phase to the gate electrodes of the n- channel IGFETS; and a controller to control the relative timing of transitions between first and second control voltage levels and transitions between the reset and programming voltage levels so that the voltage level shifter is not exposed to the programming voltage level during control voltage transitions.

22. Apparatus for controlling operation of a voltage level shifter, substantially as hereinbefore described with reference to and/or as illustrated in Figure 3.

23. A method of controlling operation of a voltage level shifter, substantially as hereinbefore described with reference to and/or as illustrated in Figure 4.

24. A level shifter circuit, substantially as hereinbefore described with reference to and/or as illustrated in Figure 3.

25. An electrically erasable memory circuit having a level shifter circuit in accordance with any of claims 19 to 21 and 24.

26. A near field RF communicator having apparatus in accordance with any of claims 1 1 to 18 and 22, or a level shifter circuit in accordance with any of claims 19 to 21 and 24 or an electrically erasable memory circuit in accordance with Claim 25.

27. A near field RF communicator according to claim 26, substantially as hereinbefore described with reference to the accompanying drawings.

28. A near field RF communicator in accordance with claim 26 or 27, wherein the near field RF communicator is an NFC communicator.