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WO2010085340A3 - Contrôleur hôte - Google Patents

Contrôleur hôte Download PDF

Info

Publication number
WO2010085340A3
WO2010085340A3 PCT/US2010/000150 US2010000150W WO2010085340A3 WO 2010085340 A3 WO2010085340 A3 WO 2010085340A3 US 2010000150 W US2010000150 W US 2010000150W WO 2010085340 A3 WO2010085340 A3 WO 2010085340A3
Authority
WO
WIPO (PCT)
Prior art keywords
host controller
memory
command
memory device
host
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2010/000150
Other languages
English (en)
Other versions
WO2010085340A2 (fr
Inventor
Peter Feeley
Robert N. Leibowitz
William H. Radke
Neal A. Galbo
Victor Y. Tsai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of WO2010085340A2 publication Critical patent/WO2010085340A2/fr
Publication of WO2010085340A3 publication Critical patent/WO2010085340A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0685—Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)
  • Information Transfer Systems (AREA)

Abstract

La présente invention concerne des procédés, des dispositifs et des systèmes destinés à commander un dispositif de mémoire. Selon un mode de réalisation, un procédé destiné à commander d'un dispositif de mémoire comprend les étapes consistant à : stocker des informations qui dépendent de la classe du dispositif et une commande dans une ou plusieurs mémoires du système hôte et du contrôleur hôte; placer un pointeur au niveau de la commande dans un registre dans un contrôleur hôte; diriger l'accès vers la ou les mémoires du système hôte et du contrôleur hôte avec le dispositif de mémoire par l'intermédiaire du contrôleur hôte; et exécuter la commande avec le dispositif de mémoire.
PCT/US2010/000150 2009-01-26 2010-01-21 Contrôleur hôte Ceased WO2010085340A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/359,537 2009-01-26
US12/359,537 US8327040B2 (en) 2009-01-26 2009-01-26 Host controller

Publications (2)

Publication Number Publication Date
WO2010085340A2 WO2010085340A2 (fr) 2010-07-29
WO2010085340A3 true WO2010085340A3 (fr) 2010-10-21

Family

ID=42355056

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/000150 Ceased WO2010085340A2 (fr) 2009-01-26 2010-01-21 Contrôleur hôte

Country Status (3)

Country Link
US (4) US8327040B2 (fr)
TW (1) TWI439861B (fr)
WO (1) WO2010085340A2 (fr)

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US8832354B2 (en) 2009-03-25 2014-09-09 Apple Inc. Use of host system resources by memory controller
US8225052B2 (en) * 2009-06-03 2012-07-17 Micron Technology, Inc. Methods for controlling host memory access with memory devices and systems
EP2682870B1 (fr) * 2011-03-02 2016-11-02 Nec Corporation Système de commande de données, procédé de commande de données et programme de commande de données
KR102030733B1 (ko) * 2013-01-02 2019-10-10 삼성전자주식회사 메모리 시스템 및 이의 구동 방법
US9569352B2 (en) 2013-03-14 2017-02-14 Sandisk Technologies Llc Storage module and method for regulating garbage collection operations based on write activity of a host
US9471254B2 (en) * 2014-04-16 2016-10-18 Sandisk Technologies Llc Storage module and method for adaptive burst mode
US9928169B2 (en) 2014-05-07 2018-03-27 Sandisk Technologies Llc Method and system for improving swap performance
US9710198B2 (en) 2014-05-07 2017-07-18 Sandisk Technologies Llc Method and computing device for controlling bandwidth of swap operations
US9665296B2 (en) 2014-05-07 2017-05-30 Sandisk Technologies Llc Method and computing device for using both volatile memory and non-volatile swap memory to pre-load a plurality of applications
US9633233B2 (en) 2014-05-07 2017-04-25 Sandisk Technologies Llc Method and computing device for encrypting data stored in swap memory
US9846662B2 (en) * 2014-09-20 2017-12-19 Netronome Systems, Inc. Chained CPP command
US20160110119A1 (en) * 2014-10-15 2016-04-21 Prabhjot Singh Direct memory access for command-based memory device
US11150613B2 (en) * 2014-11-18 2021-10-19 Sensia Llc Configurable safety logic solver
US9990158B2 (en) 2016-06-22 2018-06-05 Sandisk Technologies Llc Storage system and method for burst mode management using transfer RAM
US10127185B1 (en) * 2016-12-20 2018-11-13 The United States Of America, As Represented By The Secretary Of The Navy Format agnostic data transfer circuit
CN107193766B (zh) * 2017-05-12 2020-04-10 苏州中科集成电路设计中心有限公司 一种PCIe设备与主机之间的多路有序数据传输方法

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US20070011180A1 (en) * 2003-06-13 2007-01-11 Microsoft Corporation Systems and methods for enhanced stored data verification utilizing pageable pool memory
US20070204074A1 (en) * 2006-02-28 2007-08-30 Fujitsu Limited Apparatus and method for performing DMA data transfer
US20080195802A1 (en) * 2007-02-13 2008-08-14 Byoung-Kook Lee System and method for searching mapping table of flash memory

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US20010014933A1 (en) * 1998-09-11 2001-08-16 Shogo Shibazaki Memory management table producing method and memory device
US20070011180A1 (en) * 2003-06-13 2007-01-11 Microsoft Corporation Systems and methods for enhanced stored data verification utilizing pageable pool memory
US20070204074A1 (en) * 2006-02-28 2007-08-30 Fujitsu Limited Apparatus and method for performing DMA data transfer
US20080195802A1 (en) * 2007-02-13 2008-08-14 Byoung-Kook Lee System and method for searching mapping table of flash memory

Also Published As

Publication number Publication date
US8327040B2 (en) 2012-12-04
US9588697B2 (en) 2017-03-07
US8578070B2 (en) 2013-11-05
WO2010085340A2 (fr) 2010-07-29
US20130013822A1 (en) 2013-01-10
TW201040727A (en) 2010-11-16
TWI439861B (zh) 2014-06-01
US9043506B2 (en) 2015-05-26
US20140108678A1 (en) 2014-04-17
US20160004436A1 (en) 2016-01-07
US20100191874A1 (en) 2010-07-29

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