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WO2010061035A1 - Gaufrage de composants à couches minces électroniques - Google Patents

Gaufrage de composants à couches minces électroniques Download PDF

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Publication number
WO2010061035A1
WO2010061035A1 PCT/FI2008/050695 FI2008050695W WO2010061035A1 WO 2010061035 A1 WO2010061035 A1 WO 2010061035A1 FI 2008050695 W FI2008050695 W FI 2008050695W WO 2010061035 A1 WO2010061035 A1 WO 2010061035A1
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WO
WIPO (PCT)
Prior art keywords
distance
gate
embossing
layer
embossing operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/FI2008/050695
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English (en)
Inventor
Tomas BÄCKLUND
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UPM Kymmene Oy
Original Assignee
UPM Kymmene Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by UPM Kymmene Oy filed Critical UPM Kymmene Oy
Priority to PCT/FI2008/050695 priority Critical patent/WO2010061035A1/fr
Publication of WO2010061035A1 publication Critical patent/WO2010061035A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/621—Providing a shape to conductive layers, e.g. patterning or selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/481—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/821—Patterning of a layer by embossing, e.g. stamping to form trenches in an insulating layer

Definitions

  • the invention relates to embossing of electronic thin-film components.
  • Modem integrated circuits typically silicon based structures, have very high integration density. As one descriptive parameter of this, the number of transistors per given surface area is growing steadily. However, integrated circuit based electronics are not optimal for all applications. For some applications the integration density and/or speed of the electronics is less crucial. Therefore, for certain applications different types of printable electronics are becoming more and more interesting.
  • One approach to reducing transistor cost, while still maintaining acceptable performance, is to produce thin-film transistors on a suitable substrate by printing. Here printing means that at least some device layers have been manufactured by printing techniques. There are several known ways of manufacturing basic conductive patterns of printed circuit boards.
  • embossing As compared to traditional printing of electronics structures, embossing, which may also be referred to as imprinting, provides a simple and economic mass production with possibility to obtain smaller and better-controlled details in the electronic structures. Embossing is typically used to pattern a 3-dimensional structure on a layered substrate.
  • US 2008/0012151 discloses a method applying embossing to separate electrodes from each other.
  • a source-drain or gate electrode in a transistor device is embossed on a substrate of a transistor device to have transistor electrodes at least on two different vertical levels.
  • a method for embossing electronic thin-film components An input material comprising a compressible layer and a conductive layer on the compressible layer is provided. An embossing operation is performed on the conductive layer to gaSvanically separate portions of the conductive layer to form an electrode pattern, wherein the embossing operation is applied to form, by a single embossing operation, an electrode separated by at least two embossed lines.
  • an apparatus for manufacturing electronic thin-film components by embossing comprising: means for receiving an input material comprising a compressible layer and a conductive layer on the compressible layer; and means for performing an embossing operation on the conductive layer to galvanically separate portions of the conductive layer to form an electrode pattern, wherein the apparatus is configured to apply the embossing operation to form, by a single embossing operation, an electrode separated by at least two embossed lines.
  • an electronic thin- film component comprising a compressible layer, and a conductive layer on the compressible layer, the conductive layer comprising an embossed electrode pattern, an electrode of the electrode pattern being separated by a single embossing operation by at least two embossed lines.
  • the invention and various embodiments of the invention provide several advantages, which will become apparent from the detailed description below.
  • it is, for example, easier to arrange further electrical contacts from the electrode separated by embossing, since the remaining non-embossed part of the electrode is better available for further electrical contacts.
  • Another important feature is that the imprinted lines can be arranged to form a narrow electrical channel on the substrate. In- other words using just two parallel imprinted lines, which can be produced in a single manufacturing step, it becomes possible to create an imprinted narrow gate structure with well-controlled dimensions.
  • Figure 2 illustrates a cross-sectional view of a structure for a transistor device embossed according to an embodiment
  • Figures 3a to 3c illustrate an embossing method according to an embodiment to separate transistor electrodes
  • Figure 4 illustrates an example of imprinted transistor electrodes from a top-view
  • Figure 5 illustrates manufacturing of electronic thin-film components applying embossing according to an embodiment
  • Figure 6 illustrates a cross-sectional view of a structure for a transistor device embossed according to an embodiment
  • Figure 7 illustrates a cross-sectional view of a structure for a transistor device embossed according to an embodiment
  • Figure 8 illustrates a cross-sectional view of a transistor structure embossed according to an embodiment
  • Figure 9 illustrates a transistor component structure according to an embodiment.
  • Embossing of transistor electrodes is known from US 2008/0012151.
  • the embossed area defines a transistor gate.
  • the embossed gate is formed into the bottom of a "dwell".
  • connection to the gate requires arranging galvanic connection to the bottom of said "dwell”. Therefore, there is a clear need to further improve production efficiency of manufacturing of embossed electronics and connectabiiity of embossed electrodes.
  • Figure 1 illustrates in a simplified form cross-sectional view of electrode structure embossed according to an embodiment.
  • the electrodes 20 and 30 have been separated from an initial unitary conductive layer by an embossing operation forcing a compressible and substantially non-conductive layer 10 to compress and form a gap between the electrodes 20 and 30, in the present embodiment in a triangle form.
  • embossing is applied only to a portion 22 of an electrode 20 to be separated.
  • the embossed portion 22 of the electrode and the remaining part 24 of the electrode are positioned on at least two different levels in transverse direction in relation to the plane of the compressible layer.
  • Such embossing operation is obtained by an embossing tool comprising a non-embossing area and a protrusion producing the embossed portion 22 when pressed against the conductive layer. It will be appreciated that a tool suitable for the present purposes may instead or in addition to the non-embossing area comprise an area producing less compression than the protrusion.
  • the electrode structure of Figure 1 enables easy use of the non-embossed part 24 of the electrode for further electrical connections.
  • FIG. 2 illustrates a simplified cross-sectional view of a transistor device 100 structure embossed according to an embodiment.
  • a source (S) 80, gate (G) 60, and drain (D) 90 are provided by a conductive layer on a compressible layer 50.
  • the gate 60 is formed by an embossing operation applied only to edges 64, 66 of the gate area 60 of the conductive layer being separated.
  • at least one portion 64, 66 of the gate 60 is positioned in a different level, in transverse direction in relation to the plane of the compressible layer, than the source 80 and/or gate 90, whereas a remaining part 62 of the gate may remain substantially on the same level as the source 80 and/or the drain 90.
  • the embossing operation produces two embossed lines 64 and 66 to separate the gate 60 from the source 80 and the drain 90.
  • a transistor channel length is defined as the distance between the source and drain electrodes 80, 90. As illustrated in Figure 2, the distance between the terminating ends of the two embossed gate portions 64, 66 defines the transistor channel length.
  • the compressible layer 50 may form a substrate for the transistor device. In an alternative embodiment a further substrate layer is provided below the layer 50 in vertical direction (not shown in Figure 2).
  • the compressible layer 50 may be any of a variety of suitable compressible plastics. Examples of suitable plastics for the compressible layer 50 include polyester (PET), polyamide (Pi), polystyrene (PS), polycarbonate (PC), polymethayl methacrylatl (PMMA), polyether imide (PEI), poiytetraflouroethylene (PTFE/Teflon) or polyetheretherketone (PEEK). Also other insulating materials may be used, to which materials it is possible to produce a permanent deformation by embossing in suitable conditions.
  • the conductive layer and the electrodes 60, 80, 90 may be any of a variety of suitable conductive materials for forming electrode patterns of thin- film transistor structures.
  • suitable conductive materials for forming electrode patterns of thin- film transistor structures.
  • transparent semiconductor oxides, metals, or conducting polymers may be applied.
  • the conductor material may be metal or carbon particle ink.
  • Figures 3a to 3c illustrate an embossing method according to an embodiment to separate electrodes of a thin-film device, such as electrodes for the transistor device 100 of Figure 2.
  • input material comprising at least the conductive layer 55 and a compressible layer 50 is provided.
  • a tool which may be referred to as an embossing mold or a pressing plate 110, comprising at least two protrusions, which may be referred to as stamps 112, 114, is provided for driving a portion of the conductive layer material 55 into the compressible layer material 50.
  • the pressing plate 110 may be an independent plate or part of an endless rotated metal belt, for instance.
  • the tool 110 may be manufactured by etching. However, also other manufacturing methods may be used. Electron beam lithography and/or optical patterning may be applied for forming the protrusion 1 12, 114 patterning. For instance, electron beam lithography may be used for features requiring highest resolution and optical patterning may be used for forming larger stamp features.
  • Figure 3b illustrates the embossing operation by the pressing plate 110 at suitable conditions, such as temperature.
  • the pressing plate 110 is brought into contact with the input material.
  • the pressing plate 110 drives the conductive material 55 to the compressible material 50.
  • the compressible material is deformed and the stamps 112 and 114 break the conductive layer 55 to separate the electrodes, in the present embodiment the gate 60, the source 80 and the drain 90.
  • the pressing plate 110 is then removed from the embossed transistor device 100.
  • Suitable de-embossing technique(s) may be applied to ensure an effective and defect free separation of the pressing plate 110 from the embossed component.
  • a suitable type of cooling is applied prior to the separation, in order to ensure that the deformed material 50 is sufficiently cooled to maintain the gap between the gate 60 and the source 80 and the gap between the gate 60 and the drain 90.
  • the thin-film transistor (TFT) channel is generally preferable to be made as narrow as possible, in order to improve electrical performance, i.e. switching speed of the device. According to the present embodiment this is now achieved with only one manufacturing step as both imprints 64, 66 in Figures 2 or 3b, 3c are achieved using the same tool 1 10 that needs to be applied only once per transistor. Therefore, the channel length is defined by the tool 1 10 and this is the key to provide smaller channel length and/or better repeatable accuracy in the manufacturing method according to the present embodiment as compared to methods taught by prior art.
  • embossing of all electrodes 60, 80, 90 is done in a single embossing step, there is no need for alignment between successive steps, which increases manufacturing simplicity and and enables very high transistor- to-transistor repeatability. Further, it is possible to manufacture smaller transistor channels accurately with manufacturing tools that are suitable for large-scale manufacturing. It is expected that minimum channel lengths in the range of 0.1-50 ⁇ m can be readily achieved by the present method. Such narrow channel increases transistor performance and such transistors are well suitable for manufacturing of radio frequency identification RFID circuitry, for instance. Especially useful for very narrow transistor channel configurations is that it is easier to use all three electrodes 60, 80, 90 of the transistor for further contacts, and high resolution tools are not necessarily needed.
  • a further advantage is that, since electrodes do not make overlap, it is possible to obtain small stray capacitances leading to higher speed.
  • the patterning of the conductive layer 55 may include patterning of multiple transistor devices that are part of a larger structure. That is, while electrodes of only one transistor are shown, there may be numerous transistors that are part of the device being manufactured. The embossing operation may also serve to separate different transistors on the same substrate.
  • nanoimprint lithography which may also be referred to as hot embossing or thermoplastic embossing, is applied.
  • the compressible layer 10, 50 is cured by heating during the embossing process.
  • the pressing plate 1 10 is, instead of or in addition to the heating of the compressible layer 10, 50, heated prior to being brought into contact with the conductive layer 55 ( Figure 3a).
  • the plate 1 10 may be made of a thermally-conductive material, such as a metal.
  • the compressible layer 10, 50 such as substrate of a polymer layer on a substrate, is thus molded under pressure and heat.
  • the temperature of inputted polymer film is raised just above the glass transition temperature before or while the stamp is being pressed against the polymer film. During the pressing, the temperature is lowered below the glass transition temperature to maintain the structure.
  • photo nanoprint lithography is applied, whereby the compressible layer 10, 50 is cured by heating or ultraviolet UV light during the embossing process.
  • a still further applicable method is electrochemical nanoimprinting using a stamp 112, 114 made from a superionic conductor, such as silver sulfide.
  • a stamp 112, 114 made from a superionic conductor, such as silver sulfide.
  • the present embossing features may be applied also in various other current and future embossing or imprinting methods.
  • the embossing step produces a gate having at least two areas having different widths, which herein refers to the distance between the imprinted lines 72, 74.
  • Figure 4 illustrates a top-view of a transistor according to an embodiment.
  • the gate 60 separated by embossing has a channel portion 68 separating the transistor channel and a contact portion 70 for electrical contact to the gate 60.
  • the contact portion 70 is, when viewing the transistor structure from top, wider than the channel portion 68.
  • the single embossing operation is adapted to produce the two embossed lines 72, 74 having a first distance within the gate portion 62 and a second distance, greater than the first distance, within the contact portion 70.
  • Illustrative contacts 84, 94, and 76 for the source 80, the drain 90, and the gate 60, respectively, are depicted in Figure 4.
  • the increased area of the contact portion 70 for the gate 60 further improves electrical contactibility of the gate 60, and the advantages of the present single-embossing step method are still achieved.
  • the present embossing arrangement producing electrodes having variable width, it becomes easier to arrange further electrical contacts.
  • the gate electrode may be large at a distance, a micrometer size channel may be imprinted by using the single embossing step.
  • the first distance and the second distance are substantially invariable and there is also a third portion between the channel portion 68 and the contact portion 70 extending between the channel portion 68 and the contact portion 70, i.e. then forming a (upturned) Y- shape. It is evident that this third portion may be considered as belonging to the contact portion, and that various other shapes may be used to produce the contact portion having greater distance between the two embossed lines than that of the channel portion.
  • An electrode structure as illustrated in Figure 4 can be produced by a single imprinting step by applying a suitably formed protrusions or stamps 112, 114 within the embossing tool 110.
  • the distance between the stamps 112, 1 14 would be substantially invariable at the channel portion 68 to separate the gate 60 from the source 80 and the drain 90, but then the distance would increase to form the contact portion 70 having a greater width than the channel width.
  • the tool 1 10 produces two unitary embossed lines together forming a (upturned) Y-shaped gate electrode.
  • the patterning is a part of a roll-to-roll process.
  • Figure 5 illustrates an example of a manufacturing method and means for an apparatus for roll-to-roll electronic thin-film component manufacturing process system 150, such as manufacturing of transistors according Figures 2, 3, 4, or 6 to 9.
  • a web of input film 170 is obtained from a first rotated roll 160 and the embossed film web is rolled on a second rotated roll 162.
  • the input material for the embossing process from the first roll 160 comprises at least the compressible layer, but may also comprise further layers, such as a separate substrate and/or a conductive layer.
  • the embossing operation is arranged by means of two rollers 180 and 182.
  • a belt 190 including protrusions, such as stamps 112, 114 illustrated in Figures 3a to 3c, may move around the two rollers 180, 182 which advance the belt at a predetermined controlled speed or rate.
  • stamps 112, 114 illustrated in Figures 3a to 3c may move around the two rollers 180, 182 which advance the belt at a predetermined controlled speed or rate.
  • stamps 112, 114 illustrated in Figures 3a to 3c may move around the two rollers 180, 182 which advance the belt at a predetermined controlled speed or rate.
  • stamps 112, 114 illustrated in Figures 3a to 3c may move around the two rollers 180, 182 which advance the belt at a predetermined controlled speed or rate.
  • stamps 112, 114 illustrated in Figures 3a to 3c may move around the two rollers 180, 182 which advance the belt at a predetermined controlled speed or rate.
  • a preparation station 200 prepares or cures
  • the preparation station 200 may heat the input material from the first roll 160 to a suitable temperature for deformation of a thermo-compressible material layer 50 of the input material.
  • the rollers 180, 182 and/or the belt 190 is heated.
  • the station 200, or a further station may also be provided to form the conductive layer 55 on top of the flexible layer 50 by a suitable coating process.
  • Embossing occurs on the web of input material 170 as it and the belt 190 pass around the roller 180 and while pressure is applied by one or more pressure rollers causing the input film 170 to be pressed onto the protrusions of the belt 190 and to partially deform.
  • a backing support plate, belt or film may be pressed against the non-embossed surface of the film.
  • the source 80, gate 60 and drain 90 electrodes are separated by embossing at selected positions of the metal lines by means of the suitably patterned belt 190.
  • the protrusions of the belt 190 are formed such that the embossing operation causes, for at least one of these electrodes being separated by embossing, that only portion of the conductive layer defining such at least one electrode being embossed.
  • a cooling station or other suitable detachment preparation station 210 may be provided between the two rollers 180, 182.
  • the embossed film which may have been laminated to other films during the embossing process, is thus cooled and then moved to the second rotated roll 162.
  • the apparatus 150 configured for at least the embossing operation is controlled by a computer-based control block, control unit, or controller.
  • controller may be implemented by a suitably programmed computer program and executed in a processor of the apparatus.
  • the computer program may be stored on a computer program storage medium, such as an internal memory of the apparatus or an external memory connectable to the apparatus.
  • a specific hardware unit which may embody software-controlled features, in one embodiment controls at least some of the steps for manufacturing electronic thin-film components according to embodiments.
  • Figures 6 to 8 illustrate some further embodiments of transistor structures in which only a portion of a transistor electrode is embossed.
  • Figure 6 illustrates that the embossing operation may be performed by rectangular stamps.
  • two embossed lines 64, 66 substantially entirely on a same vertical level, may be produced.
  • FIG 7 an embodiment is illustrated, where the embossing is applied to an edge 82 of a conductive layer portion forming a source 80 and to an edge 92 of a conductive layer portion forming a drain 80.
  • the gate electrode 60 is separated by two embossed lines, but the entire gate electrode 60 is easily available for further contacts.
  • the structure of Figure 7 is well suitable for narrow imprinted structures as the distance between the source and the drain defines the thin-film transistor (TFT) channel and the gap between the source and drain electrodes 80, 90 to the gate electrode 60 must be small.
  • TFT thin-film transistor
  • Figure 8 illustrates a further embodiment of a transistor device.
  • a dielectric layer 220 is formed on top of the embossed gate electrode 60 to form an insulator.
  • the dielectric 220 on the gate electrode 60 may be fabricated in various ways. For instance, a masking process may be used where the preceding embossing step is used for defining the dielectric area. Depending on the metal applied, anodisation may be used to grow an insulator on the gate electrode 60.
  • Electroplating may be used to grow a different metal onto the source electrode 80 and the drain electrode 90 (not shown in Figure 8). These electrodes 80, 90 may be treated for obtaining ohmic contact.
  • Semiconductive material is deposited on top of the dielectric layer 220, the source 80 and the drain 90 to form a semiconductor 230.
  • suitable semiconductor materials are various polymeric semiconductor materials, such as polythiophene and polyacetylene.
  • the semiconductor 230 may be printed or patterned. However, it will be appreciated that other suitable semiconductive materials and/or deposition methods may be applied.
  • the semiconductor 230 can be deposited over the channel area. As illustrated in Figure 9, the width of the semiconductor 230 defines the transistor channel width. In another embodiment the semiconductor
  • the transistor channel width is the same as the printed layer width, which means less need for high accuracy alignment.
  • the dielectric layer 220 or the dielectric layer 220 and the semiconductor may be added during the embossing process, for instance as part of the system and method illustrated in Figure 5.
  • the configuration of Figure 8 is only one example of further material layers.
  • the semiconductor 230 may be also extend over the drain and source electrodes 80, 90.
  • Figure 8 illustrates the possibility to use a separate substrate layer 240 underneath the compressible layer 50.
  • This substrate may be part of the originally inputted material, such as the material from the first roll
  • the additional substrate layer 240 may have a higher glass transition temperature than the flexible layer 50.
  • plastics such as polyester
  • FIG. 9 further illustrates a top-view of a transistor device with a semiconductor 230 placed on top of the electrodes 60, 80, 90 embossed according to an embodiment.
  • a transistor device with a semiconductor 230 placed on top of the electrodes 60, 80, 90 embossed according to an embodiment.
  • FIGs illustrate only some examples of possible forms of the stamps 112, 1 14 and the cavities formed by the stamps. It is possible to provide various other shapes, such as U-shaped stamps or stamps having curved edges. Further, it is possible to combine these embodiments in various ways.
  • the present embossing features may be applied also for other transistor electrode configurations. For instance, a gate may be added at a separate step after only the source and drain electrodes have been embossed by a single embossing operation.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

Selon un aspect, l'invention porte sur un procédé de gaufrage de composants à couches minces électroniques. Un matériau d'entrée comprenant une couche compressible et une couche conductrice sur la couche compressible est utilisé. Une opération de gaufrage est effectuée sur la couche conductrice afin de séparer galvaniquement des parties de la couche conductrice pour former un motif d'électrode, l'opération de gaufrage étant appliquée pour former, par une seule opération de gaufrage, une électrode séparée par au moins deux lignes gaufrées.
PCT/FI2008/050695 2008-11-27 2008-11-27 Gaufrage de composants à couches minces électroniques Ceased WO2010061035A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/FI2008/050695 WO2010061035A1 (fr) 2008-11-27 2008-11-27 Gaufrage de composants à couches minces électroniques

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/FI2008/050695 WO2010061035A1 (fr) 2008-11-27 2008-11-27 Gaufrage de composants à couches minces électroniques

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WO2010061035A1 true WO2010061035A1 (fr) 2010-06-03

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6517995B1 (en) * 1999-09-14 2003-02-11 Massachusetts Institute Of Technology Fabrication of finely featured devices by liquid embossing
US20040075155A1 (en) * 2002-10-17 2004-04-22 Zhisong Huang Method of fabricating transistor device
US6911385B1 (en) * 2002-08-22 2005-06-28 Kovio, Inc. Interface layer for the fabrication of electronic devices
US20060157443A1 (en) * 2005-01-18 2006-07-20 Ping Mei Pattern reversal process for self aligned imprint lithography and device
EP1748502A1 (fr) * 2005-07-28 2007-01-31 Sony Corporation Dispositif semi-conducteur et procédé de fabrication dudit dispositif
WO2007074404A2 (fr) * 2005-11-14 2007-07-05 Ciba Holding Inc. Procede et appareil de formation de motifs d'une couche conductrice, et dispositif ainsi obtenu

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6517995B1 (en) * 1999-09-14 2003-02-11 Massachusetts Institute Of Technology Fabrication of finely featured devices by liquid embossing
US6911385B1 (en) * 2002-08-22 2005-06-28 Kovio, Inc. Interface layer for the fabrication of electronic devices
US20040075155A1 (en) * 2002-10-17 2004-04-22 Zhisong Huang Method of fabricating transistor device
US20060157443A1 (en) * 2005-01-18 2006-07-20 Ping Mei Pattern reversal process for self aligned imprint lithography and device
EP1748502A1 (fr) * 2005-07-28 2007-01-31 Sony Corporation Dispositif semi-conducteur et procédé de fabrication dudit dispositif
WO2007074404A2 (fr) * 2005-11-14 2007-07-05 Ciba Holding Inc. Procede et appareil de formation de motifs d'une couche conductrice, et dispositif ainsi obtenu

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