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WO2010058561A1 - Transistor à effet de champ - Google Patents

Transistor à effet de champ Download PDF

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Publication number
WO2010058561A1
WO2010058561A1 PCT/JP2009/006176 JP2009006176W WO2010058561A1 WO 2010058561 A1 WO2010058561 A1 WO 2010058561A1 JP 2009006176 W JP2009006176 W JP 2009006176W WO 2010058561 A1 WO2010058561 A1 WO 2010058561A1
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Prior art keywords
semiconductor layer
layer
dislocation density
threading dislocation
nitride semiconductor
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Japanese (ja)
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田中健一郎
上田哲三
松尾尚慶
引田正洋
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Panasonic Corp
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Panasonic Corp
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Priority to CN2009801463633A priority Critical patent/CN102224581A/zh
Publication of WO2010058561A1 publication Critical patent/WO2010058561A1/fr
Priority to US13/111,357 priority patent/US20110278540A1/en
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    • H—ELECTRICITY
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
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    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02538—Group 13/15 materials
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/675—Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
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    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
    • H10D62/8161—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices
    • H10D62/8162—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation
    • H10D62/8164—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation comprising only semiconductor materials 
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
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    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

  • the present invention relates to a field effect transistor using a nitride semiconductor applicable to a power transistor used in a power circuit of a consumer device such as an air conditioner.
  • Nitride semiconductors have larger band gaps, breakdown electric fields, and electron saturation drift rates than Si and GaAs. Further, in an AlGaN / GaN heterostructure formed on a substrate having a (0001) plane as a main surface, two-dimensional electron gas is generated at the heterointerface due to spontaneous polarization and piezopolarization, and 1 ⁇ 10 13 cm without any doping. A sheet carrier concentration of -2 or higher is obtained. High electron mobility transistors (HEMTs) using this high-concentration two-dimensional electron gas as a carrier have recently attracted attention, and HEMTs having various structures have been proposed.
  • HEMTs High electron mobility transistors
  • FIG. 13 is a cross-sectional view showing a conventional field effect transistor 700 having an AlGaN / GaN heterostructure (see, for example, Patent Document 1).
  • a low-temperature AlN buffer layer 702, an undoped GaN layer 703, and an undoped AlGaN layer 704 are formed in this order on a Si substrate 701.
  • a source electrode 705 and a drain electrode 707 made of a Ti layer and an Al layer are formed on the undoped AlGaN layer 704.
  • a gate electrode 706 made of a Ni layer, a Pt layer, and an Au layer is formed between the source electrode 705 and the drain electrode 707.
  • a SiN layer (not shown) is formed as a passivation film.
  • a two-dimensional electron gas formed at the interface between the undoped AlGaN layer 704 and the undoped GaN layer 703 is used as a carrier.
  • a voltage is applied between the source and drain, electrons in the channel move from the source electrode 705 toward the drain electrode 707.
  • the voltage applied to the gate electrode 706 and changing the thickness of the depletion layer immediately below the gate electrode 706 electrons moving from the source electrode 705 to the drain electrode 707, that is, the drain current can be controlled. It becomes.
  • an object of the present invention is to provide a field effect transistor capable of suppressing current collapse.
  • a field effect transistor according to the present invention is formed on a first semiconductor layer made of a first nitride semiconductor and the first semiconductor layer, and the first nitride semiconductor is formed. And a second semiconductor layer made of a second nitride semiconductor having a larger band gap than the first semiconductor layer, wherein the first semiconductor layer has a region in which threading dislocation density increases in the stacking direction.
  • the threading dislocation density at the joint surface between the first semiconductor layer and the second semiconductor layer is 2 ⁇ 10 9 cm ⁇ 2 or more.
  • the threading dislocation density of the first semiconductor layer in the channel is increased and the current collapse is not deteriorated. can do.
  • a field effect transistor capable of suppressing current collapse can be realized.
  • the first semiconductor layer includes a third semiconductor layer, a crystallinity control layer formed on the third semiconductor layer, a fourth semiconductor layer formed on the crystallinity control layer, In the crystalline control layer, the threading dislocation density may increase in the stacking direction, and the threading dislocation density of the fourth semiconductor layer may be larger than the threading dislocation density of the third semiconductor layer.
  • the thickness of the first semiconductor layer can be increased by using a part of the first semiconductor layer as a layer having a high threading dislocation density and the other as a layer having a low threading dislocation density. As a result, it is possible to achieve both high breakdown voltage and suppression of current collapse.
  • the first semiconductor layer may have a region where the threading dislocation density decreases in the stacking direction.
  • the threading dislocation density at the joint surface between the first semiconductor layer and the second semiconductor layer is lowered to 1.6 ⁇ 10 10 cm ⁇ 2 or less, and the sheet resistance is suppressed to a practically usable range. it can.
  • the thickness of the first semiconductor layer can be increased, a high withstand voltage field effect transistor can be realized.
  • the film thickness of the first semiconductor layer may be 2 ⁇ m or more.
  • a high breakdown voltage field effect transistor capable of suppressing current collapse can be realized.
  • FIG. 1 is a cross-sectional view schematically showing a configuration of a HEMT as a nitride field effect transistor according to an embodiment of the present invention.
  • FIG. 2 is a diagram illustrating the relationship between the full width at half maximum of the (1012) line of the X-ray rocking curve and the current collapse degree R af / R bf .
  • FIG. 3 is a diagram showing the relationship between the threading dislocation density and the full width at half maximum of the (1012) line of the X-ray rocking curve.
  • FIG. 4 is a graph showing the relationship between the full width at half maximum of the (1012) line of the X-ray rocking curve and the sheet resistance of the channel.
  • FIG. 1 is a cross-sectional view schematically showing a configuration of a HEMT as a nitride field effect transistor according to an embodiment of the present invention.
  • FIG. 2 is a diagram illustrating the relationship between the full width at half maximum of the (1012) line of the X
  • FIG. 5 is a graph showing the relationship between the full width at half maximum of the (1012) line of the X-ray rocking curve and the film thickness of the first nitride semiconductor layer.
  • FIG. 6 is a cross-sectional view schematically illustrating the configuration of the HEMT according to the first embodiment.
  • FIG. 7 is a graph schematically showing how the full width at half maximum of the X-ray (1012) line changes in the stacking direction in the HEMT according to each example.
  • FIG. 8 is a cross-sectional view schematically illustrating the configuration of the HEMT according to the second embodiment.
  • FIG. 9 is a cross-sectional view schematically showing a configuration of a modified example of the HEMT according to the second embodiment.
  • FIG. 10 is a cross-sectional view schematically illustrating a configuration of a modified example of the HEMT according to the second embodiment.
  • FIG. 11 is a cross-sectional view schematically illustrating the configuration of the HEMT according to the third embodiment.
  • FIG. 12 is a cross-sectional view schematically illustrating the configuration of the HEMT according to the fourth embodiment.
  • FIG. 13 is a cross-sectional view schematically showing a configuration of a conventional field effect transistor.
  • FIG. 1 is a cross-sectional view schematically showing a configuration of a HEMT 100 as a field effect transistor according to an embodiment of the present invention.
  • the HEMT 100 includes a first nitride semiconductor layer 103 and a second nitride semiconductor layer 104 that are sequentially stacked on a substrate 101 via a buffer layer 102.
  • the HEMT 100 includes a source electrode 107, a gate electrode 108, and a drain electrode 109, which are formed side by side on the second nitride semiconductor layer 104.
  • the first nitride semiconductor layer 103 is an example of the first semiconductor layer of the present invention, and is a layer made of the first nitride semiconductor formed on the buffer layer 102.
  • the second nitride semiconductor layer 104 is an example of the second semiconductor layer of the present invention, and is formed on the first nitride semiconductor layer 103 and has a band gap larger than that of the first nitride semiconductor.
  • 2 is a layer made of a nitride semiconductor.
  • the first nitride semiconductor layer 103 included in the HEMT 100 will be described.
  • the present inventors predicted that the channel crystallinity of the first nitride semiconductor layer 103 in the HEMT 100 has a correlation with the current collapse. Therefore, a plurality of HEMTs 100 having the structure shown in FIG. 1 are manufactured by changing the crystallinity of the first nitride semiconductor layer 103, and the X-ray rocking curve (1012) line of the first nitride semiconductor layer 103 is produced. The correlation between full width at half maximum and current collapse was investigated. As the measurement sample, the first nitride semiconductor layer 103 made of GaN having a thickness of 2 ⁇ m was used.
  • FIG. 2 is a graph showing the relationship between the full width at half maximum of the (1012) line of the X-ray rocking curve and the current collapse degree R af / R bf .
  • the full width at half maximum of the (1012) line of the X-ray rocking curve represents the full width at half maximum of the rocking curve obtained by X-ray diffraction with respect to the (1012) plane measured in the ⁇ scan mode.
  • the X-rays used when acquiring the rocking curve need not be interpreted as being limited to Cu K ⁇ rays, and other X-rays such as Mo K ⁇ rays may be used.
  • the method of measuring the current collapse degree shown in FIG. 2 is as follows.
  • a source electrode 107 is applied with 0V
  • a gate electrode 108 is applied with 0V
  • a substrate 101 is applied with 0V
  • a drain electrode 109 is applied with 2V. Is R bf .
  • -5 V is once applied to the gate electrode 108 and 200 V is applied to the drain electrode 109 to turn off the HEMT 100 and hold it for 30 seconds.
  • a voltage of 2 V is applied again to the drain electrode 109, the resistance between the source and the drain is measured, and this is defined as Raf .
  • This increase rate R af / R bf can be handled as an index representing the magnitude of current collapse.
  • the current collapse is poor when the current collapse degree R af / R bf is large, and the current collapse is good when the value is small.
  • the current collapse degree increases (current collapse deteriorates).
  • the full width at half maximum of the (1012) line of the X-ray rocking curve is 800 arcsec or less, the current collapse is significantly deteriorated. Therefore, the first nitride semiconductor layer 103 is formed so that the full width at half maximum of the (1012) line of the X-ray rocking curve is 800 arcsec or more at the joint surface with the second nitride semiconductor layer 104.
  • the full width at half maximum of the (1012) line of the X-ray rocking curve is 800 arcsec or more.
  • the full width at half maximum of the (1012) line of the X-ray rocking curve of the first nitride semiconductor layer 103 can correspond to the threading dislocation density existing in the first nitride semiconductor layer 103.
  • FIG. 3 shows the relationship between the full width at half maximum of the (1012) line of the X-ray rocking curve of the first nitride semiconductor layer 103 and the threading dislocation density present in the first nitride semiconductor layer 103 (
  • Non-Patent Document 1 P. Gay, P. B. Hirsch, A. Kelly, Acta Metal, 1 (1953), 315.).
  • the first nitride semiconductor layer 103 has a full width at half maximum of 800 arcsec or more of the (1012) line of the X-ray rocking curve.
  • the threading dislocation density of the first nitride semiconductor layer 103 is 2 ⁇ 10 9. Can be converted to cm -2 or more. Therefore, the first nitride semiconductor layer 103 is a junction surface with the second nitride semiconductor layer 104, preferably a portion in contact with the second nitride semiconductor layer 104 functioning as a channel, and the threading dislocation density is 2 ⁇ . It is formed to be 10 9 cm ⁇ 2 or more.
  • FIG. 4 is a graph showing the relationship between the full width at half maximum of the (1012) line of the X-ray rocking curve and the sheet resistance of the channel.
  • the sheet resistance of the first nitride semiconductor layer 103 as a channel increases. There is a tendency to go.
  • the sheet resistance is 1200 ⁇ / sq.
  • the full width at half maximum of the (1012) line of the X-ray rocking curve needs to be 1900 arcsec or less.
  • the full width at half maximum of the (1012) line of this X-ray rocking curve of 1900 arcsec or less can be converted to 1.6 ⁇ 10 10 cm -2 or less from FIG.
  • the first nitride semiconductor layer 103 is formed so that the threading dislocation density is 1.6 ⁇ 10 10 cm ⁇ 2 or less at the joint surface with the second nitride semiconductor layer 104.
  • the threading dislocation density is 1.6 ⁇ 10 10 cm ⁇ 2 or less at a portion of the first nitride semiconductor layer 103 that functions as a channel and in contact with the second nitride semiconductor layer 104.
  • the withstand voltage of the HEMT 100 is 400 V or less and does not have a practically sufficient withstand voltage. This is because breakdown between the source and the drain occurs through the conductive substrate 101 when a strong voltage is applied between the source and the drain. Therefore, in order to manufacture the HEMT 100 having a higher breakdown voltage, it is necessary to increase the breakdown voltage between the source and the substrate and between the drain and the substrate, that is, to increase the thickness of the first nitride semiconductor layer 103.
  • the required film thickness of the first nitride semiconductor layer 103 is, for example, 4 ⁇ m or more when a breakdown voltage of 800 V or more is required as the breakdown voltage of the HEMT 100, and 3 ⁇ m when a breakdown voltage of 600 V or more is required. As described above, when a breakdown voltage of 400 V or more is required, a film thickness of 2 ⁇ m or more is desirable. However, as shown in the graph showing the relationship between the film thickness of the first nitride semiconductor layer 103 and the full width at half maximum of the (1012) line of the X-ray rocking curve in FIG.
  • the inventor has described the first nitride semiconductor layer. It was found that current collapse is improved by inserting a layer for widening the full width at half maximum of the (1012) line of the X-ray rocking curve as a part of 103. Accordingly, a region in which the threading dislocation density for increasing the full width at half maximum of the (1012) line of the X-ray rocking curve increases in the stacking direction is provided in the first nitride semiconductor layer 103.
  • the region where the threading dislocation density increases in the stacking direction may be provided in a minute region of the first nitride semiconductor layer 103 in the stacking direction, but the direction perpendicular to the stacking direction (in-plane direction) ) Is preferably provided in a region having a width equal to or larger than a predetermined width of the first nitride semiconductor layer 103. Specifically, it is preferably provided in a region having a width in the in-plane direction that is half or more of the distance between the source electrode 107 and the drain electrode 109.
  • a region where the threading dislocation density increases in the stacking direction is provided over substantially the entire region in the in-plane direction, that is, substantially the entire region where the channel is formed.
  • the first nitride semiconductor layer 103 is preferably further provided with a region where the threading dislocation density decreases in the stacking direction.
  • the thickness of the first nitride semiconductor layer 103 is preferably set to 2 ⁇ m or more in order to increase the breakdown voltage.
  • the threading dislocation density at the joint surface between the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104 is 2 ⁇ 10 9 cm ⁇ 2 or more and 1. It is formed to be 6 ⁇ 10 10 cm ⁇ 2 or less. Therefore, current collapse can be suppressed while suppressing sheet resistance to a practically usable range.
  • the nitride semiconductor layer 103 is a region having a high threading dislocation density of 2 ⁇ 10 9 cm ⁇ 2 or more in the range of 100 nm from the junction surface with the second nitride semiconductor layer 104, and the other regions have low threading dislocations. It is considered as a density area. Therefore, both high breakdown voltage and suppression of current collapse can be achieved.
  • Example 1 An application example of the HEMT 100 of the present embodiment is shown by Example 1.
  • FIG. 6 is a cross-sectional view schematically showing the configuration of the HEMT 200 according to the present embodiment.
  • the HEMT 200 includes an undoped GaN layer 203, a crystallinity control layer 204, an undoped GaN layer 205, and an undoped AlGaN layer 206 that are sequentially stacked on a substrate 201 via a buffer layer 202.
  • the undoped GaN layer 203 is an example of the third semiconductor layer of the present invention
  • the undoped GaN layer 205 is an example of the fourth semiconductor layer of the present invention.
  • the substrate 201 is, for example, a Si substrate, a SiC substrate, a sapphire substrate, a GaN substrate, or the like.
  • the buffer layer 202 is a semiconductor layer made of, for example, AlN formed by low temperature growth.
  • the crystallinity control layer 204 is a semiconductor layer made of a superlattice structure composed of undoped AlN and GaN. In the crystallinity control layer 204, the threading dislocation density increases in the stacking direction.
  • the “superlattice structure” here is a structure in which, for example, a pair of AlN having a thickness of 5 nm and GaN having a thickness of 20 nm is paired, and 20 pairs thereof are alternately stacked.
  • the film thickness of the undoped GaN layer 203 is, for example, 1.5 ⁇ m, and the film thickness of the undoped GaN layer 205 is, for example, 1 ⁇ m.
  • the threading dislocation density decreases in the stacking direction. However, since the threading dislocation density is increased in the crystalline control layer 204, the threading dislocation density of the undoped GaN layer 205 formed above the crystalline control layer 204 is the threading dislocation density of the undoped GaN layer 203 formed below. Larger than
  • the undoped GaN layer 203, the crystallinity control layer 204, and the undoped GaN layer 205 constitute the first nitride semiconductor layer 103 in the HEMT 100 of this embodiment.
  • the undoped AlGaN layer 206 constitutes the second nitride semiconductor layer 104 in the HEMT 100 of the present embodiment.
  • the HEMT 200 further includes a source electrode 207, a gate electrode 208, and a drain electrode 209 formed side by side on the undoped AlGaN layer 206.
  • the source electrode 207 and the drain electrode 209 as ohmic electrodes are each composed of a Ti layer and an Al layer stacked on the undoped AlGaN layer 206.
  • the gate electrode 208 as a Schottky electrode is composed of a Pt layer and an Au layer stacked on the undoped AlGaN layer 206.
  • a schematic diagram of the film thickness direction dependence of threading dislocation density in the HEMT 200 according to this example is shown in a curve 800 in FIG. 7G, and a schematic diagram of a crystal structure is shown in FIG. 7A.
  • the undoped GaN layer 203 monotonously decreases the threading dislocation density in the stacking direction (GaN growth direction).
  • the threading dislocation is caused by the superlattice structure of the crystalline control layer 204.
  • the density increases once.
  • the threading dislocation density is decreased again in the stacking direction (GaN growth direction) by the undoped GaN layer 205.
  • the X-ray rocking curve (1012) at the junction surface of the undoped GaN layer 205 with the undoped AlGaN layer 206 is obtained.
  • the full width at half maximum of the line is 1000 arcsec, which is 4.4 ⁇ 10 9 cm ⁇ 2 in terms of threading dislocation density.
  • the current collapse degree R af / R bf 2.8 was achieved, and it was at a level where there was no practical problem. Further, the first nitride semiconductor layer 103 as a whole became 2.5 ⁇ m, and the withstand voltage at this time was 500 V, which could exceed the withstand voltage of 400 V required for a Japanese commercial power supply.
  • the crystallinity of the channel is controlled by the crystallinity control layer 204, and the threading dislocation density is 2 ⁇ 10 9 cm ⁇ 2 or more and 1.6 ⁇ 10 10 cm ⁇ 2 or less. It is adjusted to become. Therefore, current collapse can be suppressed while suppressing sheet resistance to a practically usable range.
  • an undoped GaN layer 203 and an undoped GaN layer 205 in which the threading dislocation density monotonously decreases in the stacking direction are provided. Therefore, both high breakdown voltage and suppression of current collapse can be achieved.
  • Example 2 An application example of the HEMT 100 of the present embodiment is shown by Example 2.
  • FIG. 8 is a cross-sectional view schematically showing the configuration of the HEMT 300 according to the present embodiment.
  • the HEMT 300 includes an undoped GaN layer 303, a crystallinity control layer 304, and an undoped AlGaN layer 206, which are sequentially stacked on a substrate 201 via a buffer layer 202.
  • the HEMT 300 further includes a source electrode 207, a gate electrode 208, and a drain electrode 209 formed side by side on the undoped AlGaN layer 206.
  • the crystallinity control layer 304 is a semiconductor layer made of, for example, 1 ⁇ m of GaN, and crystallizes GaN at a lower temperature (900 ° C. to 1000 ° C.) or higher temperature (1040 ° C. to 1100 ° C.) than the normal growth temperature of 1020 ° C. It is formed by growing. Therefore, in the crystallinity control layer 304, the threading dislocation density gradually increases in the stacking direction.
  • the film thickness of the undoped GaN layer 303 is 1.5 ⁇ m, for example. Since the undoped GaN layer 303 is a single semiconductor layer that is formed without adding impurities by normal crystal growth, the threading dislocation density decreases in the stacking direction.
  • the undoped GaN layer 303 and the crystallinity control layer 304 constitute the first nitride semiconductor layer 103 in the HEMT 100 of this embodiment.
  • a schematic diagram of the film thickness direction dependence of threading dislocation density in the HEMT 300 according to this example is shown in a curve 801 in FIG. 7G, and a schematic diagram of a crystal structure is shown in FIG. 7B.
  • the threading dislocation density monotonously decreases in the stacking direction (GaN growth direction) by the undoped GaN layer 303, but the stacking direction (GaN growth direction) by the crystalline control layer 304.
  • the threading dislocation density gradually increases.
  • the crystallinity control layer 304 is formed by growing 1 ⁇ m of GaN at a growth temperature of 1050 ° C.
  • the (1012) line of the X-ray rocking curve at the interface between the crystallinity control layer 304 and the undoped AlGaN layer 206 is formed.
  • the full width at half maximum is 1050 arcsec, which is 4.9 ⁇ 10 9 cm ⁇ 2 in terms of threading dislocation density.
  • the current collapse degree R af / R bf of the HEMT 300 becomes 2.7, and the current collapse can be suppressed to a level where there is no practical problem.
  • the first nitride semiconductor layer 103 is composed of the undoped GaN layer 303 and the crystallinity control layer 304, and includes the undoped GaN layer 303 as a region where the threading dislocation density monotonously decreases.
  • the first nitride semiconductor layer 103 may be formed of the crystalline control layer 304 and may include only a region where the threading dislocation density monotonously increases.
  • the structure of the HEMT 300 in this case is schematically shown in the cross-sectional view of FIG. 9, a schematic diagram of the dependency of threading dislocation density on the film thickness direction is shown by a curve 802 in FIG. 7G, and a schematic diagram of the crystal structure is shown. 7 (C).
  • the crystallinity control layer 304 gradually increases the threading dislocation density in the stacking direction (GaN growth direction).
  • the first nitride semiconductor layer 103 includes an undoped GaN layer 303, a crystalline control layer 304, and an undoped GaN layer 305, and includes a region in which the threading dislocation density monotonously decreases on the crystalline control layer 304. May be.
  • the undoped GaN layer 305 is a single semiconductor layer formed without adding impurities by normal crystal growth.
  • the structure of the HEMT 300 in this case is schematically shown in the cross-sectional view of FIG. 10, a schematic diagram of the dependency of threading dislocation density on the film thickness direction is shown by a curve 803 in FIG. 7G, and a schematic diagram of the crystal structure is shown. 7 (D). As shown in FIGS.
  • the crystallinity control layer 304 gradually increases the threading dislocation density in the stacking direction (GaN growth direction), but the undoped GaN layer 305 increases the stacking direction (GaN growth). Direction), the threading dislocation density gradually decreases.
  • Example 3 An application example of the HEMT 100 of the present embodiment is shown in Example 3.
  • FIG. 11 is a cross-sectional view schematically showing the configuration of the HEMT 400 according to the present embodiment.
  • the HEMT 400 includes an undoped GaN layer 203, crystallinity control layers 404 and 405, and an undoped AlGaN layer 206 that are sequentially stacked on a substrate 201 via a buffer layer 202.
  • the HEMT 400 further includes a source electrode 207, a gate electrode 208, and a drain electrode 209 formed side by side on the undoped AlGaN layer 206.
  • the crystallinity control layer 404 is a semiconductor layer made of a superlattice structure composed of undoped AlN and GaN. In the crystallinity control layer 404, the threading dislocation density increases in the stacking direction.
  • the “superlattice structure” here is a structure in which, for example, a pair of AlN having a thickness of 5 nm and GaN having a thickness of 20 nm is paired, and 20 pairs thereof are alternately stacked.
  • the crystallinity control layer 405 is a semiconductor layer made of, for example, 1 ⁇ m of GaN, and crystallizes GaN at a lower temperature (900 ° C. to 1000 ° C.) or higher temperature (1040 ° C. to 1100 ° C.) than the normal growth temperature of 1020 ° C. It is formed by growing. Accordingly, in the crystallinity control layer 405, the threading dislocation density gradually increases in the stacking direction.
  • the undoped GaN layer 203 and the crystallinity control layers 404 and 405 constitute the first nitride semiconductor layer 103 in the HEMT 100 of this embodiment.
  • a schematic diagram of the film thickness direction dependence of threading dislocation density in HEMT 400 according to this example is shown in a curve 804 in FIG. 7G, and a schematic diagram of a crystal structure is shown in FIG. 7E.
  • the undoped GaN layer 203 monotonously decreases the threading dislocation density in the stacking direction (GaN growth direction), but the crystallinity control layer 404 temporarily increases the threading dislocation density. Furthermore, the threading dislocation density gradually increases in the stacking direction (GaN growth direction) by the crystallinity control layer 405.
  • the full width at half maximum of the (1012) line of the X-ray rocking curve at the joint surface between the crystalline control layer 405 and the undoped AlGaN layer 206 is 1080 arcsec, which is 5.2 ⁇ 10 9 cm ⁇ in terms of threading dislocation density. 2
  • the current collapse degree R af / R bf of the HEMT 400 becomes 2.9, and the current collapse can be suppressed to a level where there is no practical problem.
  • Example 4 An application example of the HEMT 100 of the present embodiment is shown in Example 4.
  • FIG. 12 is a cross-sectional view schematically showing the configuration of the HEMT 500 according to the present embodiment.
  • the HEMT 500 includes an undoped GaN layer 203, a crystalline control layer 504, an undoped GaN layer 505, crystalline control layers 506 and 507, which are sequentially stacked on a substrate 201 with a buffer layer 202 interposed therebetween.
  • An undoped AlGaN layer 206 is provided.
  • the HEMT 500 further includes a source electrode 207, a gate electrode 208, and a drain electrode 209 formed side by side on the undoped AlGaN layer 206.
  • the crystallinity control layers 504 and 506 are semiconductor layers made of a superlattice structure composed of undoped AlN and GaN, respectively. In the crystallinity control layers 504 and 506, the threading dislocation density increases in the stacking direction.
  • the “superlattice structure” here is a structure in which, for example, a pair of AlN having a thickness of 5 nm and GaN having a thickness of 20 nm is paired, and 20 pairs thereof are alternately stacked.
  • the undoped GaN layer 505 is a single semiconductor layer that is formed without adding impurities by normal crystal growth, the threading dislocation density decreases in the stacking direction.
  • the film thickness of the undoped GaN layer 505 is, for example, 0.5 ⁇ m.
  • the crystallinity control layer 507 is a semiconductor layer made of, for example, 1 ⁇ m of GaN, and crystallizes GaN at a lower temperature (900 ° C. to 1000 ° C.) or higher temperature (1040 ° C. to 1100 ° C.) than the normal growth temperature of 1020 ° C. It is formed by growing. Therefore, in the crystallinity control layer 507, the threading dislocation density gradually increases in the stacking direction.
  • the undoped GaN layer 203, the crystallinity control layers 504, 506 and 507 and the undoped GaN layer 505 constitute the first nitride semiconductor layer 103 in the HEMT 100 of this embodiment.
  • a schematic diagram of the dependency of threading dislocation density on the film thickness direction in HEMT 500 according to this example is shown in a curve 805 in FIG. 7G, and a schematic diagram of a crystal structure is shown in FIG. 7F.
  • the undoped GaN layer 203 monotonously decreases the threading dislocation density in the stacking direction (GaN growth direction), but the threading dislocations are formed by the superlattice structure of the crystalline control layer 504. The density increases once. Thereafter, the threading dislocation density is once decreased by the undoped GaN layer 505, and then the threading dislocation density is once again increased by the superlattice structure of the crystalline control layer 506, and further the threading dislocation density is gradually increased by the crystalline control layer 507. .
  • the full width at half maximum of the (1012) line of the X-ray rocking curve at the joint surface between the crystalline control layer 507 and the undoped AlGaN layer 206 is 1100 arcsec, which is 5.3 ⁇ 10 9 cm ⁇ in terms of threading dislocation density. 2
  • the current collapse degree R af / R bf of the HEMT 500 becomes 2.5, and the current collapse can be suppressed to a level where there is no practical problem.
  • the first nitride semiconductor layer 103 (GaN layer functioning as a channel) includes a crystalline control layer.
  • the full width at half maximum of the (1012) line of the X-ray rocking curve is between 800 and 1900 arcsec at the joint surface between the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104, and the threading dislocation density is increased. It is not limited to this as long as it is 2 ⁇ 10 9 cm ⁇ 2 or more and 4.4 ⁇ 10 10 cm ⁇ 2 or less.
  • Such a region is formed by appropriately controlling the formation conditions of the first nitride semiconductor layer 103.
  • a GaN layer is crystal-grown on the buffer layer 102 while increasing the flow ratio of ammonia and trimethylgallium (ratio of group V element and group III element), the ratio of group V element and group III element is 1150, and GaN It is formed by growing the layer by 2 ⁇ m.
  • the full width at half maximum of the (1012) line of the X-ray rocking curve in the channel is 950 arcsec, which is 4.0 ⁇ 10 9 cm ⁇ 2 in terms of threading dislocation density.
  • the current collapse degree R af / R bf of the HEMT becomes 3.5, and the current collapse can be suppressed to a level where there is no practical problem.
  • a GaN layer when a GaN layer is crystal-grown on the buffer layer 102, it is formed by doping impurities such as B, As, P or N at an impurity concentration of 10 16 cm ⁇ 3 or more.
  • the formed GaN layer B, As contains an impurity concentration of 10 16 cm -3 or more impurities such as P or N. Due to the difference in size between these dopant atoms and N atoms, the lattice constant of GaN is distorted and dislocations are introduced into the GaN layer.
  • the full width at half maximum of the (1012) line of the X-ray rocking curve in the channel is 850 arcsec, which is 3.2 ⁇ 10 9 cm ⁇ 2 in terms of threading dislocation density.
  • the current collapse degree R af / R bf of the HEMT becomes 3.8, and the current collapse can be suppressed to a level where there is no practical problem.
  • the first nitride semiconductor layer 103 is made of GaN.
  • the present invention is useful as a field effect transistor, and particularly useful as a power transistor used in a power supply circuit of a consumer device such as an air conditioner.

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Abstract

La présente invention concerne un transistor à effet de champ capable de supprimer une chute de courant. Un HEMT (100), qui sert de transistor à effet de champ, comprend : une première couche de semi-conducteur nitrure (103) composée d'un premier semi-conducteur nitrure ; une seconde couche de semi-conducteur nitrure (104) formée sur la première couche de semi-conducteur nitrure (103) et composée d'un second semi-conducteur nitrure qui comporte un intervalle de bande supérieur au premier semi-conducteur nitrure. La première couche de semi-conducteur nitrure (103) possède une région dans laquelle la densité de dislocation traversante augmente dans la direction de stratification.
PCT/JP2009/006176 2008-11-21 2009-11-18 Transistor à effet de champ Ceased WO2010058561A1 (fr)

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JP5788296B2 (ja) 2011-02-22 2015-09-30 コバレントマテリアル株式会社 窒化物半導体基板及びその製造方法
JP5870574B2 (ja) * 2011-09-21 2016-03-01 住友電気工業株式会社 半導体装置、及び半導体装置の製造方法
JP2015176936A (ja) 2014-03-13 2015-10-05 株式会社東芝 半導体装置
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