WO2010054871A1 - Method for testing circuits and subassemblies with programmable logic components by introducing faults - Google Patents

Abstract

Method for testing circuits with programmable logic components (L) by introducing faults, wherein a 2-in-1 multiplexer (M) is connected into a signal path in the hardware description language model (HDL) of the programmable logic component (L), and a fault selection signal (FAS) can be used to change over between the signal (S) and a fault signal FS.

Description

 description

Method for testing circuits and assemblies with programmable logic devices by means of fault insertion,

Technical area

The invention relates to a method for testing circuits and assemblies with programmable logic devices by means of fault insertion.

State of the art

Programmable logic devices, such as CPLD (Complex Programmable Logic Device) or FPGA (Field Programmable Gate Array) are used when specific circuit functions are to be achieved without the availability of standard components and implementation of the circuit functions by means of arithmetic units (microcontrollers) is not expedient , The determination of the functions of programmable logic components is made by means of the creation of a so-called hardware description language model, which is translated by means of a synthesis tool into usable information from the respective logic component and loaded into the logic component.

If such programmable logic components are used in safety-critical applications, the test of these logic components is of particular importance. For example, the IEC 61508 family of standards defines requirements Safety-related programmable electronic systems that can only be met with proof by means of faulty installation (fault insertion). Specific errors are introduced into the hardware and the behavior of the system is documented and used for further improvement.

The usual procedure for microcontroller error installation can not be applied to programmable logic devices, as these inherently run no programs. The so-called "scan-based" testing, which is common for the testing of ASICs (application-specific integrated circuit), is in principle also applicable to programmable logic components, but involves a large number of problems, in particular increasing the complexity of the

Hardware description model and the size of the synthesized circuit. Furthermore, the provision of scan-based testing significantly restricts the hardware design. For example, only full-synchronous hardward designs are possible and switching off the clock of individual parts of the circuit (clock gating) is not possible.

Method for verifying a safety-relevant PLD-based system by means of fault introduction

The method described is used in the development process to verify that the system has been properly designed and implemented. It is not intended to test whether a mass-produced copy of the system was made correctly.

Presentation of the invention The invention is therefore based on the object of specifying a method for testing circuits and assemblies with programmable logic components by means of error insertion.

The object is achieved by a method according to claim 1 and a programmable logic component having the features of claim 2.

In accordance with the basic idea of the invention, when creating the hardware description language model of a programmable logic component in the signal path of a signal which is to be modified for test purposes, a 2-in multiplexer is connected. An error signal is switched to the second input of this 2-in-1 multiplexer and an error selection signal is switched to the selection input. By means of this error select signal, it is possible to switch between the signal and the error signal and to pass either the signal or the error signal to the signal sink (generally another logic gate).

The insertion of this 2inl multiplexer takes place in the respective hardware description language model of the circuit under test. The hardware description language used is irrelevant. The error selection signal is in the respective

Hardware description language model led to a terminal (pin) of the programmable logic device and is thus directly adjustable from outside the programmable logic device. Thus, it can be set reversibly from outside the programmable logic component, whether the programmable logic device is to behave incorrectly or according to its intended function. The error signal, which is passed in response to the error selection signal instead of the intended signal to the signal sink, on the one hand directly to the respective 2inl multiplexer to a certain signal level (logic "high" or "low") are set or formed from the output signal of another logical gate and thus represent either logical "high" or "low".

Thus, the advantage can be achieved that at any point of a realized by means of a programmable logic device digital circuit, an error can be reversibly installed. It is particularly advantageous that thereby tests can be carried out during the operation of the circuit and the introduction of errors in places of the circuit (inside the circuit) can take place, which is not possible with means according to the prior art. In particular, the introduction of errors in signal paths, which do not lead directly to external terminals (pins) of the programmable logic device is easily possible with objective invention. Likewise, it is advantageous that the present invention is independent of certain characteristics of the circuit, for example it is irrelevant whether the circuit is made synchronous or asynchronous, whether different clock frequencies are applied within the circuit and if parts of the circuit by interrupting the clock signal (clock gating) be temporarily suspended.

Another aspect of the invention lies in the universal applicability, in addition to the use in experimental setups (prototyping boards), the invention is also suitable for Use in the so-called target hardware, since no additional hardware is required, if necessary, the wiring of the error selection signal by means of a terminal of the programmable logic device must be ensured.

A particularly advantageous application of this invention is in the testing of safety-critical circuits and assemblies (which in addition to programmable logic components include other electronic components) in the development phase, for which evidence of their behavior in case of failure must be provided and where it is necessary faulty conditions directly in the However, these fault points (because the circuit is realized by means of a programmable logic device) are not accessible. This verification of the required properties of a circuit or module can be carried out particularly efficiently with objective invention.

A particular embodiment of the invention provides for each test a constant in

Provide a hardware description language model of the programmable logic device, by means of which certain tests are respectively prevented or enabled. As a result, the advantage can be achieved that the synthesized circuit of such a hardware description language model assumes a smaller extent, since currently unneeded components (2-in-multiplexer) are not realized if the respective constant switches off the corresponding test procedure. The execution of tests is thus considerably facilitated, since an already created hardware description language model is used to select one or more tests can remain unchanged and only the list of constants must be modified.

Brief description of the drawings

They show by way of example:

Fig.l a hardware description language model of a programmable logic device. Fig. 2 is a hardware description language model of a programmable logic device with provisions for error insertion testing.

3 shows an overview of the synthesis process when using a

Constant list for error correction.

Embodiment of the invention

Fig. 1 shows by way of example and schematically a hardware description language model of a programmable logic device. A logic component L comprises a first logic unit LEI and a second logic unit LE2. The first logical unit LEI transmits a signal S to the second logical unit LE2. This signal S is not accessible at any of the external terminals of the logic component L, and there are no possibilities to apply this signal S for testing purposes with a specific value (logical "high" or "low").

Fig. 2 shows by way of example and schematically a hardware description language model of a programmable logic device with provisions for error insertion testing. Fig. 2 shows the hardware description language model of Fig.l, wherein in the Signal path of the signal S a 2inl multiplexer M is connected. In this case, an input of the 2-in-multiplexer M is supplied with the outgoing signal from the first logic unit LEI signal S, the output of the 2inl multiplexer M provides a signal S2 to the second logic unit LE2. The second

Input of the 2inl multiplexer M is supplied with an error signal FS. In the example shown in Fig. 2, the logic signal "low" is represented as the error signal FS The selection input of the 2-in-multiplexer M is supplied with an error selection signal FAS, which is fed to an external terminal of the programmable logic component L. Thus, it is possible by means of the Error selection signal FAS at any time to switch between the transmission of the signal S to the second logic unit and the transmission of the error signal FS to the second logical skin.

3 shows, by way of example and schematically, an overview of the synthesis process when using a list of constants for error correction. SYNC synthesized circuit software SYNS obtains as input information to be processed the hardware description language model HDL of a logic device L to be synthesized and synthesizes the synthesized circuit SYNS, which is loaded into an integrated circuit which then has the functionality according to the hardware description language model HDL , This logic component L comprises an external terminal, which is supplied with an error selection signal FAS, by means of which is switched between error-free operation and operation with error insertion. A constant list K containing so-called HDL constants is added to the SYN software for synthesizing a synthesized circuit SYNS Input information provided. By means of this constant list K, the synthesis of the 2inl multiplexer M is controlled in the signal paths provided for error introduction and in the case that the respective error is not to be introduced, the synthesis of a 2-in-1 multiplexer M is omitted.

List of terms

L logic component LEI first logical unit

LE2 second logical unit

S signal

FS error signal

FAS error selection signal M 2inl multiplexer

S2 signal to second logical unit

SYNS Synthesized circuit

HDL Hardware Description Mode11

SYN software for creating a synthesized circuit

K Constant list

Claims

claims 1. A method for testing circuits and assemblies with programmable logic devices (L) by means of Error introduction, characterized in that in the Hardware Description Language Model (HDL) of a Programmable Logic Device (L) - in the signal path of a particular signal, a 2inl multiplexer (M) is switched, - whose second input is connected to an error signal (FS), and - whose selection input is connected to an error selection signal (FAS), and - this hardware description language model (HDL) is used to synthesize the programmable logic component (L). 2. programmable logic device (L) whose functionality is determined by synthesis from a hardware description language model (HDL), characterized in that for testing by means of error insertion a 2inl multiplexer (M) in the signal path of a particular signal (S) is connected and the second input of this 2inl multiplexer (M) is connected to an error signal (FS) and the selection input of this 2inl multiplexer (M) is connected to an error selection signal (FAS).