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WO2010052942A1 - 電子部品内蔵配線板及びその製造方法 - Google Patents

電子部品内蔵配線板及びその製造方法 Download PDF

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Publication number
WO2010052942A1
WO2010052942A1 PCT/JP2009/054585 JP2009054585W WO2010052942A1 WO 2010052942 A1 WO2010052942 A1 WO 2010052942A1 JP 2009054585 W JP2009054585 W JP 2009054585W WO 2010052942 A1 WO2010052942 A1 WO 2010052942A1
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WIPO (PCT)
Prior art keywords
electronic component
wiring board
conductor pattern
built
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2009/054585
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English (en)
French (fr)
Inventor
俊樹 古谷
剛士 古澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP2010536708A priority Critical patent/JPWO2010052942A1/ja
Priority to CN2009801326496A priority patent/CN102132639A/zh
Publication of WO2010052942A1 publication Critical patent/WO2010052942A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H05K1/187—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
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    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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    • H05K2201/09909—Special local insulating pattern, e.g. as dam around component
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
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    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49133—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing

Definitions

  • the present invention relates to an electronic component built-in wiring board in which an electronic component such as a semiconductor element is accommodated.
  • Patent Document 1 it is possible to increase the functionality and density of a multilayer wiring board by incorporating electronic components in the wiring board. In other words, by storing the electronic components inside, it is possible to mount other electronic components and the like in the surface mounting region, and it is possible to enhance the functionality.
  • the multilayer wiring board itself can be made smaller, and the circuit can be densified as compared to a conventional multilayer wiring board. Furthermore, since the wiring length can be reduced, an improvement in performance can be expected.
  • solder resist on the formed conductor pattern for the purpose of preventing adhesion of solder, maintaining insulation between conductors, and protecting conductors.
  • the conductor pattern layer including the connection terminal for electrical connection with the built-in electronic component is protected with a solder resist for fine pitch.
  • the coefficient of thermal expansion of the material (insulating resin) constituting the solder resist is higher than that of the metal constituting the conductor pattern. Therefore, if a solder resist is formed on the entire surface of the conductor pattern layer on which the connection terminals are formed, the wiring board may be warped due to the difference in thermal expansion coefficient between the two.
  • the present invention has been made in view of the above-described conventional problems, and provides a wiring board with a built-in electronic component that can achieve fine pitch, can prevent warpage, and has excellent quality such as connection reliability, and a method for manufacturing the same.
  • the purpose is to do.
  • the electronic component built-in wiring board according to the present invention An electronic component built-in wiring board in which electronic components are embedded by flip chip mounting, A conductor pattern layer; A connection terminal provided on the conductor pattern layer and electrically joined to the electronic component; A solder resist layer formed on the conductor pattern layer, The solder resist layer is formed around the connection terminal on the conductor pattern layer, and is not formed in at least some other regions on the conductor pattern layer.
  • connection terminal includes a bonding layer formed on the conductor pattern layer with a metal different from the conductor pattern layer.
  • the bonding layer may be made of solder.
  • the solder resist layer covers at least a part of the connection terminal formation region in the conductor pattern layer.
  • the electronic component is covered with an insulating material, and a through-hole conductor is formed on the insulating material.
  • the conductor pattern layer may be formed so as not to protrude from the surface of the insulating material.
  • the surface of the conductor pattern layer may be roughened.
  • the manufacturing method of the electronic component built-in wiring board A step of forming a conductor pattern layer on the metal foil in the laminated substrate in which the metal foil is disposed on the support; Forming a solder resist layer provided with a predetermined opening in a partial region on the conductor pattern layer; and Forming a connection terminal by providing a bonding layer on the conductor pattern layer corresponding to the opening of the solder resist layer; and On the laminated substrate, the electronic component is disposed so that the circuit forming surface of the electronic component and the forming surface of the connection terminal face each other, and electrically connecting the electronic component and the connection terminal; Covering the electronic component after mounting with an insulating material; Removing the support; Removing the exposed metal foil.
  • the joining layer is preferably made of a metal different from the conductor pattern layer.
  • the bonding layer may be formed of solder.
  • a step of providing a through hole in the insulating material to form a through-hole conductor may be further included.
  • the conductive pattern layer may be formed by electrolytic plating.
  • the conductor pattern layer After the formation of the conductor pattern layer, it may further include a step of roughening the surface of the conductor pattern layer before forming the solder resist layer.
  • the electronic component After mounting the electronic component, it may further include a step of filling an insulating resin around the connection terminal.
  • the bumps may be arranged in a grid pattern on the circuit formation surface (so-called area array type), or may be arranged at the end of the circuit formation surface (so-called peripheral type).
  • a wiring board with a built-in electronic component that can achieve a fine pitch, can prevent warpage, and is excellent in quality such as connection reliability.
  • FIG. 4F is a cross-sectional view showing a step of manufacturing a multilayer wiring board from the electronic component built-in wiring board of FIG. 4F (part 1).
  • FIG. 4F is a cross-sectional view showing a step of manufacturing a multilayer wiring board from the electronic component built-in wiring board of FIG. 4F (part 2).
  • FIG. 4F is a cross-sectional view showing a step of manufacturing a multilayer wiring board from the electronic component built-in wiring board of FIG. 4F (part 2).
  • FIG. 4F is a cross-sectional view showing a step of manufacturing a multilayer wiring board from the electronic component built-in wiring board of FIG. 4F (part 3).
  • FIG. 4F is a cross-sectional view showing a step of manufacturing a multilayer wiring board from the electronic component built-in wiring board of FIG. 4F (part 4).
  • FIG. 4F is a cross-sectional view showing a step of manufacturing a multilayer wiring board from the electronic component built-in wiring board of FIG. 4F (part 5). It is sectional drawing which shows the structure of the multilayer wiring board which uses the electronic component built-in wiring board of FIG. 4F. It is a top view for demonstrating the formation aspect of the soldering resist layer in this embodiment.
  • FIG. 4F is a schematic cross-sectional view of the electronic component built-in wiring board 1 according to the present embodiment.
  • the electronic component built-in wiring board 1 is used as, for example, a core substrate of a multilayer printed wiring board.
  • the electronic component built-in wiring board 1 includes an electronic component 2, an insulating material 3, an underfill material 4, a filling resin 5, inner conductor patterns 40 and 50, a solder resist layer 112, an outer conductor pattern 60, 70, a connection terminal 80, and a through-hole conductor 90.
  • the electronic component 2 is a flip chip and has a plurality of bumps 20 arranged in an area array type.
  • the bump 20 is, for example, a gold stud bump having a thickness of about 30 ⁇ m.
  • the insulating material 3 is a plate material obtained by impregnating a reinforcing material such as glass fiber or aramid fiber with a resin such as an epoxy resin, a polyester resin, a polyimide resin, a bismaleimide-triazine resin (BT resin), or a phenol resin. In the form, it consists of a prepreg.
  • the underfill material 4 is, for example, an insulating resin containing an inorganic filler such as silica or alumina, and secures the fixing strength of the electronic component 2 and also the electronic component 2 and the insulating material (for example, the insulating material 3 and the filling resin 5). ) To absorb the strain generated by the gap of thermal expansion coefficient.
  • the underfill material 4 is preferably made of a thermosetting resin and 40 to 90 wt% inorganic filler.
  • the filler size (average particle diameter) is preferably 0.1 to 3.0 ⁇ m.
  • the filling resin 5 is preferably made of a thermosetting resin and an inorganic filler.
  • the inorganic filler for example, Al 2 O 3 , MgO, BN, AlN, or SiO 2 can be used.
  • the thermosetting resin for example, an epoxy resin, a phenol resin or a cyanate resin having high heat resistance is preferable, and among them, an epoxy resin having excellent heat resistance is particularly preferable.
  • the solder resist layer 112 is made of, for example, a photosensitive resin using an acrylic-epoxy resin, a thermosetting resin mainly composed of an epoxy resin, an ultraviolet curable resin, or the like as a material for screen printing, spray coating, roll coating, or the like. Can be formed. Alternatively, a photosensitive dry film using an acrylic-epoxy resin may be formed by vacuum lamination or the like.
  • the conductor pattern 40 made of copper or the like is formed inside the first surface side (the side facing the circuit formation surface of the electronic component 2) of the electronic component built-in wiring board 1 (hereinafter referred to as a first inner layer). .
  • the thickness of the conductor pattern 40 is about 15 ⁇ m.
  • a part of the conductor pattern 40 is used as the first inner through-hole land 91 connected to the pad 81 and the through-hole conductor 90 constituting the connection terminal 80.
  • the conductor pattern 50 made of copper or the like is formed on the inner side (hereinafter referred to as a second inner layer) of the second surface (main surface opposite to the first surface) of the electronic component built-in wiring board 1, and a part thereof.
  • the second inner through-hole land 92 is connected to the through-hole conductor 90.
  • the thickness of the conductor pattern 50 is about 15 ⁇ m.
  • the first inner layer through-hole land 91 and the second inner layer through-hole land 92 are electrically connected via a through-hole conductor 90.
  • the conductor pattern 60 made of copper or the like is formed on the first surface of the electronic component built-in wiring board 1 (hereinafter referred to as the first outer layer), and a part thereof is connected to the through-hole conductor 90. This is the first outer layer through-hole land 93.
  • the thickness of the conductor pattern 60 is about 20 ⁇ m.
  • the conductor pattern 70 made of copper or the like is formed on the second surface (hereinafter referred to as a second outer layer) of the electronic component built-in wiring board 1, and a part thereof is connected to the through-hole conductor 90.
  • the second outer layer through-hole land 94 is formed.
  • the thickness of the conductor pattern 70 is about 20 ⁇ m.
  • the connection terminal 80 is a terminal for electrically connecting to the bump 20 of the electronic component 2, and includes a pad 81 and a bonding layer 82.
  • the thickness of the pad 81 is about 15 ⁇ m
  • the thickness of the bonding layer 82 is about 15 ⁇ m.
  • the bonding layer 82 is formed of a metal different from the pad 81 on the pad 81 (that is, on the conductor pattern 40).
  • the bonding layer 82 may be formed by electrolytic plating using a metal such as solder, tin, nickel, gold, or an alloy thereof, or may be formed by printing solder paste and performing reflow. May be.
  • the bonding layer 82 may be composed of a plurality of layers by combining these.
  • the outermost layer portion of the bonding layer 82 is preferably made of solder.
  • the electronic component built-in wiring board 1 configured as described above is characterized in that the solder resist layer 112 is partially formed instead of the entire surface of the conductor pattern layer.
  • a method for manufacturing the electronic component built-in wiring board 1 will be described with reference to FIGS. 1A to 4E.
  • connection terminal 80 (FIGS. 1A to 1H)
  • the support substrate 100 is a so-called copper foil with a carrier, in which a copper foil 101 and a carrier 102 made of copper are bonded using an adhesive (peeling layer) so as to be peeled (separated).
  • the thickness of the copper foil 101 is about 5 ⁇ m
  • the thickness of the carrier 102 is about 70 ⁇ m.
  • the carrier 102 is not limited to copper, and an insulating material or the like can be used.
  • connection terminal 80 for mounting the electronic component 2 is formed on the copper foil 101 of the support base material 100 using the additive method.
  • a metal such as nickel is used as the first base layer 110 by a method such as electroless plating, electrolytic plating, or sputtering. It is formed so as to have a thickness of about 1 ⁇ m on the entire surface of 100 copper foils 101. Thus, erosion due to etching can be prevented and a fine pattern can be formed.
  • the solder resist layer 112 is formed as in this embodiment, as shown in FIG. 1B, a metal such as titanium is used as the second underlayer 111 by a method such as electroless plating or sputtering.
  • the first base layer 110 is formed on the entire surface so as to have a thickness of about 0.1 ⁇ m.
  • the additive method refers to a method of forming a conductor pattern by growing a plating on a portion where a plating resist pattern is not formed and then removing the plating resist.
  • the formation of the connection terminal 80 using this additive method will be specifically described.
  • a dry film-like photosensitive resist 103 is laminated on the second underlayer 111 of the substrate of FIG. 1B (see FIG. 1C). Then, a mask film is brought into close contact with the laminated photosensitive resist 103, exposed to ultraviolet rays, and developed with an alkaline aqueous solution. As a result, the plating resist layer 104 having an opening corresponding to only the conductor pattern 40 is formed (see FIG. 1D).
  • the substrate of FIG. 1D is washed with water and dried, and then electrolytic copper plating is performed to form a copper plating layer 105 having a thickness of about 15 ⁇ m (see FIG. 1E).
  • substrate (refer FIG. 1F) in which the conductor pattern 40 and the pad 81 were formed is obtained by peeling the plating resist layer 104.
  • a liquid or dry film photosensitive resist (solder resist) is applied or laminated on the substrate surface of FIG. 1F to form a solder resist layer having a thickness of about 20 ⁇ m.
  • a mask film on which a predetermined pattern is formed is brought into close contact with the surface of the solder resist layer, exposed to ultraviolet rays, and developed with an alkaline aqueous solution.
  • FIG. 6 is a plan view showing a part of the substrate of FIG. 1G.
  • the solder resist layer 112 is formed in a region corresponding to the circuit formation surface of the electronic component 2 on the substrate surface of FIG. 1G.
  • the solder resist layer 112 is provided with a plurality of openings 61 for exposing the surface of each pad 81. More strictly, the entire surface of each pad 81 is not exposed by the opening 61 of the solder resist layer 112, and at least a part of each pad 81 is covered with the solder resist layer 112.
  • a bonding layer 82 is formed on the pad 81 (see FIG. 1H).
  • the bonding layer 82 is formed by printing solder paste and performing reflow.
  • the solder resist layer 112 is formed around the pad 81, it is possible to prevent the solder from flowing out to a portion other than the pad 81, and to form a uniform and bulky bonding layer 82 on the pad 81. It is easy to form.
  • the connection terminal 80 for joining with the bump 20 of the electronic component 2 is obtained.
  • the insulating materials 30a and 30b are placed on the mounting surface of the electronic component 2 on the substrate of FIG. 2B (see FIG. 3A).
  • the insulating materials 30a and 30b are plate materials (a prepreg in this embodiment) formed by impregnating a reinforcing material such as a glass cloth with a resin.
  • the insulating material 30a is punched according to the shape of the electronic component 2, and is placed in such a manner as to surround the electronic component 2 in a direction parallel to the mounting surface.
  • a punching method (punching) is suitable for punching.
  • a mechanical drill or a laser may be used.
  • the insulating material 30b is not subjected to punching processing and is in the form of a sheet, and is placed on the insulating material 30a and on the surface opposite to the bump 20 formation surface of the electronic component 2.
  • the substrate 500 on which the conductor pattern 50 is formed is laminated on the insulating material 30b with the surface on which the conductive pattern 50 is formed facing the insulating material 30b (see FIGS. 3B and 3C).
  • this lamination method for example, an autoclave method, a hydro press method, or the like can be used.
  • a method for manufacturing the substrate 500 will be briefly described. First, a support base material (consisting of a copper foil 501 having a thickness of about 5 ⁇ m and a carrier 502 having a thickness of about 70 ⁇ m) is prepared. Then, a dry film-like photosensitive resist is laminated on the supporting substrate. Then, a mask film on which a predetermined pattern is formed is brought into close contact with the laminated photosensitive resist, and exposure and development are performed, whereby a plating resist layer in which only a portion corresponding to the conductor pattern 50 is opened is formed.
  • the substrate after the plating resist layer is formed is washed with water and dried, and then electrolytic nickel plating or the like is performed to form a base layer 503 having a thickness of about 1 ⁇ m.
  • electrolytic copper plating is further performed to form a copper plating layer having a thickness of about 15 ⁇ m on the base layer 503. Then, when the plating resist layer is removed, washed with water and dried, the substrate 500 on which the conductor pattern 50 is formed is obtained.
  • the insulating material 30a and the insulating material 30b are fused, and the insulating material 3 is formed as shown in FIG. 3C. Further, at that time, the resin component flows out from the insulating materials 30 a and 30 b, and the gap portion generated between the electronic component 2 and the insulating materials 30 a and 30 b is filled with the filling resin 5.
  • a plating resist layer 107 having an opening corresponding to only the conductor pattern 60 and a plating resist layer 108 having an opening corresponding to only the conductor pattern 70 are formed (see FIG. 4D).
  • the substrate of FIG. 4D is washed with water and dried, and then electrolytic copper plating is performed to remove the plating resist layers 107 and 108.
  • the copper plating film 109 and the through-hole conductor 90 are formed.
  • unnecessary copper plating layers 113, copper foil 101, and copper foil 501 on both main surfaces of the substrate of FIG. 4E are removed using an etchant that can selectively etch copper.
  • the first base layer 110 and the second base layer 111 are removed using an etchant that can selectively etch a metal different from copper, such as nickel or titanium.
  • the electronic component built-in wiring board 1 manufactured as described above has the following excellent features.
  • connection terminal 80 for mounting an electronic component is previously formed on the support base material 100, (b) the support base material 100 has a large thickness (about 75 ⁇ m), (c )
  • the conductor pattern 40 and the connection terminal 80 can be formed at a fine pitch (for example, 50 ⁇ m).
  • the carrier 102 of the supporting base material 100 is easily removed by peeling, damage that may be applied to the connection terminal 80 can be reduced as much as possible when removing an unnecessary metal layer.
  • the formed connection terminal 80 and conductor pattern 40 are not etched in a subsequent process, the pattern shape at the time of formation is maintained. Therefore, the pattern accuracy can be improved.
  • the electronic component built-in wiring board 1 has a structure (symmetric structure) in which the insulating material (the underfill material 4 and the insulating material 3) sandwiches the electronic component 2 in the downward direction and the upward direction on the mounting surface. have.
  • stress due to stress heat, vibration impact, drop impact, etc.
  • the conductor pattern 60 and the conductor pattern 70 are respectively formed on the first surface and the second surface of the electronic component built-in wiring board 1, resistance to warping is further increased.
  • the solder resist layer 112 is not formed on the entire surface, and a non-formation portion is provided. That is, the formation area of the solder resist having a high coefficient of thermal expansion is limited to an indispensable area. For this reason, it is possible to reduce the warpage of the substrate.
  • FIG. 5F is a schematic cross-sectional view of a multilayer wiring board 600 using the electronic component built-in wiring board 1 of FIG. 4F as a core substrate. A method of manufacturing the multilayer wiring board 600 will be briefly described with reference to FIGS. 5A to 5E.
  • a sheet-like plate material obtained by impregnating a reinforcing material such as glass cloth with a resin (in this embodiment, Prepreg), and further, a rolled copper foil or an electrolytic copper foil is placed thereon and thermocompression bonded.
  • insulating layers 601 and 602 having a thickness of about 40 ⁇ m and copper foils 610 and 611 having a thickness of about 12 ⁇ m are formed (see FIG. 5A).
  • the amount of resin pushed away by the first outer layer through-hole land 93 and the second outer layer through-hole land 94 and the amount of resin entering the inside (cavity) of the through-hole conductor 90 are offset. Accordingly, the surfaces of the insulating layers 601 and 602 are planarized.
  • laser vias (blind holes) 612 and 613 are formed at predetermined positions on both main surfaces of the substrate of FIG. 5A by a carbon dioxide (CO 2 ) laser, a UV-YAG laser, or the like (see FIG. 5B).
  • CO 2 carbon dioxide
  • UV-YAG laser UV-YAG laser
  • electroless copper plating is performed on the entire surface to form a copper plating layer 620 on both main surfaces and on the inner surfaces of the laser vias 612 and 613 (see FIG. 5C).
  • plating resist layers 621 and 622 see FIG. 5D
  • electrolytic copper plating is performed to form vias 603 and 604 and copper plating layers 614 and 615 (see FIG. 5E).
  • the plating resist layers 621 and 622 are removed, and unnecessary copper foils 610 and 611 on both main surfaces and the copper plating layer 620 are removed by etching, whereby conductor patterns 605 and 606 are formed.
  • multilayer wiring board 600 is obtained (see FIG. 5F).
  • the formation mode of the solder resist layer 112 is not limited to that shown in FIG.
  • the opening 61 of the solder resist layer 112 may have a rectangular frame shape as shown in FIG.
  • the area between the pads 81 may be covered with a solder resist layer 112 as shown in FIG. 8, or at the center of the area corresponding to the circuit formation surface of the electronic component 2 as shown in FIG. A non-forming region may be provided.
  • the surface of the conductor pattern layer is subjected to surface roughening such as blackening treatment or chemical etching treatment (CZ treatment) before the formation of the solder resist layer. May be roughened.
  • the insulating layers 601 and 602 and the conductor patterns 605 and 606 are laminated on each main surface of the electronic component built-in wiring board 1, respectively. It is not limited to the configuration. That is, two or more layers may be laminated, or the number of laminations may be different on both main surfaces. Furthermore, you may laminate
  • the technology according to the present invention can be widely applied to wiring boards that house electronic components therein.

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Abstract

　この電子部品内蔵配線板（１）は、導体パターン層（４０）と、導体パターン層（４０）に設けられ、フリップチップ実装する電子部品（２）と電気的に接合する接続端子（８０）と、導体パターン層（４０）上に形成されたソルダーレジスト層（１１２）と、を備える。そして、このソルダーレジスト層（１１２）は、導体パターン層（４０）上における接続端子（８０）の周囲に形成され、導体パターン層（４０）上におけるその他の少なくとも一部の領域には形成されていない。このため、接続端子（８０）が保護され、導体間の絶縁性が確保される。さらに、ソルダーレジスト層（１１２）が導体パターン層（４０）上の全面に形成されていないため、基板の反りを低減させることが可能となる。

Description

電子部品内蔵配線板及びその製造方法
　本発明は、半導体素子等の電子部品を内部に収容した電子部品内蔵配線板に関する。
　近年、電子機器の高性能化、小型化が進展し、それと共に、電子機器の内部に実装される配線板の高機能化、高集積化の要請は益々高くなってきている。
　これに対し、ＩＣチップ等の電子部品を配線板内に収容する（内蔵する）技術が種々提案されている（例えば、特許文献１で開示される多層配線基板など）。
　特許文献１で開示されるように、電子部品を配線板に内蔵することにより、多層配線板の高機能化と高密度化とが可能となる。つまり、電子部品を内部に収納することで、表層の実装領域に他の電子部品等を実装することが可能となり、高機能化が可能となる。
　また、電子部品を内蔵することにより、多層配線板自体を小さくすることも可能となり、従来の多層配線板と比較して、回路を高密度化することができる。さらに、配線長を減少させ得るため、性能向上も期待できる。
特開２００４－７００６号公報
　ところで、配線板の製造プロセスにおいて、半田の付着防止、導体間の絶縁性の維持、導体の保護などの目的から、形成した導体パターン上にソルダーレジストをコーティングすることは周知である。特に、ファインピッチ化のため、内蔵される電子部品と電気的に接続させるための接続端子を含む導体パターン層は、ソルダーレジストで保護されるのが望ましい。
　一方、ソルダーレジストを構成する材料（絶縁性樹脂）の熱膨張率は、導体パターンを構成する金属の熱膨張率より高い。したがって、上記の接続端子が形成された導体パターン層において、全面にソルダーレジストが形成されると、両者の熱膨張率の違いから配線板に反りが発生してしまうおそれがある。
　本発明は、上記従来の問題に鑑みてなされたものであり、ファインピッチ化が図れると共に、反りの発生を防止でき、接続信頼性等の品質に優れる電子部品内蔵配線板及びその製造方法を提供することを目的とする。
　本発明に係る電子部品内蔵配線板は、
　電子部品をフリップチップ実装にて内蔵した電子部品内蔵配線板であって、
　導体パターン層と、
　該導体パターン層に設けられ、前記電子部品と電気的に接合する接続端子と、
　前記導体パターン層上に形成されたソルダーレジスト層と、を備え、
　前記ソルダーレジスト層は、前記導体パターン層上における前記接続端子の周囲に形成され、前記導体パターン層上におけるその他の少なくとも一部の領域には、形成されていない、ことを特徴とする。
　好ましくは、前記接続端子は、前記導体パターン層と異なる金属で前記導体パターン層上に形成される接合層を含む。
　前記接合層は半田で構成されていてもよい。
　好ましくは、前記ソルダーレジスト層は、前記導体パターン層における前記接続端子の形成領域の少なくとも一部分を覆っている。
　好ましくは、前記電子部品は絶縁材で覆われており、該絶縁材にはスルーホール導体が形成されている。
　この場合、前記導体パターン層は、前記絶縁材の表面から突出しない状態で形成されていてもよい。
　前記導体パターン層の表面が粗化されていてもよい。
　また、本発明に係る電子部品内蔵配線板の製造方法は、
　支持体上に金属箔が配置された積層基材における前記金属箔上に、導体パターン層を形成する工程と、
　前記導体パターン層上の一部の領域に、所定の開口部を設けたソルダーレジスト層を形成する工程と、
　前記ソルダーレジスト層の開口部に対応する前記導体パターン層上に接合層を設けることで、接続端子を形成する工程と、
　前記積層基材上に、前記電子部品を該電子部品の回路形成面と前記接続端子の形成面とが向かい合うように配置し、前記電子部品と前記接続端子とを電気的に接続する工程と、
　前記実装後の電子部品を絶縁材で被覆する工程と、
　前記支持体を除去する工程と、
　露出している前記金属箔を除去する工程と、を有する、ことを特徴とする。
　前記接合層は前記導体パターン層と異なる金属からなるのが好ましい。
　この場合、前記接合層を半田で形成してもよい。
　前記電子部品を前記絶縁材で被覆した後、前記絶縁材に貫通孔を設け、スルーホール導体を形成する工程をさらに有してもよい。
　前記導体パターン層を電解めっきで形成してもよい。
　前記導体パターン層の形成後、前記ソルダーレジスト層を形成する前に、前記導体パターン層の表面を粗化する工程をさらに有してもよい。
　前記電子部品の実装後、前記接続端子の周りに絶縁性樹脂を充填する工程をさらに有してもよい。
　また、上記両発明において、前記電子部品には、前記接続端子と接合させるためのバンプが形成されていることが望ましい。その場合、前記バンプは、回路形成面に格子状に配置（いわゆる、エリアアレイ型）されていてもよいし、回路形成面の端部に配置（いわゆる、ペリフェラル型）されていてもよい。
　本発明によれば、ファインピッチ化が図れると共に、反りの発生を防止でき、接続信頼性等の品質に優れる電子部品内蔵配線板を提供できる。
支持基材の構成を示す断面図である。 支持基材に第１の下地層及び第２の下地層が形成された様子を示す断面図である。 図１Ｂの基板に感光性レジストがラミネートされた様子を示す断面図である。 図１Ｂの基板にめっきレジスト層が形成された様子を示す断面図である。 図１Ｄの基板に銅めっき層が形成された様子を示す断面図である。 図１Ｅの基板からめっきレジスト層が剥離された後の様子を示す断面図である。 図１Ｆの基板にソルダーレジスト層が形成された様子を示す断面図である。 図１Ｇの基板に接合層が形成された様子を示す断面図である。 電子部品の実装工程を示す断面図である。 アンダーフィル材充填後の様子を示す断面図である。 積層工程を示す断面図（その１）である。 積層工程を示す断面図（その２）である。 積層工程を示す断面図（その３）である。 図３Ｃの基板からキャリアを剥離した後の様子を示す断面図である。 図４Ａの基板に貫通孔が形成された様子を示す断面図である。 図４Ｂの基板に無電解銅めっきを施した後の様子を示す断面図である。 図４Ｃの基板にめっきレジスト層が形成された様子を示す断面図である。 図４Ｄの基板に銅めっき膜及びスルーホール導体が形成された様子を示す断面図である。 本発明の一実施形態に係る電子部品内蔵配線板の構成を示す断面図である 図４Ｆの電子部品内蔵配線板から多層配線板を製造する工程を示す断面図である（その１）。 図４Ｆの電子部品内蔵配線板から多層配線板を製造する工程を示す断面図である（その２）。 図４Ｆの電子部品内蔵配線板から多層配線板を製造する工程を示す断面図である（その３）。 図４Ｆの電子部品内蔵配線板から多層配線板を製造する工程を示す断面図である（その４）。 図４Ｆの電子部品内蔵配線板から多層配線板を製造する工程を示す断面図である（その５）。 図４Ｆの電子部品内蔵配線板を使用した多層配線板の構成を示す断面図である。 本実施形態におけるソルダーレジスト層の形成態様を説明するための平面図である。 他の実施形態におけるソルダーレジスト層の形成態様を説明するための平面図（その１）である。 他の実施形態におけるソルダーレジスト層の形成態様を説明するための平面図である（その２）。 他の実施形態におけるソルダーレジスト層の形成態様を説明するための平面図である（その３）。
符号の説明
　１　　電子部品内蔵配線板
　２　　電子部品
　３　　絶縁材
　４　　アンダーフィル材
　５　　充填樹脂
　２０　バンプ
　４０、５０、６０、７０　導体パターン
　８０　接続端子
　８１　パッド
　８２　接合層
　９０　スルーホール導体
　９１　第１の内層のスルーホールランド
　９２　第２の内層のスルーホールランド
　９３　第１の外層のスルーホールランド
　９４　第２の外層のスルーホールランド
　１１２　ソルダーレジスト層
　以下、本発明の実施形態に係る電子部品内蔵配線板及びその製造方法について、図面を参照して説明する。
　図４Ｆは、本実施形態に係る電子部品内蔵配線板１の概略断面図である。この電子部品内蔵配線板１は、例えば、多層プリント配線板のコア基板等として使用される。
　電子部品内蔵配線板１は、電子部品２と、絶縁材３と、アンダーフィル材４と、充填樹脂５と、内層の導体パターン４０、５０と、ソルダーレジスト層１１２と、外層の導体パターン６０、７０と、接続端子８０と、スルーホール導体９０と、からなる。
　電子部品２は、フリップチップであり、エリアアレイ型に配列した複数のバンプ２０を有している。バンプ２０は、例えば、厚さ約３０μｍの金スタッドバンプである。
　絶縁材３は、ガラス繊維、アラミド繊維等の補強材にエポキシ樹脂、ポリエステル樹脂、ポリイミド樹脂、ビスマレイミド‐トリアジン樹脂（ＢＴ樹脂）、フェノール樹脂等の樹脂を含浸させてなる板材であり、本実施形態では、プリプレグで構成される。
　アンダーフィル材４は、例えば、シリカやアルミナ等の無機フィラーを含む絶縁性樹脂であり、電子部品２の固定強度を確保すると共に、電子部品２と絶縁材（例えば、絶縁材３や充填樹脂５）との熱膨張率のギャップによって発生する歪みを吸収する役割を担う。　アンダーフィル材４は、熱硬化性樹脂と４０～９０ｗｔ％の無機フィラーからなることが好ましい。また、フィラーのサイズ（平均粒径）は０．１～３．０μｍであることが好ましい。
　充填樹脂５は、熱硬化性樹脂と無機フィラーとからなることが好ましい。無機フィラーには、たとえば、Ａｌ２Ｏ３、ＭｇＯ、ＢＮ、ＡｌＮまたはＳｉＯ２などを用いることができる。熱硬化性樹脂には、たとえば、耐熱性が高いエポキシ樹脂、フェノール樹脂またはシアネート樹脂が好ましく、この中でも、耐熱性が優れるエポキシ樹脂が特に好ましい。
　ソルダーレジスト層１１２は、例えば、アクリル－エポキシ系樹脂を用いた感光性樹脂、エポキシ樹脂を主体とした熱硬化性樹脂、紫外線硬化型の樹脂等を材料として、スクリーン印刷、スプレーコーティング、ロールコーティング等で形成することができる。あるいは、アクリル－エポキシ系樹脂を用いた感光性ドライフィルムを真空ラミネート等することで形成してもよい。
　銅等からなる導体パターン４０は、電子部品内蔵配線板１の第１面側（電子部品２の回路形成面と対向する側）の内部（以下、第１の内層という。）に形成されている。導体パターン４０の厚みは約１５μｍである。導体パターン４０の一部は、接続端子８０を構成するパッド８１やスルーホール導体９０に接続している第１の内層のスルーホールランド９１として使用される。
　銅等からなる導体パターン５０は、電子部品内蔵配線板１の第２面（第１面と反対側の主面）の内側（以下、第２の内層という。）に形成され、その一部が、スルーホール導体９０に接続している第２の内層のスルーホールランド９２となる。導体パターン５０の厚さは、約１５μｍである。第１の内層のスルーホールランド９１と第２の内層のスルーホールランド９２は、スルーホール導体９０を介して電気的に接続している。
　銅等からなる導体パターン６０は、電子部品内蔵配線板１の第１面上（以下、第１の外層という。）に形成されていて、その一部が、スルーホール導体９０に接続している第１の外層のスルーホールランド９３となる。導体パターン６０の厚さは、約２０μｍである。
　銅等からなる導体パターン７０は、電子部品内蔵配線板１の第２面上（以下、第２の外層という。）に形成されていて、その一部が、スルーホール導体９０に接続している第２の外層のスルーホールランド９４となる。導体パターン７０の厚さは、約２０μｍである。
　接続端子８０は、電子部品２のバンプ２０と電気的に接続するための端子であり、パッド８１と、接合層８２とから構成される。パッド８１の厚さは約１５μｍであり、接合層８２の厚さは約１５μｍである。
　接合層８２は、パッド８１上（即ち、導体パターン４０上）にパッド８１とは異なる金属で形成される。例えば、半田、錫、ニッケル、金などの金属、あるいは、それらの合金などを用いた電解めっき等により接合層８２を形成してもよいし、半田ペーストを印刷し、リフローを行うことで形成してもよい。あるいは、これらを組み合わせることで、接合層８２を複数の層で構成してもよい。但し、接合層８２の最表層部は半田からなることが好ましい。
　以上にように構成される電子部品内蔵配線板１は、ソルダーレジスト層１１２が導体パターン層の全面ではなく部分的に形成されている点に特徴を有する。以下、図１Ａ～図４Ｅを参照して、電子部品内蔵配線板１の製造方法を説明する。
（１）接続端子８０の形成工程（図１Ａ～図１Ｈ）
　先ず、図１Ａに示す支持基材１００を準備する。支持基材１００は、銅箔１０１と、銅からなるキャリア１０２とを接着剤（剥離層）を使って剥離（分離）可能に接着した、いわゆるキャリア付き銅箔である。ここで、銅箔１０１の厚さは、約５μｍであり、キャリア１０２の厚さは、約７０μｍである。なお、キャリア１０２として、銅に限らず、絶縁材なども採用できる。
　次に、支持基材１００の銅箔１０１上に、電子部品２を実装するための接続端子８０をアディティブ法を用いて形成する。
　なお、接続端子８０をアディティブ法で形成する前に、図１Ｂに示すように、第１の下地層１１０として、ニッケル等の金属を、無電解めっき、電解めっき、スパッタリング等の方法で支持基材１００の銅箔１０１上の全面に厚さが約１μｍとなるように形成する。　これによって、エッチングによる侵食を防止でき、ファインパターンを形成することができる。
　また、本実施形態のように、ソルダーレジスト層１１２を形成する場合には、図１Ｂに示すように、第２の下地層１１１として、チタン等の金属を、無電解めっき、スパッタリング等の方法で第１の下地層１１０上の全面に厚さが約０．１μｍとなるように形成する。これによってソルダーレジスト層１１２との密着性が向上するという効果が得られる。
　ここで、アディティブ法とは、めっきレジストパターンの非形成部分にめっきを成長させた後、めっきレジストを除去することにより導体パターンを形成する手法をいう。
　以下、このアディティブ法を用いた接続端子８０の形成について、具体的に説明する。
　図１Ｂの基板の第２の下地層１１１上にドライフィルム状の感光性レジスト１０３をラミネートする（図１Ｃ参照）。そして、ラミネートした感光性レジスト１０３にマスクフィルムを密着させ、紫外線で露光し、アルカリ水溶液で現像する。その結果、導体パターン４０に相当する部分のみが開口しためっきレジスト層１０４が形成される（図１Ｄ参照）。
　続いて、図１Ｄの基板を水洗し、乾燥させた後、電解銅めっきを行い、厚さ約１５μｍの銅めっき層１０５を形成する（図１Ｅ参照）。
　そして、めっきレジスト層１０４を剥離することで、導体パターン４０及びパッド８１が形成された基板（図１Ｆ参照）が得られる。
　それから、図１Ｆの基板表面に、液状又はドライフィルム状の感光性レジスト（ソルダーレジスト）を塗布又はラミネートして、厚さ約２０μｍのソルダーレジスト層を形成する。そして、所定のパターンが形成されたマスクフィルムをソルダーレジスト層の表面に密着させ、紫外線で露光し、アルカリ水溶液で現像する。
　その結果、図１Ｆの基板表面にソルダーレジスト層１１２が形成される（図１Ｇ参照）。図６は、図１Ｇの基板の一部分を示す平面図である。図６に示すように、ソルダーレジスト層１１２は、図１Ｇの基板表面における電子部品２の回路形成面に対応する領域に形成される。そして、ソルダーレジスト層１１２には、各パッド８１の表面を露出させるための開口部６１が複数設けられている。より厳密には、ソルダーレジスト層１１２の開口部６１によって各パッド８１の表面全域は露出されず、各パッド８１上の少なくとも一部は、ソルダーレジスト層１１２で覆われている。
　続いて、パッド８１上に接合層８２を形成する（図１Ｈ参照）。本実施形態では、接合層８２は、半田ペーストを印刷し、リフローを行うことで形成される。
　この際、上述したように、ソルダーレジスト層１１２がパッド８１の周りに形成されているため、パッド８１以外の部分への半田の流出を防止でき、パッド８１上に均一で嵩高い接合層８２を形成することが容易となる。
　以上のようにして、電子部品２のバンブ２０と接合させるための接続端子８０が得られる。
（２）電子部品２の実装工程（図２Ａ、図２Ｂ）
　続いて、図１Ｈの基板上に電子部品２をフェースダウン方式にて載置し、電子部品２のバンプ２０と接続端子８０とを接合して、実装する（図２Ａ参照）。
　上述したように、接合層８２は、均一かつ嵩高く形成されているため、電子部品２のバンプ２０と接続端子８０との接続信頼性が確保できる。
　電子部品２の実装後、電子部品２と基板との間に生じる空隙に、アンダーフィル材４を充填する（図２Ｂ参照）。
　アンダーフィル材４は、上述したように、例えば、シリカやアルミナ等の無機フィラーを含む絶縁性樹脂である。
（３）積層工程（図３Ａ～図３Ｃ）
　続いて、絶縁材３０ａと、絶縁材３０ｂとを図２Ｂの基板における電子部品２の実装面上に載置する（図３Ａ参照）。絶縁材３０ａ、３０ｂは、ガラス布等の補強材に樹脂を含浸させてなる板材（本実施形態では、プリプレグ）である。絶縁材３０ａは、電子部品２の形状に合わせてくり貫き加工が施されており、電子部品２をその実装面に対して平行な方向で囲むような態様で載置される。くり貫き加工には、打ち抜き加工法（パンチング）が好適である。尚、メカニカルドリルやレーザ等を用いてもよい。
　一方、絶縁材３０ｂは、くり貫き加工が施されておらずシート状であり、絶縁材３０ａ上及び電子部品２のバンプ２０形成面と反対面上に載置される。
　絶縁材３０ａ、３０ｂの載置後、絶縁材３０ｂ上に、導体パターン５０が形成された基板５００を、導体パターン５０の形成面を絶縁材３０ｂ側に向けて積層する（図３Ｂ、図３Ｃ参照）。この積層方式として、例えば、オートクレーブ方式やハイドロプレス方式等を用いることができる。
　基板５００の製造方法について簡単に説明する。先ず、支持基材１００と同様の構成の支持基材（厚さ約５μｍの銅箔５０１と、厚さ約７０μｍのキャリア５０２とから構成される。）を準備する。そして、かかる支持基材上にドライフィルム状の感光性レジストをラミネートする。それから、ラミネートした感光性レジストに所定のパターンが形成されたマスクフィルムを密着させ、露光・現像することで、導体パターン５０に相当する部分のみが開口しためっきレジスト層が形成される。
　そして、めっきレジスト層形成後の基板を水洗乾燥した後、電解ニッケルめっき等を行って、厚さ約１μｍの下地層５０３を形成する。それから、さらに電解銅めっきを行い、下地層５０３上に、厚さ約１５μｍの銅めっき層を形成する。そして、めっきレジスト層を除去し、水洗乾燥すると、導体パターン５０が形成された基板５００が得られる。
　上記積層の際、加圧されることで、絶縁材３０ａと、絶縁材３０ｂとが融合し、図３Ｃに示すように、絶縁材３が形成される。また、その際、絶縁材３０ａ、３０ｂから樹脂成分が流出し、電子部品２と、絶縁材３０ａ、３０ｂとの間に生じる空隙部が、充填樹脂５で充填される。
（４）後工程（図４Ａ～図４Ｅ）
　続いて、図３Ｃの基板からキャリア１０２と、キャリア５０２とを剥離（分離）し、図４Ａの基板を得る。そして、メカニカルドリル等を用いた既知の穴あけ工法により、図４Ａの基板に貫通孔１０６をあける（図４Ｂ参照）。貫通孔１０６の形成後、図４Ｂの基板に無電解銅めっきを施し、両主面上および貫通孔１０６の内壁に銅めっき層１１３を形成する（図４Ｃ参照）。
　そして、図４Ｃの基板の両主面上に、ドライフィルム状の感光性レジストをラミネートし、該感光性レジストにマスクフィルムを密着させ、露光・現像を行う。そうすると、導体パターン６０に相当する部分のみが開口しためっきレジスト層１０７と、導体パターン７０に相当する部分のみが開口しためっきレジスト層１０８が形成される（図４Ｄ参照）。
　次に、図４Ｄの基板を水洗し、乾燥させた後、電解銅めっきを行い、めっきレジスト層１０７及び１０８を除去する。すると、図４Ｅに示すように、銅めっき膜１０９と、スルーホール導体９０が形成される。そして、図４Ｅの基板の両主面上の不要な銅めっき層１１３、銅箔１０１及び銅箔５０１を銅を選択的にエッチングできるエッチング液を用いて除去する。続いて、ニッケル、チタン等の銅とは異なる金属を選択的にエッチングできるエッチング液を用いて、第１の下地層１１０及び第２の下地層１１１を除去する。
　これにより、導体パターン６０（第１の外層のスルーホールランド９３）と、導体パターン７０（第２の外層のスルーホールランド９４）とが形成された図４Ｆに示す電子部品内蔵配線板１が得られる。
　第１の下地層１１０及び第２の下地層１１１のエッチング除去の際、銅とは異なる金属を選択的にエッチングできるエッチング液を用いるため、導体パターン４０はエッチングの影響を受けず保護される。
　さらに、パッド８１は、ソルダーレジスト層１１２に埋設され、その表面から突出していないので、エッチング時のパターン細りが起きにくく、ファインパターンが維持できる。
　以上のようにして製造された電子部品内蔵配線板１は、以下のような優れた特徴を有する。
　（１）電子部品２を収容（内蔵）しているため、表層の実装領域に他の電子部品等を実装することが可能となり、高機能化が可能となる。また、内蔵する電子部品をフリップチップ実装することで、薄型化（小型化）が図れる。
　（２）また、（ａ）予め、支持基材１００上に電子部品実装用の接続端子８０を形成しておくこと、（ｂ）支持基材１００の厚みが大きい（約７５μｍ）こと、（ｃ）導体パターン４０及び接続端子８０をアディティブ法にて形成すること、等により、導体パターン４０及び接続端子８０をファインピッチ（例えば、５０μｍ）で形成することが可能となる。また、支持基材１００のキャリア１０２は、剥離により容易に除去されるため、不要の金属層を除去する際、接続端子８０に加わるおそれのあるダメージを極力低減できる。さらに、形成した接続端子８０及び導体パターン４０は、後工程においてエッチング等されないため、形成時のパターン形状が保持される。したがって、パターン精度の向上が図れる。
　（３）また、収容される電子部品２は、アンダーフィル材４、絶縁材３により、被覆され、封止されているため、固定強度が高い。このため、電子部品内蔵配線板１をコア基板としたビルトアップ等の多層化工程において、ハンドリングが容易となり、また、エッチング等が行われても、電子部品２に与える影響を極力防止できる。
　（４）また、電子部品内蔵配線板１は、絶縁材料（アンダーフィル材４及び絶縁材３）が、電子部品２をその実装面における下方向及び上方向で挟み込んだ態様の構造（対称構造）を有している。かかる対称構造にすると、ストレス（熱、振動衝撃、落下衝撃等）による応力が緩和でき、反りに対する耐性が確保できる。
　さらに、電子部品内蔵配線板１の第１面上及び第２面上に、それぞれ、導体パターン６０及び導体パターン７０が形成されているため、反りに対する耐性はより一層高いものとなる。
　（５）また、導体パターン４０の形成層において、接続端子８０の周りをソルダーレジスト層１１２でコーティングしているため、不必要な部分に半田が付かず、接続端子８０が保護され、導体間の絶縁性が確保される。さらに、導体パターン４０の形成層において、ソルダーレジスト層１１２が全面に形成されておらず、非形成部が設けられている。つまり、熱膨張率の高いソルダーレジストの形成領域を必要不可欠な領域のみに制限している。このため、基板の反りを低減させることが可能となる。
　図５Ｆは、図４Ｆの電子部品内蔵配線板１をコア基板として使用した多層配線板６００の概略断面図である。この多層配線板６００の製造方法について、図５Ａ～図５Ｅを参照して簡単に説明する。
　先ず、図４Ｆの電子部品内蔵配線板１の両主面上（第１面及び第２面上）に、ガラス布等の補強材に樹脂を含浸させてなるシート状の板材（本実施形態では、プリプレグ）を載置し、さらに、その上に圧延銅箔あるいは電解銅箔を載置し、加熱圧着する。その結果、厚さ約４０μｍの絶縁層６０１、６０２と、厚さ約１２μｍの銅箔６１０、６１１が形成される（図５Ａ参照）。
　その際、第１の外層のスルーホールランド９３及び第２の外層のスルーホールランド９４によって押し退けられる樹脂量と、スルーホール導体９０の内部（空洞）に入り込む樹脂量とが相殺される。したがって、絶縁層６０１及び６０２の表面は平坦化される。
　続いて、炭酸ガス（ＣＯ２）レーザやＵＶ－ＹＡＧレーザ等により、図５Ａの基板の両主面の所定箇所にレーザバイア（ブラインドホール）６１２、６１３を形成する（図５Ｂ参照）。
　そして、図５Ｂの基板において、全面に無電解銅めっきを行って、両主面上並びにレーザバイア６１２及び６１３の内面に銅めっき層６２０を形成する（図５Ｃ参照）。
　それから、めっきレジスト層６２１、６２２を形成した後（図５Ｄ参照）、電解銅めっきを行い、バイア６０３、６０４と、銅めっき層６１４、６１５を形成する（図５Ｅ参照）。
　そして、図５Ｅの基板において、めっきレジスト層６２１、６２２を除去し、両主面上の不要な銅箔６１０、６１１と、銅めっき層６２０をエッチングして除去すると、導体パターン６０５、６０６が形成された多層配線板６００が得られる（図５Ｆ参照）。
　尚、本発明は、上記実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲で種々の変更が可能である。
　例えば、ソルダーレジスト層１１２の形成態様は、図６に示すものに限られない。例えば、電子部品２のバンプ２０が、ペリフェラル型に配列されている場合では、図７に示すように、ソルダーレジスト層１１２の開口部６１を矩形枠状にしてもよい。
　この場合、図８に示すように、各パッド８１間の領域をソルダーレジスト層１１２で覆ってもよいし、図９に示すように、電子部品２の回路形成面に対応する領域の中央部に非形成領域を設けてもよい。
　また、ソルダーレジスト層と導体パターン層との密着性を向上させるために、ソルダーレジスト層の形成前に、導体パターン層の表面を黒化処理、化学エッチング処理（ＣＺ処理）等の表面粗化法によって、粗化してもよい。
　また、上記実施形態の多層配線板６００は、電子部品内蔵配線板１の両主面に、絶縁層６０１、６０２と導体パターン６０５、６０６からなる層をそれぞれ１層ずつ積層しているが、かかる構成に限定されない。即ち、２層以上積層しても構わないし、両主面において、積層数が異なっていてもよい。さらには、片側の主面のみに積層してもよい。
　本出願は、２００８年１１月６日にされた、米国仮特許出願６１／１１２０３５に基づく。本明細書中に、その明細書、特許請求の範囲、図面全体を参照して取り込むものとする。
　本発明に係る技術は、電子部品を内部に収容する配線板に広く適用可能である。

Claims (18)

  1. 　電子部品をフリップチップ実装にて内蔵した電子部品内蔵配線板であって、
    　導体パターン層と、
    　該導体パターン層に設けられ、前記電子部品と電気的に接合する接続端子と、
    　前記導体パターン層上に形成されたソルダーレジスト層と、を備え、
    　前記ソルダーレジスト層は、前記導体パターン層上における前記接続端子の周囲に形成され、前記導体パターン層上におけるその他の少なくとも一部の領域には、形成されていない、
    　ことを特徴とする電子部品内蔵配線板。
  2. 　前記接続端子は、前記導体パターン層と異なる金属で前記導体パターン層上に形成される接合層を含む、
    　ことを特徴とする請求項１に記載の電子部品内蔵配線板。
  3. 　前記接合層は半田からなる、
    　ことを特徴とする請求項２に記載の電子部品内蔵配線板。
  4. 　前記ソルダーレジスト層は、前記導体パターン層における前記接続端子の形成領域の少なくとも一部分を覆っている、
    　ことを特徴とする請求項１に記載の電子部品内蔵配線板。
  5. 　前記電子部品は絶縁材で覆われており、該絶縁材にはスルーホール導体が形成されている、
    　ことを特徴とする請求項１に記載の電子部品内蔵配線板。
  6. 　前記導体パターン層は、前記絶縁材の表面から突出していない、
    　ことを特徴とする請求項５に記載の電子部品内蔵配線板。
  7. 　前記電子部品には、前記接続端子と接合させるためのバンプが形成されている、
    　ことを特徴とする請求項１に記載の電子部品内蔵配線板。
  8. 　前記導体パターン層の表面が粗化されている、
    　ことを特徴とする請求項１に記載の電子部品内蔵配線板。
  9. 　前記電子部品のバンプは、回路形成面の端部に配置されている、
    　ことを特徴とする請求項７に記載の電子部品内蔵配線板。
  10. 　支持体上に金属箔が配置された積層基材における前記金属箔上に、導体パターン層を形成する工程と、
    　前記導体パターン層上の一部の領域に、所定の開口部を設けたソルダーレジスト層を形成する工程と、
    　前記ソルダーレジスト層の開口部に対応する前記導体パターン層上に接合層を設けることで、接続端子を形成する工程と、
    　前記積層基材上に、前記電子部品を該電子部品の回路形成面と前記接続端子の形成面とが向かい合うように配置し、前記電子部品と前記接続端子とを電気的に接続する工程と、
    　前記実装後の電子部品を絶縁材で被覆する工程と、
    　前記支持体を除去する工程と、
    　露出している前記金属箔を除去する工程と、を有する、
    　ことを特徴とする電子部品内蔵配線板の製造方法。
  11. 　前記接合層は前記導体パターン層と異なる金属からなる、
    　ことを特徴とする請求項１０に記載の電子部品内蔵配線板の製造方法。
  12. 　前記接合層は半田からなる、
    　ことを特徴とする請求項１１に記載の電子部品内蔵配線板の製造方法。
  13. 　前記電子部品を前記絶縁材で被覆した後、前記絶縁材に貫通孔を設け、スルーホール導体を形成する工程をさらに有する、
    　ことを特徴とする請求項１０に記載の電子部品内蔵配線板の製造方法。
  14. 　前記導体パターン層は、電解めっきにより形成される、
    　ことを特徴とする請求項１０に記載の電子部品内蔵配線板の製造方法。
  15. 　前記電子部品には、前記接続端子と接合させるためのバンプが形成されている、
    　ことを特徴とする請求項１０に記載の電子部品内蔵配線板の製造方法。
  16. 　前記導体パターン層の形成後、前記ソルダーレジスト層を形成する前に、前記導体パターン層の表面を粗化する工程をさらに有する、
    　ことを特徴とする請求項１０に記載の電子部品内蔵配線板の製造方法。
  17. 　前記電子部品の実装後、前記接続端子の周りに絶縁性樹脂を充填する工程をさらに有する、
    　ことを特徴とする請求項１０に記載の電子部品内蔵配線板の製造方法。
  18. 　前記電子部品のバンプは、回路形成面の端部に配置されている、
    　ことを特徴とする請求項１５に記載の電子部品内蔵配線板の製造方法。
PCT/JP2009/054585 2008-11-06 2009-03-10 電子部品内蔵配線板及びその製造方法 Ceased WO2010052942A1 (ja)

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