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WO2009138138A3 - Procédé de fabrication de puces - Google Patents

Procédé de fabrication de puces Download PDF

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Publication number
WO2009138138A3
WO2009138138A3 PCT/EP2008/066593 EP2008066593W WO2009138138A3 WO 2009138138 A3 WO2009138138 A3 WO 2009138138A3 EP 2008066593 W EP2008066593 W EP 2008066593W WO 2009138138 A3 WO2009138138 A3 WO 2009138138A3
Authority
WO
WIPO (PCT)
Prior art keywords
chip
membrane
producing chips
detached
chips
Prior art date
Application number
PCT/EP2008/066593
Other languages
German (de)
English (en)
Other versions
WO2009138138A2 (fr
Inventor
Torsten Kramer
Matthias Boehringer
Stefan Pinter
Hubert Benzel
Matthias Illing
Frieder Haag
Simon Armbruster
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Priority to CN2008801291702A priority Critical patent/CN102026909B/zh
Priority to JP2011508802A priority patent/JP5119361B2/ja
Priority to EP08874259.8A priority patent/EP2285733B1/fr
Priority to US12/736,721 priority patent/US8389327B2/en
Publication of WO2009138138A2 publication Critical patent/WO2009138138A2/fr
Publication of WO2009138138A3 publication Critical patent/WO2009138138A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00349—Creating layers of material on a substrate
    • B81C1/0038—Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/0191—Transfer of a layer from a carrier wafer to a device wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Micromachines (AREA)
  • Pressure Sensors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un procédé de fabrication de puces (1, 2), lequel procédé consiste d'abord à réaliser au moins une membrane (11, 12) dans la couche superficielle d'un substrat de semi-conducteur (10), ladite membrane recouvrant une cavité (13). Le procédé consiste ensuite à intégrer la fonctionnalité de la puce (1, 2) dans la membrane (11, 12) et à retirer la membrane (11, 12) du substrat en sandwich afin de séparer la puce (1, 2). Selon l'invention, la face arrière de la puce est métallisée lors d'un processus de galvanisation avant que la puce (1, 3) ne soit extraite du substrat en sandwich.
PCT/EP2008/066593 2008-05-14 2008-12-02 Procédé de fabrication de puces WO2009138138A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2008801291702A CN102026909B (zh) 2008-05-14 2008-12-02 用于制造芯片的方法
JP2011508802A JP5119361B2 (ja) 2008-05-14 2008-12-02 チップの製造のための方法
EP08874259.8A EP2285733B1 (fr) 2008-05-14 2008-12-02 Procédé de fabrication de puces
US12/736,721 US8389327B2 (en) 2008-05-14 2008-12-02 Method for manufacturing chips

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102008001738A DE102008001738A1 (de) 2008-05-14 2008-05-14 Verfahren zur Herstellung von Chips
DE102008001738.8 2008-05-14

Publications (2)

Publication Number Publication Date
WO2009138138A2 WO2009138138A2 (fr) 2009-11-19
WO2009138138A3 true WO2009138138A3 (fr) 2010-05-27

Family

ID=41212370

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2008/066593 WO2009138138A2 (fr) 2008-05-14 2008-12-02 Procédé de fabrication de puces

Country Status (6)

Country Link
US (1) US8389327B2 (fr)
EP (1) EP2285733B1 (fr)
JP (1) JP5119361B2 (fr)
CN (1) CN102026909B (fr)
DE (1) DE102008001738A1 (fr)
WO (1) WO2009138138A2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009027180A1 (de) 2009-06-25 2010-12-30 Robert Bosch Gmbh Mikromechanisches Element sowie Verfahren zu dessen Herstelllung
DE102009046081B4 (de) 2009-10-28 2021-08-26 Robert Bosch Gmbh Eutektische Bondung von Dünnchips auf einem Trägersubstrat
WO2012069078A1 (fr) 2010-11-23 2012-05-31 Robert Bosch Gmbh Connexion eutectique de puces minces sur un support de substrat
DE102015102453A1 (de) * 2015-02-20 2016-08-25 Heraeus Deutschland GmbH & Co. KG Bandförmiges Substrat zur Herstellung von Chipkartenmodulen, Chipkartenmodul, elektronische Einrichtung mit einem derartigen Chipkartenmodul und Verfahren zur Herstellung eines Substrates
DE102024200057A1 (de) 2024-01-04 2025-07-10 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zum Herstellen eines Halbleiterbauteils und Mikrospiegelanordnung

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5391257A (en) * 1993-12-10 1995-02-21 Rockwell International Corporation Method of transferring a thin film to an alternate substrate
WO2003083930A1 (fr) * 2002-03-28 2003-10-09 Commissariat A L'energie Atomique Procede de manipulation de couches semiconductrices pour leur amincissement
DE10246053A1 (de) * 2002-10-02 2004-04-15 Robert Bosch Gmbh Verfahren und Substratchip
WO2007104443A1 (fr) * 2006-03-14 2007-09-20 Institut Für Mikroelektronik Stuttgart Procédé pour produire un circuit intégré

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69632950T2 (de) * 1996-07-31 2005-08-25 Stmicroelectronics S.R.L., Agrate Brianza Integrierte Mikrostrukturen aus Halbleitermaterial und ein Verfahren zu deren Herstellung
DE10350036B4 (de) 2003-10-27 2014-01-23 Robert Bosch Gmbh Verfahren zum Vereinzeln von Halbleiterchips und entsprechende Halbleiterchipanordnung
CN1280178C (zh) * 2004-12-17 2006-10-18 华东师范大学 Mems电控动态增益均衡器芯片的制备方法
CN101228790A (zh) 2005-07-21 2008-07-23 皇家飞利浦电子股份有限公司 使得用户能够选择协同内容的协同装置及其方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5391257A (en) * 1993-12-10 1995-02-21 Rockwell International Corporation Method of transferring a thin film to an alternate substrate
WO2003083930A1 (fr) * 2002-03-28 2003-10-09 Commissariat A L'energie Atomique Procede de manipulation de couches semiconductrices pour leur amincissement
DE10246053A1 (de) * 2002-10-02 2004-04-15 Robert Bosch Gmbh Verfahren und Substratchip
WO2007104443A1 (fr) * 2006-03-14 2007-09-20 Institut Für Mikroelektronik Stuttgart Procédé pour produire un circuit intégré

Also Published As

Publication number Publication date
JP2011520625A (ja) 2011-07-21
CN102026909A (zh) 2011-04-20
CN102026909B (zh) 2013-11-20
JP5119361B2 (ja) 2013-01-16
EP2285733A2 (fr) 2011-02-23
WO2009138138A2 (fr) 2009-11-19
US20110151620A1 (en) 2011-06-23
DE102008001738A1 (de) 2009-11-26
US8389327B2 (en) 2013-03-05
EP2285733B1 (fr) 2018-07-25

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