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WO2009126952A2 - Procédé d'assemblage de nanoéléments à large échelle, permettant de réaliser des interconnexions de circuit à l'échelle nanométrique, et diodes - Google Patents

Procédé d'assemblage de nanoéléments à large échelle, permettant de réaliser des interconnexions de circuit à l'échelle nanométrique, et diodes Download PDF

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Publication number
WO2009126952A2
WO2009126952A2 PCT/US2009/040346 US2009040346W WO2009126952A2 WO 2009126952 A2 WO2009126952 A2 WO 2009126952A2 US 2009040346 W US2009040346 W US 2009040346W WO 2009126952 A2 WO2009126952 A2 WO 2009126952A2
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substrate
template
nanotubes
assembly
nanotube assembly
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WO2009126952A3 (fr
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Srinivas Sridhar
Evin Gultepe
Dattatri Nagesha
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Northeastern University China
Northeastern University Boston
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Northeastern University China
Northeastern University Boston
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Publication of WO2009126952A3 publication Critical patent/WO2009126952A3/fr
Anticipated expiration legal-status Critical
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00031—Regular or irregular arrays of nanoscale structures, e.g. etch mask layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • G11C13/025—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
    • H10K71/125—Deposition of organic active material using liquid deposition, e.g. spin coating using electrolytic deposition e.g. in-situ electropolymerisation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/07—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/0183—Selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/491—Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • SWNT single walled carbon nanotubes
  • conventional conductors e.g., copper wires
  • SWNT have a large current capacity, as high as 10 9 A cm “2 (Yao et al.), or a mobility as high as 100,000 cm 2 /Vs (Durkop et al.).
  • a key challenge in utilizing SWNT and other nanoelements in nanoscale electronics is to develop their application in large scale devices.
  • SWNT-related manufacturing is mainly divided into two types: growing SWNT into a device, and assembling prefabricated SWNT into a device. All methods of growing SWNT require high temperature synthesis (Bethune et al., Kong et al.), and in most methods nanotubes need a post process for cleaning, cutting and sorting to reach a narrow size distribution as well as for purification to eliminate the impurities (Sinha et al.).
  • post-synthesis assembly methods permit arranging nanotubes in a desired position without the need of high temperatures. Assembly methods also allow the choice of SWNT (e.g., commercially available SWNT) having properties suitable for the desired application.
  • SWNT e.g., commercially available SWNT
  • Different assembly methods that have been investigated so far include magnetic field (Long et al.) and electric field assisted assembly (Dimaki et al., Li et al., Seo et al., Chan et al., and Makaram et al.).
  • previously available methods lack the scalability needed for high-rate manufacturing. For devices such as memories, assembly of the nanoelements needs to be performed over at least millimeter- square areas.
  • One aspect of the invention is a method of fabricating an assembly of nanoelements in three dimensions.
  • the method includes the steps of: a) providing an electrically insulating template in which to assemble the nanoelements; b) contacting the template with a liquid suspension of the nanoelements; and c) applying a voltage between a substrate attached to the template and the suspension.
  • the template has a first surface, a second surface, and a plurality of nanoscale tunnels that connect between openings at the surfaces.
  • the applied voltage causes nanoelements from the suspension to migrate into the tunnels by electrophoresis or dielectrophoresis.
  • the method can be carried out at ambient temperatures and can be used to form nanoelement assemblies covering large areas of over 1 mm .
  • the nanoelements are single walled carbon nanotubes.
  • the assembly includes an electrically conductive substrate attached to an electrically insulating template containing a plurality of nanoscale tunnels traversing between openings at first and second surfaces, and a plurality of nanoelements disposed within the tunnels.
  • the nanoelements are single walled carbon nanotubes.
  • the assembly forms an electrical interconnect for nanoscale electronic applications.
  • the assembly functions as a Schottky diode or a p-n junction diode. In other embodiments, the assembly functions as a biosensor.
  • Yet another aspect of the invention is a microelectronic device that contains the nanoelement assembly.
  • the device can be used, for example, as a memory, a switch, a microprocessor, an emitter, a solar cell, a display, or a biosensor.
  • Still another aspect of the invention is a method of fabricating such an electronic device. The method includes the steps of providing an electronic device containing the nanoelement assembly and applying a contact layer to the template, whereby an electrically conductive pathway is established between the substrate and the contact layer through the nanoelement assembly.
  • FIG. 1 shows a schematic representation of a process of SWNT assembly according to the invention.
  • a positive electrode is attached to a silicon substrate, which is attached to the underside of an alumina template, while a Pt-Ir wire in the SWNT suspension is used as the counter electrode.
  • Figure 2 shows a schematic representation of one embodiment of a nanotube assembly according to the invention, with an equivalent electrical component diagram shown at the right.
  • Figures 3A and 3B show scanning electron micrographs of assembled SWNT in an anodic alumina array: Fig. 3A is a top view, and Fig. 3B is a cross-sectional view.
  • the top layer is a contact layer of sputtered Au.
  • the scale bars are 120 nm.
  • Figure 4A shows I-V measurements of two different Si substrate-alumina template assemblies.
  • the square data points represent a connection between SWNT assembled in the alumina template and a silicon substrate below the template.
  • the round data points represent a control without assembled SWNT, and showing no current.
  • Fig. 4B shows the current density as a function of voltage for a bulk Si-alumina assembly containing no nanotubes (triangles) and a Si-alumina assembly containing SWNT (squares).
  • the inventors have developed a method for assembling SWNT and other nanoelements into nanoporous templates utilizing electric field assisted assembly carried out at ambient temperatures.
  • the method is scalable to at least several cm and forms electrical connections capable of carrying high current density suitable for nanoscale electronics.
  • an electrically insulating template 10 is provided or prepared.
  • the template is porous at the nanometer scale, and its porous nature is utilized to provide a preferred pathway in which the nanoelements will assemble in an appropriate electrical field.
  • the template has a first surface 12, a second surface 14, and a plurality of nanoscale tunnels 15 that connect between openings at the first and second surfaces.
  • the first surface of the template is in contact with an adjacent substrate 20, which contains a conducting or semiconducting material that provides electrical contact with the nanoelements.
  • the substrated is coated on a different surface with a layer of conducting material 40 serving as an electrical contact.
  • the template is contacted at its second surface with a liquid suspension 30 containing nanoelements 35 or a mixture of nanoelements for assembly; the nanoelements are suspended in a solvent.
  • Suitable solvents can be organic or inorganic solvents having a surface tension that is not greater than that of ethanol. Ethanol is a preferred solvent.
  • a voltage is applied between the substrate attached to the template (or electrical contact 40) and the suspension of nanoelements via suspension electrode 50 using voltage source 60.
  • the substrate serves as one electrode, and a Pt or Pt-Ir wire or a metallic sheet or other structure placed into the suspension serves as the counter electrode.
  • the substrate can serve as the anode and the wire as the cathode, or alternatively the substrate can serve as the cathode and the wire as the anode.
  • the voltage applied can be either DC, AC, or a combined DC + AC signal.
  • An applied DC or AC voltage can be in the range from 0 to 100 kV, 0 to 1 kV, or 0 to 50 V, and the AC frequency can have any value from 0 to 500 MHz or 0 to 100 MHz.
  • the applied voltage causes nanoelements from the suspension to align and migrate into the tunnels by electrophoresis or dielectrophoresis.
  • suspension electrode 50 should be such that a non-uniform electrical field is supplied over the surface of the template.
  • the electrode can be a wire or a pointed structure. Since assembly will occur over a limited range in the vicinity of the solution electrode, where the field is of sufficient strength, it may be required to move the solution electrode laterally across the template, i.e., parallel and in close proximity to the second surface, during application of the voltage to ensure uniform assembly over the entire surface of the template, or over a desired portion of the template.
  • k f Re ⁇ ( ⁇ ⁇ - ⁇ m * )/3[( ⁇ ⁇ - ⁇ m * )A + ⁇ m * ] ⁇ (Zheng et al.), where ⁇ p * and ⁇ m * are the complex permittivity of particle and medium respectively and A is the depolarizing factor given by
  • A (l - e 2 )/2e 3 [ln((l + e)/(l - e)) - 2e].
  • e is defined as e ⁇ -jl - ⁇ / a) 2 , where a and b are the major and minor axis of ellipsoid respectively.
  • Fig. 2 depicts a circuit interconnect prepared from the above described nanoassembly.
  • a layer 70 of a conductor such as gold or another metal, can be deposited onto the second surface 14 of the template to provide electrical contact with the assembled nanoelements. Examples of suitable deposition techniques are sputtering and chemical vapor deposition. Electrical contact with the other end of the nanoelement assembly is provided through contact of the nanoelements with the substrate 20 at the first surface 12 of the template. Electrical circuit contact 40 is attached to the substrate; position of the attachment can vary depending on the needs of the application.
  • Voltage source 62 which may be provided by a device that the circuit interconnect is installed in, connects electrical contacts 40 and 70 on the interconnect; the position of these contacts can be determined by the use of the interconnect and the device into which it is installed.
  • nanoscale or “nanometer scale” refers to a structure having one or more dimensions in the range from about 1 nm to 1000 nm, and is used to distinguish from microscale structures having dimensions of greater than 1 ⁇ m.
  • Suitable substrates will typically be composed of a conducting or semiconducting material, or be coated with a conducting or semiconducting material.
  • the substrate can be formed of a single homogeneous material or it can be formed from a layered assembly or other assembly of different materials.
  • the substrate may or may not contain one or more base layers or other layers, such as an electrical contact layer or a layer to provide support or structure as required for use in a device. Such a layer can extend over the entire substrate surface or a portion of the substrate surface. Any material suitable for use in nanodevices, electronics, photonics, or biosensor applications can be used in the substrate.
  • the substrate can contain silicon, silicon dioxide, a polymer, or other materials.
  • the substrate is preferably formed from a semiconductor material, such as doped silicon.
  • a base layer or electrical contact can be formed by depositing a conducting metal such as gold, silver, copper, or chromium using known methods, such as evaporation or sputtering.
  • the thickness of the base layer or contact layer, and any additional layers or regions, can be tailored to suit the desired application.
  • Conducting layers will typically be in the nanometer range, e.g., from about 1 nm to about 1000 nm, or from about 1 nm to about 500 nm, or about 50 nm to about 150 nm, and preferably in the range from about 10 nm to about 100 nm, such as about 75 nm, but may be greater depending on the application.
  • a nanoporous template is utilized to direct the assembly process in three dimensions and to provide points of contact with the substrate at a first surface of the template and with a another component, e.g., a circuit component, at a second surface of the template.
  • the template contains a plurality of continuous pores or tunnels having a diameter in the nanometer range and extending from an opening at the first surface to an opening at the second surface.
  • nanoelements such as SWNT form a continuous pathway or connection, e.g., a circuit interconnect, between the substrate and another component.
  • the template is stably adhered to the substrate and may cover all or just a portion of the substrate, depending on the application.
  • the substrate surface on which the template is disposed can have any geometry, but is preferably planar.
  • the template can have any desired geometry in a third dimension perpendicular to the surface or surface plane of the substrate, but preferably the template adopts the geometry and surface structure, including any surface texturing, of the substrate.
  • the template is planar.
  • the pores or tunnels of the template thus provide a connection in a third dimension leading away from the substrate surface, which is adjacent to the template first surface toward the connecting component, which is adjacent to the template second surface.
  • the first and second surfaces of the template can be essentially parallel, or the first and second surfaces each can have different forms, e.g., one planar and the other textured.
  • both template surfaces are planar and essentially parallel.
  • the template is fabricated from a material that is poorly conducting or essentially non- conducting. This serves to orient the electrical field during assembly so as to direct the migration of nanoelements into the template pores.
  • a template for use in the invention can be prepared from, for example, aluminum oxide (alumina), titanium oxide, silicon oxide, nonconducting silicon, or a polymer.
  • a variety of known nanofabrication techniques are available for fabricating a nanotemplate for use in the invention. See, e.g., Rabin et al., Matsumoto et al., and Gultepe et al.
  • the template can be fabricated by depositing a layer of desired material upon the substrate followed by a process such as photolithography, e-beam lithography, chemical etching, or an electrochemical process such as anodization to produce the pore structures. Pore structure and template morphology can be evaluated, for example, by electron microscopy or atomic force microscopy.
  • a preferred fabrication method for the template is to anodize an Al film in the presence of 5 wt% oxalic acid, followed by soaking in a chromic-phosphoric acid solution, and repeated anodization in oxalic acid (Gultepe et al.).
  • This process results in a hexagonally ordered array of tunnels having approximatetly 30 nm diameter, and extending through the entire thickness of the resulting Al 2 O 3 layer, e.g., about 500 nm. Pore diameter can be enlarged as desired, e.g., to about 80 nm, by soaking the template in 5% phosphoric acid.
  • any available method can be used that is capable of establishing a plurality of nanoscale tunnels.
  • the method can involve electron beam lithography (see Danelon et al., use of electron beam to prepare 50 nm holes in silicon nitride membranes; see also Chang et al., use of electron beam to prepare 50-200 nm holes in Si and Si oxide layers), electron beam lithography with reactive ion etching (see Storm et al., 20-200 nm holes in Si oxide), ion beam lithography, photolithography, or nanoimprint lithography.
  • electron beam lithography see Danelon et al., use of electron beam to prepare 50 nm holes in silicon nitride membranes; see also Chang et al., use of electron beam to prepare 50-200 nm holes in Si and Si oxide layers
  • electron beam lithography with reactive ion etching see Storm et al., 20-200 nm holes in Si oxide
  • ion beam lithography photolithography
  • nanoimprint lithography nanoimprint lithography
  • the template contains a plurality nanoscale passageways (e.g., pores, channels, or tunnels, hereinafter generically referred to as "tunnels") providing a connecting space between a first surface of the template and a second surface of the template.
  • the tunnels have a diameter in the nanometer ranges, such as less than 1000 nm, less than 100 nm, less than 50 nm, less than 30 nm, or about 10-100 nm, 10-50 nm, 20-80 nm, or 1-10 nm.
  • the length of the tunnels is generally determined by the thickness of the template, and can be any desired length, such as 10, 20, 30, 50, 80, 100, 200, 250, 500, 1000 nm or longer.
  • Nanoscale tunnels in the template can be oriented so as to provide preferred pathways for nanoelement assembly.
  • the tunnel orientation can be, for example, essentially vertical (e.g., perpendicular to the first and/or second surfaces of the template), extending continuously from one face of the template to the other.
  • the tunnels can have any desired orientation with respect to one another.
  • the tunnels can be essentially parallel to one another or can have different orientations.
  • the tunnel openings can form a regular pattern or array, or can be distributed at random or according to any desired arrangement.
  • the surface area of the first and second surfaces of the template can be in any desired range, but generally will be at least 0.1, 1, 2, 5, 10, 50, 100, 500, or 1000 or more mm 2 .
  • the current carrying capacity will be proportional to the template surface area (i.e., area of the first and/or second surfaces) as well as to the number and density of nanoelements bridging between the substrate and the connecting component, and thus also on the tunnel density (number per template surface area as well as cross-sectional area of tunnels per template surface area).
  • any nanoelements can be assembled within the tunnels of a suitable template, provided that the nanoelements are either metallic, semiconducting, charged, or have dielectric properties that allows them to become charged in an electric field, so that they are capable of aligning and migrating by electrophoresis or dielectrophoresis.
  • a mixture of different nanoelements having such properties also can be used. While nanoelements having various geometries (such as particulate, spherical, cylindrical, or tubular) will be suitable, their size should be somewhat smaller than the tunnel diameter of the template so as to permit assembly within the tunnels.
  • nanoelements are nanotubes such as carbon nanotubes, single walled carbon nanotubes (SWNT), multiwalled carbon nanotubes, and nanospheres or nanobeads such as polystyrene or latex nanobeads.
  • SWNT are preferred due to their high conductivity.
  • SWNT can be semiconducting or metallic, or a mixture thereof.
  • a nanotube mixture used in the methods and devices of the invention preferably contains metallic SWNT.
  • the above described method can be used to produce a three-dimensional nanoelement assembly, such as a circuit interconnect.
  • the assembly includes an electrically conductive substrate attached to an electrically insulating nanoporous template.
  • the template contains a plurality of nanoscale tunnels providing a pathway between openings at first and second surfaces of the template and a plurality of nanoelements assembled within the tunnels.
  • the nanoelements are SWNT.
  • the nanoelement assembly creates a three dimensional conductive pathway leading from the substrate to an electrical contact vertically removed from the substrate.
  • the assembly forms an electrical interconnect for nanoscale electronic applications.
  • the interconnect When the interconnect includes a junction between a semiconducting substrate (e.g., p or n doped silicon) and metallic nanoelements (e.g., metallic SWNT), it functions as a Schottky diode.
  • a p-n junction diode can be formed from the junction between p or n doped silicon and semiconducting SWNT.
  • the assembly can function as a biosensor.
  • nanotubes or nanoparticles in the assembly can be derivatized with probes such as polynucleotides (including nucleic acids and oligonucleotides), polypeptides (including peptides and proteins), antibodies (including polyclonal, monoclonal, single chain antibodies, single domain antibodies, or other recombinant antibodies), or pharmaceutical agents.
  • probes such as polynucleotides (including nucleic acids and oligonucleotides), polypeptides (including peptides and proteins), antibodies (including polyclonal, monoclonal, single chain antibodies, single domain antibodies, or other recombinant antibodies), or pharmaceutical agents.
  • Such assemblies can be used to detect biomolecules of interest in a sample, for example by causing an alteration of the conductivity or other electrical properties of the interconnect.
  • kits containing one or more components of the invention together with packaging material and instructions for using the components.
  • a kit contains a substrate, a nanoporous template, and a suspension of nanoelements which the user assembles into a nanoassembly.
  • a kit contains a substrate with a bound nanoporous template, and the user supplies his own nanoelement solution.
  • a kit according to the invention is a nanoelement assembly containing a substrate and an attached nanoporous template containing assembled nanoelements.
  • the kit also provides instructions for installing the assembly in a device provided by the user.
  • a further embodiment of a kit includes a nanoporous template and a nanoelement solution. The user supplies a substrate, e.g., contained within the user's device, attaches the template to the substrate and uses the nanoelement suspension to prepare an assembly in the user's device.
  • nanoelements such as SWNT can be assembled vertically into nanoscale tunnels in a template by the combination of electrophoresis and dielectrophoresis.
  • the method has many advantages, including mild conditions of assembly, use of post production or commercially available SWNT, high rate and large scale of assembly, and the integration of SWNT into silicon technology. It is also possible to attach aluminum oxide templates to Si after anodization if necessary, for example to avoid exposure to acidic environments (Jung et al.).
  • large scale assembly of SWNT on the order of one million elements over a one centimeter square area, can be achieved.
  • the strength of the connection established through the assembled SWNT is similar to the connection through nanotubes grown in place on Si.
  • This assembly technique can be applied to make SWNT interconnects that integrate with Si microelectronics, such as in field emission displays and memory devices.
  • Nanoporous Alumina Template Porous alumina nanotemplates were prepared on 0.1 x 0.1 cm 2 n-doped Si substrates (3-7
  • Ordered nanoporous alumina templates were prepared by two step anodization (Matsuda et al., Li et al.) of the Al surface on the Si chip in 5 wt% oxalic acid. Anodization was carried out at 5C under a constant 40 V DC potential until the whole Al layer was consumed (approx. 12 min). The resulting aluminum oxide barrier layer was removed by soaking in 5 wt% phorphoric acid for 40 min. The process produced a periodic, hexagonally-ordered nanoporous layer with pore diameter about 40 nm and thickness around 1 ⁇ m. The total area of alumina array was 0.4 cm 2 .
  • Negatively charged SWNT (Nantero, MA) were used for assembly into an alumina template prepared as described in Example 1.
  • the SWNT solution was prepared in ethanol, and assembly occurred under 10V DC together with 10V AC at 10MHz.
  • a schematic of the assembly process can be seen in Fig. 1.
  • the counter electrode was moved constantly to achieve assembly over large surface areas.
  • a pointed wire counter electrode was used for the assembly. This form of counter electrode can approach the template much closer, and the resulting electric field magnitude consequently is larger. The non-uniformity of the electric field is another reason for choosing a pointed electrode.
  • Example 3 Characterizaation of a Three-Dimensional Assembly of SWNT The SWNT assembly from Example 2 was studied using scanning electron microscopy
  • the current passing between the top and bottom layer of the assemby through assembled SWNT was also measured (Fig. 4A).
  • the upper surface of the alumina template was sputtered with a 15 nm thick Au layer to form an electrical connection between all the SWNT on the surface.
  • the I-V measurement was carried out using a parameter analyzer with a probe station by attaching one electrode to the Au layer and the other to the Si surface at the bottom of the template.
  • the I-V curve of assembled SWNT showed a Schottky diode type behavior.
  • the I-V characteristics of a Schottky diode can be estimated by using the thermionic emission model (Cheung et al.).
  • the practical non-ideal diode is usually modeled as a series combination of a diode and a resistor, R.
  • the SWNT used for assembly were a mixture of semiconducting and metallic types. Although calculations showed the force on the metallic SWNT is two orders of magnitude greater than on semiconducting SWNT, because of bundling of nanotubes, both types assembled into the tunnels. However the current passed preferentially over the metallic nanotubes because they are the lower resistant path, and also because there is no applied gate voltage. Hence, the observation of a Schottky barrier between Si and m-SWNT was consistent with theoretical predictions.
  • An aluminum oxide nanoporous template attached to a Si substrate was prepared by a method similar to that in Example 1 (see Gultepe et al.).
  • the resulting template contained a hexagonal array of tunnels having a diameter of about 75-80 nm, with a template thickness of 250 nm, as determined by SEM.
  • a suspension of 50 nm polystyrene beads was applied to the upper surface of the template.
  • a DC voltage of 10 V was applied across the template (positive at the bottom of the template), producing a zeta potential of approximately -40 mV on the beads.

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Abstract

Des nanoéléments, comme des nanotubes de carbone à une seule paroi par exemple, sont assemblés en trois dimensions de façon à former un modèle à l'échelle nanométrique sur un substrat, au moyen de procédés d'électrophorèse et de diélectrophorèse à température ambiante. La relation courant-tension indique que des interconnexions robustes entre le substrat et un nanotube, qui véhiculent des courants mA, sont établies à l'intérieur des pores du modèle. Le procédé est adapté pour un assemblage rapide, en trois dimensions et à large échelle, d’un million de nanotubes par centimètre carré dans des conditions non sévères. Des interconnexions de circuit réalisées suivant le procédé peuvent être utilisées pour des applications électroniques à l'échelle nanométrique.
PCT/US2009/040346 2008-04-11 2009-04-13 Procédé d'assemblage de nanoéléments à large échelle, permettant de réaliser des interconnexions de circuit à l'échelle nanométrique, et diodes Ceased WO2009126952A2 (fr)

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