WO2009125361A1

WO2009125361A1 - Display data channel lock-up prevention

Info

Publication number: WO2009125361A1
Application number: PCT/IB2009/051487
Authority: WO
Inventors: Denis Coulon; Guillaume Bertrand; Arnaud Dartevelle
Original assignee: NXP BV
Current assignee: NXP BV
Priority date: 2008-04-08
Filing date: 2009-04-08
Publication date: 2009-10-15
Anticipated expiration: 2010-10-08

Abstract

The present application relates to an apparatus configured to prevent display data channel lock-ups. The apparatus comprises connecting elements configured to connect the apparatus to at least a display data channel. The apparatus comprises an analyzer configured to analyze at least one signal of the display data channel. The analyzer is configured to control at least one display data channel switch depending on the analyzed signal of the display data channel such that lock-up situations in the display data channel are prevented.

Description

Display Data Channel Lock-up Prevention

DESCRIPTION

TECHNICAL FIELD OF THE INVENTION

The present application relates to an apparatus comprising connecting elements configured to connect the apparatus with at least a display data channel. The present application relates also to a transmitter and receiver, comprising said apparatus and to a system. Furthermore, the present application relates to a computer and monitor as well as to a method for preventing lock-up situations and a computer readable medium having a computer program stored thereon.

BACKGROUND OF THE INVENTION

A Display Data Channel (DDC) is a digital connection between a display and a computer, in particular, between a computer display and a graphics adapter. The DDC allows the display to communicate its specifications to the graphics adapter. The standard was created by the Video Electronics Standards Association (VESA). The DDC link is typically carried on three pins - data, clock and ground - in a 15 -pin Video Graphics Array (VGA) connector, a Digital Visual Interface (DVI) connector or a High Definition Multimedia Interface (HDMI) connector. The current version of DDC, called DDC2B (version 2, level B) is based on the Inter Integrated Circuit (I²C) bus. This is a serial bus that allows multiple bus masters, although DDC2B allows only one master - the graphics adapter. The monitor (e.g. a Cathode Ray Tube (CRT) or a Liquid Crystal Display (LCD)) comprises a memory, like a read-only memory (ROM) chip, programmed by the manufacturer with information about the graphics modes that the respective monitor can display. The data in the ROM can be held in a standard format called Extended Display Identification Data (EDID). This format is also defined by VESA. Generally, the DDC is implemented into any digital video interface (HDMI, DVI, Display Port...) in order to access the EDID embedded in the monitor, wherein the monitor may act as a receiver. Fig. 1 shows a first embodiment of a DDC implementation according to prior art. As can be seen from Fig. 1, a transmitter 2 is in communication with a receiver 4 via two interconnections 6 and 8. The transmitter 2 may be a computer or a graphics adapter, like a STB, DVD or the like. The receiver 4 may be a display comprising at least one memory 10, such as a ROM, provided to store the EDID data. Furthermore, reference sign 8 indicates a unidirectional communication, like a digital video interface, while reference sign 6 indicates the bidirectional DDC channel. In Fig. 2, a second embodiment of a DDC implementation according to prior art is shown. In this embodiment, a DDC buffer, in particular a digital video buffer 12 is arranged between a transmitter 2 and a receiver 4. Fig. 3 shows a third embodiment of a DDC channel implementation according to prior art. As can be seen from this Figure, two transmitters 2.1 and 2.2 are provided. These transmitters 2.1 and 2.2 are connected to a receiver via a DDC switch 14, in particular a digital video switch. The DDC switch 14 comprises two switches 16.1 and 16.2 being arranged for connecting the transmitters 2.1 and 2.2 via the respective channels, i.e. digital video interface 8 and DDC 6, with the receiver 4 in a desired way.

DDC is a bi-directional serial communication protocol based on one data bit and one clock (up to 400 kHz). In a digital video switch and/or buffer, it is generally implemented as a pass-through. Issues occur since there is no information of the current direction. This may cause a lock-up situation if the loop-back paths are always activated. This results in erroneous message, short-cut and/or lost of communication. The problem occurs when a Zero is driven either by the transmitter (master) or the receiver (slave). Indeed, the DDC buffers are open drain pads with an external pull-up (as for I2C).

The problem is shown in Fig. 4. Fig. 4 shows a fourth embodiment of a DDC implementation according to prior art. As stated above, the DDC link is typically carried on three pins, wherein for simplicity reasons merely the clock pin 6.2 or clock signal 6.2 and the data pin 6.1 or data signal 6.1 are depicted in this embodiment. Block 20 may be a switch and/or a buffer.

As can be further seen from this Figure, the data signal 6.1 or data pin 6.1 comprises two loop-back paths 18.1 and 18.2. The first loop-back path 18.1 is provided for the master-slave direction while the second loop-back path 18.2 is provided for the reverse direction, i.e. slave-master direction. The arrows indicate the lock-up situation, which causes erroneous message, short-cut and/or lost of communication.

So, it is necessary to find a way to disable or release one of loop-back paths 18.1 or 18.2 in the two following situations. In the first situation, the transmitter or master drives. In this case the path slave to master has to be disabled. In the second situation, the receiver or slave drives. In this case the path master-to-slave has to be disabled.

According to prior art, for these preventing lock-up situations, DDC switches are used which use "Slightly different "legal" low voltage" levels between the input and the output of each repeater. Such an embodiment according to prior art is shown in Fig. 5. For instance, in the master-slave direction or transmitter-receiver direction, the loop-back the path 18.1 is activated and the other loop-back path 18.2 has to be de-activated. In other words, the transmission of any Zero value is disabled.

This analogue solution, according to prior art, consist to shift the output low level, generally 200 mV, and to design the input/output pin 7 of the receiver 4 in order that the loop-back path 18.2 is activated only when the low supply voltage is under the sum of the legal low level voltage and the defined level shift. The same mechanism is implemented on the opposite side. The level shift is generated by additional level shifters 22.1 and 22.1, which are analogue components.

However, the solution according to prior art has the drawback of high required effort, and thus, high costs for implementing the respective components, like the analogue level shifters. Furthermore, such an apparatus has to be designed for each different technology in a different way. In addition, the prior art solution is not robust regarding noise and process, voltage and temperature (PVT) variations.

Therefore, it is one object of the present application to provide a simple apparatus for preventing lock-up situations in a DDC. A further object is to provide a technology-independent apparatus. Another object is to provide an apparatus which is robust regarding noise and PVT variations.

SUMMARY OF THE INVENTION

These and other objects are solved by an apparatus comprising connecting elements configured to connect the apparatus to at least a display data channel. The apparatus comprises an analyzer configured to analyze at least one signal of the display data channel. The analyzer is configured to control at least one display data channel switch depending on the analyzed signal of the display data channel such that lock-up situations in the display data channel are prevented.

The present apparatus can be used in any application comprising a display data channel (DDC). For connecting the apparatus according to the present application, the apparatus comprises connecting elements. The connecting elements may be configured to receive signals and transmit signals, which are transmitted via the DDC.

Contrary to expectation it is found according to the present application that an analyzer and a switching device may ensure a particular simple and technology-independent apparatus for preventing lock-up situations. The analyzer may be configured to analyze at least one signal transmitted via the DDC. In particular, the analyzer may receive a signal of the DDC at least via the connecting elements. It shall be understood that further components may be arranged between the connecting elements and the analyzer.

Furthermore, the analyzer may determine which entity, like the master or slave drives the line. In other words, the analyzer determines how a DDC switch must be switched for preventing lock-up situations. In dependence of the analysis results, the analyzer controls the DDC switch such that lock-up situations do not occur. For instance, a suitable control signal or the like can be generated by the analyzer.

In other words, in order to use standard IO pads and then to avoid tuning low levels supply voltages, which requires specific analogue design, which may be costly in time, technology dependent and riskily if PVT variations are not the expected ones, a simple solution is provided, which comprises substantially two modules: a DDC analyzer and a DDC switch instantiated in the DDC slave, like a digital slave.

The present application provides for an apparatus, which is simple, technology-independent, robust regarding noise and PVT variations and allows to implement an internal slave (EDID for example) in a digital video switch/buffer.

According to a further embodiment, the display data channel may comprise at least a data pin, a clock pin, and/or a ground pin. These pins or lines are configured to transmit the respective signals, such as a data signal and a clock signal. While data signals can be transmitted bidirectional between a master and a slave, the clock signal can be transmitted unidirectional from a master to a slave. A simple realization of a DDC, which is suitable for a plurality of different interfaces, can be ensured.

Furthermore, the analyzer may comprise at least one over-sampling device, which may be configured to over-sample at least a data signal of the display data channel and/or a clock signal of the display data channel. It may be advantageous to over-sample both the clock signal and the data signal being transmitted via the respective lines or pins of the DDC. The apparatus may comprise any suitable oscillator device for generating a suitable frequency signal required for over-sampling these signals.

In a further embodiment of the present application, the analyzer may comprise at least one filtering device being connected to the over-sampling device. By filtering and over-sampling especially the clock signal and the data signal, suitable signals for further analyzing processes can be obtained. According to another embodiment, the over-sampling device and the filtering device can be formed as a single over-sampling and filtering module, wherein the over-sampling and filtering module may comprise a glitch filter and stability detector. By way of example, such a single module can be implemented by using a field programmable gate array (FPGA). However, it shall be understood that any suitable component, being suitable for implementing the required function, in particular, digitally, can be employed. Synergies can be exploited by using a single module for over-sampling and filtering. For determining simply the wanted information, i.e. which entity, like the master or slave, drives the data line, the analyzer may comprise at least one protocol analyzer configured to analyze the display data channel protocol. By analyzing the DDC protocol, the required information can be determined in a simple manner. In particular, a digital interpretation is possible. Furthermore, the protocol analyzer may comprise an edge detection device arranged for analyzing the display data channel protocol. Such a device is particular suitable for analysis and may be suitable in connection with a glitch filter and stability detector.

In another embodiment of the present application, the protocol analyzing may be configured to generate at least one output enable signal. The protocol analyzer may be configured is configured to transmit the output enable signal to the display data channel switch for disabling one of the loop-back paths. In other words, depending on the performed analysis, one loop-back path of the data line can be activated while the other loop-back path can be disabled. It may be excluded that both loop-back paths are activated at the same time. By way of example, the DDC switch may comprise suitable switching elements, which activate or release the respective loop-back paths depending on the output enable signal, like a digital signal. According to a further embodiment of the present application, the apparatus may be implemented in the digital domain. A digital realization of the present apparatus can be implemented easily with reduced effort and is robust regarding noise and PVT variations.

A further aspect of the present application is transmitter, comprising at least one apparatus as stated above. This includes an additional device, like a buffer and or switch which is connectable to the transmitter.

A further aspect of the present application is receiver, comprising at least one apparatus as stated above. This includes an additional device, like a buffer and or switch which is connectable to the receiver. Another aspect of the present application is a system comprising at least one transmitter, at least one receiver, and at least one apparatus as stated above. It may be possible that the system comprises a receiver and/or a transmitter as stated above.

A further aspect of the present application is a computer comprising a transmitter as stated above. Another aspect of the present application is a monitor comprising the receiver as stated above.

A further aspect of the present application is a method for preventing display data channel lock-up comprising detecting a signal of the display data channel. The method comprises analyzing the detected signal of the display data channel. The method comprises controlling a display data channel switch depending on analyzing results of the detected signal of the display data channel such that lock-up situations in the display data channel are prevented.

Another aspect of the present application is a computer readable medium having a computer program stored thereon. The computer program comprises instructions operable to cause a processor to perform the above mentioned method.

These and other aspects of the present patent application become apparent from and will be elucidated with reference to the following figures. The features of the present application and of its exemplary embodiments as presented above are understood to be disclosed also in all possible combinations with each other. BRIEF DESCRIPTION OF THE DRAWINGS

In the Figures show:

Fig. 1 a first embodiment of a DDC implementation according to prior art, Fig. 2 a second embodiment of a DDC implementation according to prior art, Fig. 3 a third embodiment of a DDC implementation according to prior art,

Fig. 4 a fourth embodiment of a DDC implementation according to prior art, Fig. 5 a sixth embodiment of a DDC implementation according to prior art, Fig. 6a first embodiment of the system according to the present application, Fig. 7 a second embodiment of the system according to the present application,

Fig. 8 a third embodiment of the system according to the present application, Fig. 9 a flowchart of an embodiment of the method according to the present application,

Fig. 10 a flowchart of a display data channel finite state machine.

Like reference numerals in different figures indicate like elements.

DETAILED DESCRIPTION OF THE DRAWINGS

In the following detailed description of the present application, exemplary embodiments of the present application will describe and point out a simple and cost-efficient apparatus for preventing lock-up situations in a data display channel, which is technology independent. Or in other words, in the following, an electronic device will be elucidated which comprises lock-up prevention means for preventing lock-up on a Display Data Channel (DDC), the lock-up prevention means comprising a DDC analyzer and a DDC switch. Fig. 6 shows a first simplified embodiment of the system according to the present application. For avoiding repetition, already stated components, like transmitter 2 or receiver 4 are not explained again. The shown system comprises an apparatus 24. The apparatus 24 is connected to a data line 6.1 or loop-back paths 18.1 and 18.2 respectively and a clock line 6.2 via connecting elements 21.1 and 21.2. More particularly, according to the present embodiment, a DDC switch 26 is connected to the respective lines and arranged between the transmitter 2 and the receiver 4. A possible realization of the DDC switch 26 will follow subsequently.

Furthermore, the apparatus 24 comprises an analyzer 28. In turn, the analyzer 28 comprises an over-sampling device 30, a filtering device 32 and a protocol analyzer 34. Thereby, the three components 30, 32 and 34 may communicate with each other.

The analyzer 28 is configured to analyze a signal of the DDC. In particular, the data signal 36.1 and the clock signal 36.2 are received by the analyzer 28. After analyzing these signals 36.1 and 36.2, the DDC switch can be controlled by generating a suitable control signal 38, like an output enable signal. This output enable signal can be provided for enabling and disabling respectively the respective loop-back path 18.1 or 18.2. It shall be understood that, according to further variants of the present application, more than one transmitter or receiver can be arranged. Furthermore, the apparatus may be implemented within a DDC buffer or DDC switch, wherein such a component can be integrated within the transmitter or receiver. The apparatus 24 may be totally implemented in the digital domain.

In Fig. 7, a second simplified embodiment of the system according to the present application is shown. For simplicity reasons, merely apparatus 24.1 is shown. The present apparatus 24.1 comprises a DDC switch 26.1, an analyzer 28.1 and an optional internal slave 50. It shall be understood that it may be possible that a plurality of internal slaves are provided.

The DDC switch 26.1 comprises an AND gate 48, an inverter 44 and two switching elements 46.1 and 46.2. Each of the switching elements comprises three inputs, wherein one input is provided to connect the data pin or line 18.1 or 18.2 respectively while the second input is configured to receive the output enable signal 38 and the third terminal 47.1 or 47. 2 is arranged for receiving a logical One or a high signal.

In addition, the analyzer 28 comprises an over-sampling and filtering module 40 being connected to a protocol analyzer 34.1. The over-sampling and filtering module 40 receives the clock signal 36.2 and data signal 36.1 while the protocol analyzer 34.1 outputs the output enable signal 38 and a data output signal 42. Moreover, the protocol analyzer 34.1 is in communication with the internal slave 50. Furthermore, a frequency signal 52 for oversampling is additional received by the analyzer 28.1.

In the following, the functioning of the depicted embodiment will be elucidated. In case data should be transmitted via the DDC, the over-sampling and filtering module 40 receives a clock signal 36.2 and a data signal 36.1. These signals 36.1 and 36.2 are oversampled and filtered by the over-sampling and filtering module 40. For instance, this module 40 may be implemented on a field programmable gate array (FPGA). The resulting signals are forwarded to the protocol analyzer 34.1 for analyzing the DDC protocol. The protocol analyzer 34.1 is configured to detect whether the master or the slaves drives the data line 6.1. Then it is possible to generate an output enable signal 38 and send this signal 38 to the switch module 26.1, which is in charge to disable one of the loop-back paths 18.1 or 18.2. Due to the provided inverter 44, merely one of the switching elements 46.1 and 46.2 can be activated for passing the data signal while the other one is disabled avoiding data throughput. In case the internal slave 50 wants to drive the data line, a data output signal 42 can be generated and transmitted to the master via the arranged AND gate 48. An advantage of this digital solution is to have an internal DDC slave (for example embedded EDID memory) in addition of the external one.

This digital solution (~0.5 Kgates), allows to use only standard open-drain pads and is completely technology independent. As mentioned above, the application may reside in a digital solution to prevent lock-up. There are many ways to over sample data. One example of an implementation and demonstration on a FPGA is shown in Figure 8. Figure 8 gives some details on the over- sampling module applied on both DDC clock and data. It is a combination of a glitch filter and a stability detector 64 comprising buffers 60, an AND array 56 and a latch 58. In addition, edge detection is implemented by module 54 in order to follow the DDC protocol (Start-stop detection, DDC clock edges). The sample frequency 52 can be generated for example by a Free Running Oscillator (not shown). Thereby, a 20MHz frequency may be enough. The DDC input 62 is received by the present module while a filtered DDC signal is output. Fig. 9 shows a flowchart of an embodiment of the method according to the present application. In a first step 102, the method can be started. Then, in a next step 104, a signal transmitted via the display data channel is detected. More particularly, the data signal and the clock signal of the DDC can be detected and fed to an analyzer.

In step 106, the detected signal, like the data signal and the clock signal of the DDC, can be analyzed by the analyzer. For instance, the detected signal can be over-sampled and filtered. Subsequently, a protocol analyzer may analyze the protocol and determine the desired information, i.e. which entity drives the data line.

Subsequently, a DDC switch can be controlled depending on the analyzing results such that lock-up situations are prevented (step 108). The analyzer may generate a digital enabling signal for activating the respective loop-back path and for disabling the other loop-back path.

In a last step 110, the method can be terminated. For instance, it can be detected that there are no signals on the DDC. Fig. 10 shows a flowchart of a display data channel finite state machine. The first step 202 represents the idle state after which the method can be started. In the next step 204, the address can be got (get addr), while the output enable signal comprises the logical value One. Furthermore, an acknowledgement (ack addr) is generated and the output enable signal can be set to logical Zero (step 206). Then, in step 208, the data can be put on the line (put data) while the output enable signal remains logical Zero. An acknowledgement (get data ack) can be got in step 210 and the output enable signal is set to the logical value One. Afterwards, it can be returned to step 208 or it can be stopped in step 212.

Moreover, in step 214, an index can be got (get index) and the output enable signal is set to the logical value One. In the next step 216, an acknowledgement can be generated (index ack) and the output enable signal is set to the logical value Zero. Subsequently, in step 218, data can be got (get_data) and the output enable signal is set in turn to the logical value One. Then, an acknowledgement (data ack) is generated and the output enable signal can be set to logical Zero (step 220). From this step 220, it can be returned to step 218. The steps 204, 208, 214 and 218 are performed depending on the clock signal.

It is remarked that the scope of protection of the application is not restricted to the embodiments described herein. Neither is the scope of protection of the application restricted by the reference symbols in the claims. The word 'comprising' does not exclude other parts than those mentioned in a claim. The word 'a(n)' preceding an element does not exclude a plurality of those elements. Means forming part of the application may both be implemented in the form of dedicated hardware or in the form of a programmed general- purpose processor. The application resides in each new feature or combination of features.

Claims

Display Data Channel Lock-up Prevention CLAIMS:

1. An apparatus (24, 24.1), comprising: connecting elements (21.1, 21.2) configured to connect the apparatus (24, 24.1) to at least a display data channel (6), an analyzer (28, 28.1) configured to analyze at least one signal of the display data channel (6), and wherein the analyzer (28, 28.1) is configured to control at least one display data channel switch (26, 26.1) depending on the analyzed signal of the display data channel (6) such that lock-up situations in the display data channel (6) are prevented.

2. The apparatus (24, 24.1) according to claim 1, wherein the display data channel (6) comprises at least one of:

A) data pin (6.1),

B) clock pin (6.2), C) ground pin.

3. The apparatus (24, 24.1) according to claim 1, wherein the analyzer (28, 28.1) comprises at least one over-sampling device (30) configured to over-sample at least one of: A) data signal (36.1) of the display data channel (6), B) clock signal (36.2) of the display data channel (6).

4. The apparatus (24, 24.1) according to claim 3, wherein the analyzer (28, 28.1) comprises at least one filtering device (32) being connected to the over-sampling device (30).

5. The apparatus (24, 24.1) according to claim 4, wherein the over-sampling device (30) and the filtering device (32) are formed as a single over-sampling and filtering module (40), wherein the over-sampling and filtering module (40) comprises a glitch filter and stability detector (64).

6. The apparatus (24, 24.1) according to claim 1, wherein the analyzer (28, 28.1) comprises at least one protocol analyzer (34, 34.1) configured to analyze the display data channel protocol.

7. The apparatus (24, 24.1) according to claim 6, wherein the protocol analyzer (34, 34.1) comprises an edge detection device (54) arranged for analyzing the display data channel protocol.

8. The apparatus (24, 24.1) according to claim 6, wherein the protocol analyzer (28, 28.1) is configured to generate at least one output enable signal (38), and - the protocol analyzer (28, 28.1) is configured is configured to transmit the output enable signal (38) to the display data channel switch (26, 26.1) for disabling one of the loop-back paths (18.1, 18.2).

10. The apparatus (24, 24.1) according to claim 1, wherein the apparatus (24, 24.1) is implemented in the digital domain.

10. A transmitter, comprising at least one apparatus according to claim 1.

11. A receiver, comprising at least one apparatus according to claim 1.

12. A system, comprising: at least one transmitter, at least one receiver, and at least one apparatus according to claim 1.

13. A computer, comprising a transmitter according to claim 10.

14. A monitor, comprising the receiver according to claim 11.

15. A method for preventing display data channel lock-up, comprising: detecting a signal of the display data channel (6), analyzing the detected signal of the display data channel (6), controlling a display data channel switch (26, 26.1) depending on analyzing results of the detected signal of the display data channel (6) such that lock-up situations in the display data channel (6) are prevented.

16. A computer readable medium having a computer program stored thereon, the computer program comprising: - instructions operable to cause a processor to perform a method according to claim 14.